Elemental patterns of verification strategies

Verification activities are intended to reduce the costs of system development by identifying design errors before deploying the system. However, subcontractors in multifirm projects are motivated to implement locally cost‐effective verification strategies over verification strategies that benefit the main contractor. Incentivizing verification activities is one mechanism by which the contractor can motivate subcontractors to implement verification strategies desirable to the contractor. Prior work on mathematical models of verification in systems engineering has neither explored optimal verification strategies nor incentives in multi‐firm projects. In this paper, we present a modeling concept for determining optimal verification strategies in multi‐firm projects. Our models are belief‐based, which means that contractors and subcontractors incorporate their at times limited knowledge about true verification state through a probabilistic assessment of possible states. We develop an initial two‐level model, where one contractor directly works with multiple subcontractors at the next lower level. This model is then extended to a general network model with multiple, multilevel contractor‐subcontractor relationship. We derive solution algorithms that characterize the optimal verification strategies and incentives for each of the firms. Our work contributes to the systems engineering literature by laying the foundation for the study of incentives as a mechanism to align verification activities in multi‐firm systems engineering projects.

In current practice, a verification strategy (VS) is planned by considering various uncertainties at the beginning of a development program. All relevant uncertainties are expected to be calibrated to facilitate the evaluation of the planned verification strategies. However, not all calibration information about uncertainties may be available at the beginning and some additional activities to discover unknown uncertainties may be necessary. This paper presents a set‐based planning (SBP) methodology for designing and executing system verification strategies under knowable uncertainty (KU). Building on a Bayesian network model of verification and correction activities (CAs), we introduce preparation activities that quantify KU, enabling dynamic planning as new information becomes available. Using a notional satellite communication instrument as a case study, we compare SBP against traditional static planning across scenarios with varying estimation errors in likelihood ratio (LR) values. Results show that SBP consistently achieves higher expected values, with substantial gains when CAs have low success rates. The findings provide practical guidance on when dynamic verification planning yields value and lay the groundwork for extensions to broader classes of uncertainty.

Verification planning is a sequential decision-making problem that specifies a set of verification activities (VAs) and correction activities (CAs) at different phases of system development. While VAs are used to identify errors and defects, CAs also play important roles in system verification as they correct the identified errors and defects. However, current planning methods only consider VAs as decision choices. Because VAs and CAs have different activity spaces, planning a joint verification-correction strategy (JVCS) is challenging, especially for large-scale systems. Here, we introduce a UCB-based tree search approach to search for near-optimal JVCSs. First, verification planning is simplified as repeatable bandit problems and an upper confidence bound rule for repeatable bandits (UCBRBs) is presented with the optimal regret bound. Next, a tree search algorithm is proposed to search for feasible JVCSs. A tree-based ensemble learning model is also used to extend the tree search algorithm to handle local optimality issues. The proposed approach is evaluated on the notional case of a communication system.

This paper presents an automatic video based face verification and recognition system by Support Vector Machines (SVMs). Faces as training samples are automatically extracted from input video sequences in real-time by LUT-based Adaboost and are normalized both in geometry and in gray level distribution after facial landmark localization via Simple Direct Appearance Model (SDAM). Two different strategies for multi-class face verification and recognition problems with SVMs, one-vs-all and one-vs-another, are discussed and compared in details. Experiment results over 100 clients are reported to demonstrate the effectiveness of SVM on video sequences.

The challenges of system on a chip (SoC) verification is becoming increasingly complex as submicron process technology shrinks die size, enabling system architects to include more functionality in a single chip solution. A functional defect refers to the feature sets, protocols or performance parameters not conforming to the specifications of the SoC. Some of the functional defects can be solved by software workarounds but some require revisions of silicon. The revision of silicon not only costs millions of dollars but also impacts time to market, quality, customer commitments. Working silicon for the first revision of the SoC requires a robust module, chip and system verification strategy to uncover the logical and timing defects before tapeout. Different techniques are needed at each level (module, chip and system) to complete verification. In addition verification should quantify with a metric at every hierarchy to assess functional holes and address it. Verification metric can be a combination of code coverage, functional coverage, assertion coverage, protocol coverage, interface coverage and system coverage. A successful verification strategy also requires the test bench to be scalable, configurable, support reuse of functional tests, integration with tools and finally linkage to validation. The scope of this paper will discuss the verification strategy and pitfalls used in verification strategy and finally make recommendations for successful strategy.

We demonstrate a new modelling technique that facilitates the description and the formal verification of timing properties of concurrent systems, such as asynchronous digital hardware. We utilise a process algebra and its associated automatic verification system and construct models and verification strategies using them. Utilising the hierarchical nature of our approach, these techniques may then be applied to larger systems, such as asynchronous circuits of commercial complexity. The modelling techniques introduced permit four distinct classes of objects, namely system components, assumed constraints on their behaviour, properties requiring proof and behaviour refinements, all to be modelled by a process. We illustrate this approach by modelling the necessary timing relationships required for the correct operation of asynchronous micropipline stages and then verifying that the resulting behaviour is correct. Finally, we demonstrate how the same models are used to make some observations about the performance and the timing properties of such designs.

Currently, microvascular data are almost exclusively deposited in scholarly journals. With the increasing availability of molecular data and the construction of genomic databases, a need arises to organize physiological data in a more accessible format. The microcirculation is a functional system that spans all organ systems and shares certain characteristics of organization with metabolic pathways, which have successfully been organized around genomic information for several prokaryotes. Here, we present a web-based research and teaching tool (http:@hsc.Virginia.EDU/medicine/basic-sci/biomed/l ey/) that covers a small aspect of microcirculatory physiology, the leukocyte adhesion cascade. Currently, the site is organized in a flat-text mode with hypertext links to GenBank, Medline, and online journals where available. The web-based research and education tool is useful for graduate student education, and as a research resource for genetic researchers interested in gene function and for physiologists and biomedical engineers interested in the molecular basis of the leukocyte adhesion cascade. Our effort is intended to be a beginning toward a distributed database for the microcirculation (microcirculation physiome. see http://www.bme.jhu.edu/news/microphys). We invite all microvascular researchers to provide annotations and comments to make the research and teaching tool more useful to the scientific community.

This plan supersedes, but does not replace, the previous Waste Receiving and Processing/Solid Waste Engineering Development Program Plan. In doing this, it does not repeat the basic definitions of the various types or classes of development activities nor provide the rigorous written description of each facility and assign the equipment to development classes. The methodology described in the previous document is still valid and was used to determine the types of verification efforts required. This Engineering Verification Program Plan will be updated on a yearly basis. This EVPP provides programmatic definition of all engineering verification activities for the following SWOC projects: (1) Project W-026 - Waste Receiving and Processing Facility Module 1; (2) Project W-100 - Waste Receiving and Processing Facility Module 2A; (3) Project W-112 - Phase V Storage Facility; and (4) Project W-113 - Solid Waste Retrieval. No engineering verification activities are defined for Project W-112 as no verification work was identified. The Acceptance Test Procedures/Operational Test Procedures will be part of each project`s Title III operation test efforts. The ATPs/OTPs are not covered by this EVPP.

System verification and validation are important activities in the software development process aiming at testing the software system in various quality aspects. The purpose is to investigate the important characteristics of the verification and validation activities in the software development process in an organization. A qualitative research method is employed in order to facilitate the assessment and understanding of a testing key area regarding the software development process. The methodology and results could act as input to other organizations, which are likely to have other important characteristics than the ones included in this study. The main characteristics were identified in the analysis and it was concluded that the results could facilitate further process improvements in the organization.

With the development of the nuclear technology, the instrumentation and control (I&C) systems have evolved from the analog systems to the current state-of-the-art digital systems. It has been reported that China has recently developed the digital systems based on Field Programmable Gate Array (FPGA) in CAP1400 nuclear power plant. And the lack of methods in the verification and validation work of the FPGA systems has become an important issue. This thesis describes the basic principles of FPGA, and the development process of FPGA. And then, the thesis proposes an effective improved method—formal verification, describing three methods of formal verification in detail, namely theorem proof, model checking, and equivalence proof. Describing the FPGA verification methodology and pointing out the shortcomings of traditional simulation, comparing the formal verification and traditional simulation verification in terms of complexity, timing, and applications. We also discussed the importance of formal verification method in FPGA. We selected the temperature and power control chip based on FPGA as an example, using System Verilog Assertions (SVA) method of model checking, and verifying the SRAM controller module and the internal calculation module. Through the analysis of the results, this paper proved the feasibility of formal verification methods in the instrumentation and control system of nuclear power plants, and provided some references of verification work for other system chips in instrumentation and control of nuclear power plant in the future work. The thesis showed that verification engineers can use the formal verification method based on SVA to verify the robustness of the system quickly and accurately. This method improves the controllability and observability which are the main drawbacks of the traditional simulation verification. It also avoids several issues in the debug process of traditional simulation verification, improving the accuracy and completeness of the chip verification.

The verification of safety-critical software systems has many challenges, such as the complex language constructs in embedded software. This paper addresses the verification problem of software systems using bitwise operations, and we present an extension to the Theta open-source formal verification framework. Our goal is to integrate bitvectors and bitwise operations in the abstraction-refinement-based formal verification methods in Theta. Supporting bitvectors is a step towards the verification of industrial embedded software systems. We extended the language support in Theta with formal semantics. In addition, the new language constructs and operators are transformed into the formal language inside Theta. We also need new algorithms to solve the verification problem: we implemented Newton-style refinement algorithms in Theta to verify software with bitvectors and bitwise operators efficiently.

Performing formal verification of concurrent systems involves partial order logics (here MSO with partial orders) for the specification of properties or of the concurrent system itself. A common structure for the verification of concurrent systems is so-called pomset. A pomset is a multiset of partially ordered events. The partial order relation describes causal dependencies of events. We propose a new word based model, namely Pre-Post-Pomset, making the exploration of pomsets space possible. In this paper, our new model stands to be a general model in the sense that some classical models used in the specification of concurrent systems (Synchronized product of systems, Mazurkiewicz traces or parallel series) can be specified within. Besides its general aspect, our model offers decidability results on the verification problem according to an MSO formula on pomsets.

Verification is a hard task, but much progress has been achieved recently. Many verification problems have been shown decidable by reducing them to model-checking finite state transition systems. Verification of infinite state transition systems has achieved tremendous progress too, by showing that many particular cases were themselves decidable, such as timed automata [1] or some forms of pushdown-automata [4]. However, the demand for verification is growing fast, and the industrial needs go far beyond the verification of decidable systems.

Introducing a new strategy for verification of System On Chip (SoC) using system Verilog. System Verilog provides a great platform for verification. The OOPs concept in System Verilog make it more reliable. There are many existing SoC verification methods are available. But most of them are not that much efficient. So here we are planning to introduce a new verification strategy that takes many of the positive characteristics of the existing strategies and mixes them together to have an efficient and perfect strategy by using the advantages of System Verilog.

Due to the rapid advances in algorithms, VLSI design and computer technology, security systems based on speaker recognition are on the verge of commercial success. In this thesis, an improved strategy for Text Tndependent Automatic Speaker Verification (TI-ASV) system based on Malayalam has been proposed and results are observed. The system performs on Gaussian Mixture Model (GMM) technique with cepstral based features. Different speech pre-processing techniques like pre-emphasis filtering, frame blocking and windowing have been used to process the speech utterances. MFCC, ΔMFCC and ΔΔMFCC have been used to extract the features. Speaker identification is performed using Continuous Hidden Markov Model. The performance is analyzed in terms of Percentage Correctness (PC) and accuracy. An application with Graphical User Interface (GUI) is also developed for security purposes using the system. The system is developed using the framework of Hidden Markov Model Tool Kit (HTK).