Bottlenecks in multimedia processing with SIMD style extensions and architectural enhancements

Many important multimedia applications contain a significant fraction of reduction operations. Although, in general, multimedia applications are characterized for having high amounts of Data Level Parallelism, reductions and accumulations are difficult to parallelize and show a poor tolerance to increases in the latency of the instructions. This is specially significant for /spl mu/-SIMD extensions such as MMX or AltiVec. To overcome the problem of reductions in /spl mu/-SIMD ISAs, designers tend to include more and more complex instructions able to deal with the most common forms of reductions in multimedia. As long as the number of processor pipeline stages grows, the number of cycles needed to execute these multimedia instructions increases with every processor generation, severely compromising performance. The paper presents an in-depth discussion of how reductions/accumulations are performed in current /spl mu/-SIMD architectures and evaluates the performance trade-offs for near-future highly aggressive superscalar processors with three different styles of /spl mu/-SIMD extensions. We compare a MMX-like alternative to a MDMX-like extension that has packed accumulators to attack the reduction problem, and we also compare it to MOM, a matrix register ISA. We show that while packed accumulators present several advantages, they introduce artificial recurrences that severely degrade performance for processors with high number of registers and long latency operations. On the other hand, the paper demonstrates that longer SIMD media extensions such as MOM can take great advantage of accumulators by exploiting the associative parallelism implicit in reductions.

Modern out-of-order processors have increased capacity to exploit instruction level parallelism (ILP) and memory level parallelism (MLP), e.g., by using wide superscalar pipelines and vector execution units, as well as deep buffers for inflight memory requests. These resources, however, often exhibit poor utilization rates on workloads with large working sets, e.g., in-memory databases, key-value stores, and graph analytics, as compilers and hardware struggle to expose ILP and MLP from the instruction stream automatically. In this paper, we introduce the IMLP (Instruction and Memory Level Parallelism) task programming model. IMLP tasks execute as coroutines that yield execution at annotated long-latency operations, e.g., memory accesses, divisions, or unpredictable branches. IMLP tasks are interleaved on a single thread, and integrate well with thread parallelism and vectorization. Our DSL embedded in C++, Cimple, allows exploration of task scheduling and transformations, such as buffering, vectorization, pipelining, and prefetching. We demonstrate state-of-the-art performance on core algorithms used in in-memory databases that operate on arrays, hash tables, trees, and skip lists. Cimple applications reach 2.5× throughput gains over hardware multithreading on a multi-core, and 6.4× single thread speedup.

Utilizing speculative execution alone to extract instruction level parallelism in the presence of branches has performance limitation .The fundamental limitation is that speculation eliminates dependencies between instructions and branches, but does not remove the branches themselves. To overcome this drawback, predicate execution is investigated. Predicate or guarded execution enables a compiler to eliminate branches from the instruction stream. As a result, many of the difficulties introduced by branches can be eliminated. This paper addresses the architectural support required to accomplish predicate execution. The architectural extensions required to provide efficient support for the predicated execution are discussed.

SIMD extensions have gained widespread acceptance in modern microprocessors as a way to exploit data-level parallelism in general-purpose cores. Popular SIMD architectures (e.g. Intel SSE/AVX) have evolved by adding support for wider registers and datapaths, and advanced features like indexed memory accesses, per-lane predication and inter-lane instructions, at the cost of additional silicon area and design complexity. This paper evaluates the performance impact of such advanced features on a set of workloads considered hard to vectorize for traditional SIMD architectures. Their sensitivity to the most relevant design parameters (e.g. register/datapath width and L1 data cache configuration) is quantified and discussed. We developed an ARMv7 NEON based ISA extension (ARGON), augmented a cycle accurate simulation framework for it, and derived a set of benchmarks from the Berkeley dwarfs. Our analyses demonstrate how ARGON can, depending on the structure of an algorithm, achieve speedups of 1.5x to 16x.

Recently, the opportunity to use FPGA in the field of embedded computer system has increased. The cost for development of system using FPGA is quite high. Therefore, to easily develop the embedded system using FPGA, the development cost should be reduced, and it can be reduced by limiting the development of the dedicated circuit to the truly required part of the system and by using soft-core processor. If the performance of the soft-core processor improves, the development cost can be suppressed, since we can expect that the amount of the dedicated circuit can be reduced. Furthermore, even in the field of embedded system, the opportunity for data parallel processing such as image processing is increasing. We consider that it is important merit of soft-core processor with SIMD extension that the computation performance can be optimized to the system by changing the number of parallel computing units according to the application. However, when optimizing the performance of soft-core processor, it is an obstacle that the software for soft-core processor needs to be changed every time we change the number of computing units. Thus, vector processing facility should provide the scalability that means the number of computing units can be changed without changing the program code. In this paper, we propose a scalable vector extension for RISC-V ISA and its programming method.

Recently, the opportunity to use FPGA in the field of embedded computer system has increased. However, the development cost using FPGA is quite high. We can reduce the cost by limiting the development of the dedicated circuit to the essenially required part of the system and by using soft-core processor together. If the performance of the soft-core processor improves, the development cost can be suppressed, since the amount of the dedicated circuit can be reduced. Furthermore, even in the field of embedded system, the opportunity for data parallel processing such as image processing is increasing. We consider that it is important merit of soft-core processor with SIMD extension that the computation performance can be optimized to the system by changing the number of parallel computing units according to the application. However, it is an obstacle that the software for soft-core processor needs to be changed every time we change the number of computing units. Thus, vector processing facility should provide the scalability that means the number of computing units can be changed without changing the program code. In this paper, we develop a RISC-V based soft-core processor with the scalable vector extension.

The available instruction level parallelism allowed by current register file organizations is not always fully exploited by media processors when running a multimedia application. This paper introduces a novel register file organization, called multi-shared register file, that eliminates this superfluous instruction scheduling flexibility by reducing the number of read and write ports and partitioning the register file in a special ring structure. A parameterized generic VLIW architecture is used to explore different configurations of our proposed register file structure in terms of estimated silicon area, minimum clock period, estimated power consumption, and multimedia task processing performance. Moreover, a metric highly related to multimedia applications is introduced to study trade-offs between hardware cost and performance. The results show that by substituting a monolithic register file with an equivalent multi-shared register file, the estimated area and the power consumption are considerably reduced at the cost of a negligible performance degradation.

In this paper we focus on common data reorganization operations such as shuffle, pack/unpack, swap, transpose, and layout transformations. Although these operations simply relocate the data in the memory, they are costly on conventional systems mainly due to inefficient access patterns, limited data reuse and roundtrip data traversal throughout the memory hierarchy. This paper presents a two pronged approach for efficient data reorganization, which combines (i) a proposed DRAM-aware reshape accelerator integrated within 3D-stacked DRAM, and (ii) a mathematical framework that is used to represent and optimize the reorganization operations. We evaluate our proposed system through two major use cases. First, we demonstrate the reshape accelerator in performing a physical address remapping via data layout transform to utilize the internal parallelism/locality of the 3D-stacked DRAM structure more efficiently for general purpose workloads. Then, we focus on offloading and accelerating commonly used data reorganization routines selected from the Intel Math Kernel Library package. We evaluate the energy and performance benefits of our approach by comparing it against existing optimized implementations on state-of-the-art GPUs and CPUs. For the various test cases, in-memory data reorganization provides orders of magnitude performance and energy efficiency improvements via low overhead hardware.

This paper presents the results of a study of dynamic parallel media processing using Speculative Broadcast Loop (SBL), a speculative run-time looplevel parallelization method. Due to processing regularity, multimedia applications typically contain extensive parallelism. Subword parallelism methods are commonly used to support data parallelism between independent loop iterations in inner loops, but much of the data parallelism in media processing resides in outer loops and cannot be supported with subword parallelism. Larger-scale parallel methods are needed to enable use of the full range of data parallelism in multimedia. Because static parallel compilation methods are often unable to recognize all parallelism at compile time, a run-time method is assumed for the speculative execution of potentially parallel loops. The SBL run-time method combines SIMD parallelism with large-scale speculation for supporting data parallelism in multimedia.

9 - Parallel Processors

SIMD (Single Instruction Multiple Data) extensions are acceleration components integrated in general processor, aiming at extracting instruction and data level parallelism of multimedia and scientific calculation programs. Currently, most of the automatic vectorization methods for SIMD architectures are based on innermost loops. Inner loop vectorization is the common approach for auto-vectorization. This method has been used for many years and its efficiency is widely accepted by people. In this paper, we put forward a better method than inner loop vectorization for some loop nests, which is outer loop vectorization. Outer loop vectorization method means vectorizing the outer loop directly. It can extract more data level parallelism and make the most use of the spatial locality to improve the program efficiency than the inner one which is more suitable for some loop nests. This paper presents the realization. In this paper, we first revisit the preliminary analysis of outer loop vectorization based on Open64 complier. And then, data type conversion and code generation is presented in detail. Finally, we propose two optimization methods, capable of boosting the performance of outer loop vectorization to achieve the acceleration of 20% on average, 50% at most.

Digital media are sensory-rich, multimodal, and often highly interactive. An extensive collection of theories and models within the field of media psychology assume the multimodal nature of media stimuli, yet there is current ambiguity as to the independent contributions of visual and auditory content to message complexity and to resource availability in the human processing system. In this article, we argue that explicating the concepts of perceptual and cognitive load can create progress toward a deeper understanding of modality-specific effects in media processing. In addition, we report findings from an experiment showing that perceptual load leads to modality-specific reductions in resource availability, whereas cognitive load leads to a modality-general reduction in resource availability. We conclude with a brief discussion regarding the critical importance of separating modality-specific forms of load in an increasingly multisensory media environment.

The appearance of simultaneous multithreading (SMT) processors, offering instruction-level parallelism and increasing hardware resources utilization, permits the execution of various instructions streams at the same time. A particular case is the Intel SMT implementation (Hyper-Threading Technology) where a processor can execute two instructions streams independently. Due to hardware resources sharing in a Hyper-Threading processor, both instruction streams can contend for the same execution resources depending on the instruction execution units utilization.As other works in this area have demonstrated, we have observed that the system throughput can be improved when the execution resources used by each thread are contemplated in their scheduling. Starting from the evaluation results, we propose a Thread Coloring philosophy that designs a way to manage information about resources utilization (hardware and software resources) per each thread. This policy permits the scheduler to select threads that will perform better with less resource contention, besides including OS upper layers in the resource management. The proposed Thread Coloring scheme establishes the bases of processor and OS cooperation, sharing resources utilization information and providing a form of controlling logical processor thread assignment taking into account possible resource contention.

In recent years, the success of Internet and World Wide Web, and the growing feasibility of image and video compression techniques have pushed multimedia into mainstream computing. These requirements necessitate new and modified hardware architectures enabling realtime multimedia applications. Three methods have been proposed for enhancing multimedia architectures namely dedicated processors, media processors and multimedia extensions for general-purpose processors. Multimedia extended instruction set is an efficient solution for public and widely used computers, because it offers a solution with less expense and high flexibility. In this paper, we propose an enhanced multimedia extended instruction set for the DLX RISC processor. The enhancement is shown by implementing typical multimedia applications. Our synthesis and simulation results show an average speedup of 3.3 for these applications at a expense of 3% growth in chip area.

In multiprocessors, performance improvement is typically achieved by exploring parallelism with fixed granularities, such as instruction-level, task-level, or data-level parallelism. We introduce a new reconfiguration mechanism that facilitates variations in these granularities in order to optimize resource utilization in addition to performance improvements. Our reconfigurable multiprocessor QuadroCore combines the advantages of reconfigurability and parallel processing. In this article, a unified hardware-software approach for the design of our QuadroCore is presented. This design flow is enabled via compiler-driven reconfiguration which matches application-specific characteristics to a fixed set of architectural variations. A special reconfiguration mechanism has been developed that alters the architecture within a single clock cycle. The QuadroCore has been implemented on Xilinx XC2V6000 for functional validation and on UMC’s 90nm standard cell technology for performance estimation. A diverse set of applications have been mapped onto the reconfigurable multiprocessor to meet orthogonal performance characteristics in terms of time and power. Speedup measurements show a 2--11 times performance increase in comparison to a single processor. Additionally, the reconfiguration scheme has been applied to save power in data-parallel applications. Gate-level simulations have been performed to measure the power-performance trade-offs for two computationally complex applications. The power reports confirm that introducing this scheme of reconfiguration results in power savings in the range of 15--24%.