Development of RISC-V Based Soft-core Processor with Scalable Vector Extension for Embedded System

Recently, the opportunity to use FPGA in the field of embedded computer system has increased. The cost for development of system using FPGA is quite high. Therefore, to easily develop the embedded system using FPGA, the development cost should be reduced, and it can be reduced by limiting the development of the dedicated circuit to the truly required part of the system and by using soft-core processor. If the performance of the soft-core processor improves, the development cost can be suppressed, since we can expect that the amount of the dedicated circuit can be reduced. Furthermore, even in the field of embedded system, the opportunity for data parallel processing such as image processing is increasing. We consider that it is important merit of soft-core processor with SIMD extension that the computation performance can be optimized to the system by changing the number of parallel computing units according to the application. However, when optimizing the performance of soft-core processor, it is an obstacle that the software for soft-core processor needs to be changed every time we change the number of computing units. Thus, vector processing facility should provide the scalability that means the number of computing units can be changed without changing the program code. In this paper, we propose a scalable vector extension for RISC-V ISA and its programming method.

This talk showcases the ongoing studies on the emulation of Armv8-A Scalable Vector Extension (SVE) in Armv8-A architectures. SVE is the newest SIMD instruction set for Armv8-A, featuring scalable vector lengths enabling length-agnostic programming, gather/scatter, per-lane predication, amongst others features, targeting HPC workloads. Thanks to the Arm Instruction Emulator (ArmIE), we can run SVE workloads on real hardware which, paired with dynamic binary instrumentation (DynamoRIO), enables full application tracing without the overhead found in simulators. Traces can then be analysed or fed to simulators (e.g. cache simulator) in order to extract more meaningful metrics such as percentage of vectorization, vector utilization, cache hit/miss rates, cache access latency and more. In this talk, we dive into the current workflow of SVE dynamic binary instrumentation, from the toolset to the ongoing studies and preliminary results, providing some early findings and insights along the way. The toolset encompasses ArmIE and DynamoRIO with SVE instruction and memory tracing clients as well as a simple SVE cache simulator, enabling memory studies on the generated SVE memory traces. For the evaluation, the study considers several HPC mini-and proxy-applications, focusing on SVE utilization and the impact of SVE in the memory system, for different vector lengths (128 bits up to 2048 bits).

We present the first implementation of Supersingular Isogeny Key Encapsulation (SIKE) using ARM's Scalable Vector Extension (SVE), aiming to maximize throughput. Large integer multiplications in SIKE can be accelerated by using 64-bit integer multiplication instructions available in SVE, which was not available in previous work. The main problem is at addition with carry: SVE does not natively support add-with-carry or reduced radix. We propose to handle carries using predicate instructions. As a result, 3.4 times higher throughput was obtained on Wisteria/BDEC-01 (Odyssey) powered by Fujitsu A64FX CPU compared with SIDHv3.5, an ARMv8 assembly implementation of SIKE developed by Microsoft.

Recently Arm introduced a new instruction set called Scalable Vector Extension (SVE), which supports vector lengths up to 2048 bits. While SVE hardware will not be generally available until about 2021, we believe that future SVE-based architectures will have great potential for Lattice QCD. In this contribution we discuss key aspects of SVE and describe how we implemented SVE in the Grid Lattice QCD framework.

Data-level parallelism is frequently ignored or underutilized. Achieved through vector/SIMD capabilities, it can provide substantial performance improvements on top of widely used techniques such as thread-level parallelism. However, manual vectorization is a tedious and costly process that needs to be repeated for each specific instruction set or register size. In addition, automatic compiler vectorization is susceptible to code complexity, and usually limited due to data and control dependencies. To address some of these issues, Arm recently released a new vector ISA, the scalable vector extension (SVE), which is vector-length agnostic (VLA). VLA enables the generation of binary files that run regardless of the physical vector register length. In this paper, we leverage the main characteristics of SVE to implement and optimize stencil computations, ubiquitous in scientific computing. We show that SVE enables easy deployment of textbook optimizations like loop unrolling, loop fusion, load trading or data reuse. Our detailed simulations using vector lengths ranging from 128 to 2048 bits show that these optimizations can lead to performance improvements over straightforward vectorized code of up to 1.57$$\times$$. In addition, we show that certain optimizations can hurt performance due to reduced arithmetic intensity and instruction overheads, and provide insight useful for compiler optimizers.

In this paper we propose an implementation of the fast Fourier transform (FFT) targeting the ARM Scalable Vector Extension (SVE). We performed automatic vectorization via a compiler and an explicit vectorization through code generation by SPIRAL for FFT kernels, and compared the performance. We show that the explicit vectorization of SPIRAL generated code improves performance significantly. Performance results of FFTs on RIKEN's Fugaku processor simulator are reported. With the ARM compiler SPIRAL-generated FFT kernels written in SVE intrinsic are up to 3.16 times faster than FFT kernels of FFTE written in Fortran and up to 5.62 times faster than SPIRAL-generated FFT kernels written in C.

The FPGA with Avalon Bus architecture and Nios soft-core processor developed by Altera Corporation is an advanced embedded solution for control and interface systems. A CCD data acquisition system with an Ethernet terminal port based on the TCP/IP protocol is implemented in NAOC, which is composed of a piece of interface board with an Altera's FPGA, 32MB SDRAM and some other accessory devices integrated on it, and two packages of control software used in the Nios II embedded processor and the remote host PC respectively. The system is used to replace a 7200 series image acquisition card which is inserted in a control and data acquisition PC, and to download commands to an existing CCD camera and collect image data from the camera to the PC. The embedded chip in the system is a Cyclone FPGA with a configurable Nios II soft-core processor. Hardware structure of the system, configuration for the embedded soft-core processor, and peripherals of the processor in the PFGA are described. The C program run in the Nios II embedded system is built in the Nios II IDE kits and the C++ program used in the PC is developed in the Microsoft's Visual C++ environment. Some key techniques in design and implementation of the C and VC++ programs are presented, including the downloading of the camera commands, initialization of the camera, DMA control, TCP/IP communication and UDP data uploading.

The effective use of simulation for the design and analysis of propulsion systems, and for operator training of these systems, requires a clear definition of the simulation's intended purpose and expected results. Issues such as model fidelity, computational performance and data requirements must be carefully balanced against the development effort and costs. The relative importance of each of these factors can only be determined once the purpose and expected outputs from the simulation are known.Experience with some recent marine propulsion simulation initiatives has highlighted the need for clear definitions of model requirements, especially with regard to simulation fidelity and the use of physics‐based models. Marine propulsion system simulations can be used for a variety of purposes ranging from machinery performance analysis through maneuvering and seakeeping analysis to equipment health monitoring studies. This wide range of applications, with differing requirements, provides an excellent forum for examining the influence of fidelity on simulation computational performance, data requirements, and development cost. Examples from various marine propulsion machinery simulations are used to illustrate the discussion.

A limiting performance factor for soft cores that exploit high instruction-level parallelism (ILP) is the need of a high performance multiport memory to provide data at the rate it can be consumed by the available functional units. At the same time, FPGAs contain block RAMs (BRAMs) that provide enormous bandwidth, especially when data is spread through multiple blocks of independent address spaces. We present a novel technique to cope with the multiport memory problem and increase performance in very long instruction word (VLIW) FPGA-based soft-core processors. We emulate the use of a multi-ported memory system through the use of multiple single-ported memories, which are controlled at the software level. Experimental results demonstrate that our technique can improve performance on data-driven and control-driven applications where data reuse is found. Measurements show performance improvements of up to 2.15x for a Filter benchmark, a data-driven application, and 1.25x for a Knuth-Morris-Pratt (KMP) string search, a control-driven application. These improvements are achieved while maintaining the same area of the baseline soft processor core.

To realize a highly efficient embedded system employing an enhanced soft-core processor with SIMD operations, we are developing the MIQS (MIPS Instruction processor with Quadword SIMD extension) system. Generally, in many embedded systems using FPGA and memory devices, relatively low bandwidth restricts memory access performance and the low memory performance limits the system performance even though high-performance operations are implemented on the FPGA device. We introduce a high-performance on-chip memory system on the MIQS system to reduce the number of accesses to the off-chip memory in order to improve the system performance. This paper proposes a highly efficient memory access method using a locked-cache. This paper also discusses implementation issues of the proposed method and extends the instruction set to control the locked-cache. As our preliminary evaluation to estimate the effectiveness of the on-chip memory systems, we run four application programs on two configurations of the MIQS systems, one has scratch pad memory (SPM) and the other one has an ordinal cache, respectively. The results show that the best configuration of on-chip memory varies depending on the application.

Multimedia SIMD extensions such as MMX and AltiVec speed up media processing; however, our characterization shows that the attributes of current general-purpose processors enhanced with SIMD extensions do not match very well with the access patterns and loop structures of media programs. We find that 75 to 85 percent of the dynamic instructions in the processor instruction stream are supporting instructions necessary to feed the SIMD execution units rather than true/useful computations, resulting in the underutilization of SIMD execution units (only 1 to 12 percent of the peak SIMD execution units' throughput is achieved). Contrary to focusing on exploiting more data-level parallelism (DLP), we focus on the instructions that support the SIMD computations and exploit both fine and coarse-grained instruction level parallelism (ILP) in the supporting instruction stream. We propose the MediaBreeze architecture that uses hardware support for efficient address generation, looping, and data reorganization (permute, packing/unpacking, transpose, etc.). Our results on multimedia kernels show that a 2-way processor with SIMD extensions enhanced with MediaBreeze provides a better performance than a 16-way processor with current SIMD extensions. In the case of application benchmarks, a 2-/4-way processor with SIMD extensions augmented with MediaBreeze outperforms a 4-/8-way processor with SIMD extensions. A first-order approximation using ASIC synthesis tools and cell-based libraries shows that this acceleration is achieved at a 10 percent increase in area required by MMX and SSE extensions (0.3 percent increase in overall chip area) and 1 percent of total processor power consumption.

The concept of system-on-a-chip is becoming increasingly popular for the integration of complex systems. New types of processor cores are now available that enable the designer to customize their processors for the target applications. These soft cores are not tightly coupled with the target application, and this leads to processing cores sub-optimal for their specific applications. This paper proposes a method to derive application-specific embedded processors from soft processor cores. The derivation process involves an analysis of the resources of the processing core used by the target application. Then a series of optimizations based on the analysis results are performed on an optimizable model of the processor core. We present the tool used to perform the analysis of the resources used by an application, and results from a real-world case. Then, various optimization methods are described.

The diversity of processor architectures used for High-Performance Computing (HPC) applications has increased significantly over the last few years. This trend is expected to continue for different reasons, including the emergence of various instruction set extensions. Examples are the renewed interest in vector instructions like Arm's Scalable Vector Extension (SVE) or RISC-V's RVV. For application developers, research software developers, and performance engineers, the increased diversity and complexity of architectures have led to the following challenges: Limited access to these different processor architectures and more difficult root cause analysis in case of performance issues. To address these challenges, we propose leveraging the much-improved capabilities of processor simulators such as gem5. We enhanced this simulator with a performance analysis framework. We extend available performance counters and introduce new analysis capabilities to track the temporal behaviour of running applications. An algorithm has been implemented to link these statistics to specific regions. The resulting performance profiles allow for the identification of code regions with the potential for optimization. The focus is on observables to monitor quantities that are usually not directly accessible on real hardware. Different algorithms have been implemented to identify potential performance bottlenecks. The framework is evaluated for different types of HPC applications like the molecular-dynamics application GROMACS, Ligra, which implements the breadth-first search (BFS) algorithm, and a kernel from the Lattice QCD solver DD-αAMG.

The Fujitsu A64FX ARM-based processor is used in supercomputers such as Fugaku in Japan and Isambard 2 in the UK and provides an interesting combination of hardware features such as Scalable Vector Extension (SVE), and native support for reduced-precision floating-point arithmetic. The goal of this paper is to explore performance of the Julia programming language on the A64FX processor, with a particular focus on reduced precision. Here, we present a performance study on axpy to verify the compilation pipeline, demonstrating that Julia can match the performance of tuned libraries. Additionally, we investigate Message Passing Interface (MPI) scalability and throughput analysis on Fugaku showing next to no significant overheads of Julia of its MPI interface. To explore the usability of Julia to target various floating-point precisions, we present results of ShallowWaters.jl, a shallow water model that can be executed a various levels of precision. Even for such complex applications, Julia's type-flexible programming paradigm offers both, productivity and performance.

The supercomputer “Fugaku” is an exascale manycore-based parallel system developed as a Japanese national flagship supercomputer in the FLAGSHIP 2020 Project. While “Fugaku” was ranked first for several benchmarks such as TOP500, HPCG, HPL-AI, and Graph500 in 2020, the major design concept is the application-first concept by the co-design for power efficiency and high performance. We have designed an original manycore processor based on Armv8 instruction sets with the scalable vector extension, A64FX processor, with Fujitsu, our industry partner. The system consists of 158,976 nodes with 7.6 million cores in total and a theoretical peak of 537 Peta Floating-point Operations Per Second in double-precision floating points, connected by Tofu-D interconnect. The high performance computing (HPC)-oriented design enables an extremely good performance for memory-intensive workloads thanks to HBM2 memory with breakthrough power efficiency. In this article, we present the pragmatic practice of our co-design effort for “Fugaku” followed by an overview and the performance of “Fugaku.”