Built-In Self-Test Methodology With Statistical Analysis for Electrical Diagnosis of Wearout in a Static Random Access Memory Array

Silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) have been produced by several vendors for commercial applications. SiC-MOSFET reliability was assessed using bias-temperature instability (BTI) and time-dependent dielectric breakdown (TDDB) characteristics. Here, we compared two planar SiC-MOSFET samples (A and B) from different vendors. The samples exhibited significantly different positive and negative BTI, time-dependent gate-current, TDDB lifetime statistics, and temperature dependence. These differences suggest NO (nitric oxide)-annealing variations.

We investigated the mechanisms of bias temperature instability (BTI) and time dependent dielectric breakdown (TDDB) of phase-controlled-Ni-FUSI/HfSiON that has an electrode of NiSi and Ni <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> Si. A NFET-PBTI did not degrade and the electron trap density remained low even with a higher Ni-content electrode. On the other hand, NFET-TDDB degraded with a Ni <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> Si electrode. The decrease was related to a degradation in insulator quality near the gate dielectrics/Si interface that was enhanced by a compressive mechanical strain due to the gate electrode. NBTI of PFET did not degrade with a Ni <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> Si electrode, but the main NBTI component changed from interface trap generation to hole trapping of the gate dielectrics. PFET-TDDB was improved by using NiSi and Ni <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> Si instead of p+ poly-Si. We attribute this improvement to a reduction in electron energy at the anode. Thus, the NFET: NiSi and PFET: Ni <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> Si is judged to be a superior combination for both of reliability and initial characteristics

Built-In Self Test (BIST) has been proposed as a powerful technique for addressing the highly complex testing problems of VLSI circuits. In the BIST methodology, two major problems which must be addressed are test generation and response analysis. In this paper, we present an efficient unified procedure, named three-phase cluster partitioning, to automatically synthesize a pseudo-exhaustive test generator for VLSI BIST design. Previous approaches to the problem of test generation have optimized computational efficiency at the expense of the required hardware overhead, or vice versa. Our design procedure is computationally efficient and produces test generation circuitry with low hardware overhead. The procedure minimizes the number of test patterns that are required for pseudo-exhaustive test. Based on three-phase cluster partitioning, a design generator named BISTSYN has been developed and implemented to facilitate the BIST design. The input to the design generator is a circuit description at the gate level which is viewed as a netlist. BISTSYN provides the BIST mechanisms as the output. For those conventional circuits which are extremely unsuitable for pseudo-exhaustive test, BISTSYN employs a circuit partitioning tool, named Autonomous, to partition the combinational portion of the circuit into different structural subcircuits so that each subcircuit can be pseudo-exhaustively tested. We demonstrate the effectiveness of BISTSYN by applying the method to different examples and practical VLSI designs. The detailed comparisons of our benchmark simulation results against those that would be obtained by existing techniques are also presented. >

With the steep expansion of the n-type 4H-SiC power metal-oxide-semiconductor field-effect transistor (MOSFET) market space, gate oxide reliability is gaining more and more attention. Although there exist several reports dealing with the bias temperature instability (BTI) under both positive and negative gate biases, gate oxide lifetime evaluations predominantly focus on positive gate bias time-dependent dielectric breakdown (TDDB) stresses for n-channel SiC MOSFETs. In this work we address that gap. From the negative gate bias TDDB data measured at 175 °C and at a gate oxide electric field of about 4 MV/cm, an intrinsic lifetime of 1E8 hours has been predicted, which closely matches with the results obtained from similar devices under positive gate stress. Also, in this work the correlation between failure location in a MOSFET unit cell and the failure signatures during TDDB stress have been established, and an explanation from a device physics standpoint has been provided. The identification of the failure location in the unit cell from in-situ gate leakage data without the need of physical failure analysis can turn out to be key during the early phase of a new process development activity.

Tutorial 1: Memory Technology: Reliability Challenges and Future PerspectivesAbstract: Memory technologies occupy a huge share of the semiconductor market. Despite a large plethora of memory device concepts proposed over the years, only a restricted group of them has achieved large-scale production. Reliability is one of the main aspects limiting the adoption of a memory technology by the semiconductor industry. This tutorial aims at outlining the main reliability characteristics of memory devices and the characterization techniques to assess them. Representative case studies, namely RRAM and DRAM, are provided, to review the challenges to be overcome before a memory technology is widely accepted by the industry, and to describe how the causes of reliability failure are identified and mitigated. As the pursuit of innovative memory devices and architectures is relentless and fast-paced, this tutorial also provides future perspectives on memory technology and the related reliability challenges.Tutorial 2: Reliability of Energy-Efficient Phase Change Memory Based on Novel Superlattices and NanocompositesAbstract: Today’s computing systems are reaching fundamental limits with conventional materials like silicon, and with conventional layouts that separate memory and computing. To overcome these challenges, phase change memory (PCM) technology based on chalcogenides like Ge2Sb2Te5 (GST225) hold great promise for both data storage and neuromorphic computing. However, using conventional phase change materials, PCM operation requires large power consumption and suffers from resistance drift, limiting its potential for neuro-inspired and energy-efficient data storage. In this tutorial, we will address some of these challenges in PCM devices using novel phase change nanocomposite Ge4Sb6Te7 (GST467) and GST based phase-change superlattices. We will discuss the operation of energy-efficient and neuro-inspired PCM devices demonstrating gradual change of resistance states, low power switching, and multilevel operation with low resistance drift. We will also focus on the fundamental correlation between superlattice material characteristics and PCM device performance, important to ensure reliability and robustness of such technology for low power and brain-inspired computing.Tutorial 3: Brief Introduction to Device and Circuit ReliabilityAbstract: After a brief review of selected reliability basics, we discuss the main degradation mechanisms occurring in Field-Effect Transistors (FETs). These mechanisms include SILC (Stress Induced Leakage Current), TDDB (Time-Dependent Dielectric Breakdown), BTI (Bias Temperature Instability), RTN (Random Telegraph Noise), and HCD (Hot Carrier Degradation) with the accompanying Self-Heating (SHE) and are linked with the underlying properties of defects. The effects of Mechanical Stress are also briefly reviewed. We then show that these defects play the essential role in many emerging technologies and applications, including CryoCMOS and 2D FETs, and are responsible for degradation variability in deeply-scaled devices. Finally, we show how device degradation can be accounted for in circuit simulations and demonstrate how in-depth knowledge of defect properties can be used to our advantage to design new devices and applications.Tutorial 4: 22FDX® RF/mmWave ReliabilityAbstract. The Fully Depleted Silicon on Insulator (FDSOI) technology was proven to be one of the best candidate for radio frequency (RF) and millimeter wave (mmWave) applications with lowest power consumption, lowest system footprint and the efficient electrostatic control of short channel effects. These advantages in addition with back-bias tuning and scalability knob offered by FDSOI technology give designers more freedom to explore and enhance their RF/mmWave designs. They need to push the devices at their limits to optimize and unlock best competitiveness for their IPs/designs. It results in high voltage/current stress to the devices, challenging standard technology qualification reliability models and their coverage. This tutorial will offer an overview about 22FDX® reliability effort to support the RF/mmWave design. It will include Non Conducting hot carrier injection (NCHCI) studies, off-state TDDB modeling, HCI Low Vgs modeling, Safe Operating Area methodology based on TDDB & RF/mmWave waveform analysis. The waveform analysis provides a base for assessing RF operation based on all DC reliability models and helps sizing critical RF/mmWave IPs for safe product lifetime, reducing design iterations to final product.

One of the major wearout mechanisms in modern microprocessors is time-dependent dielectric breakdown. Beyond the 28 nm technology node, time-dependent dielectric breakdown from not only the frontend-of-line and backend-of-line, but also the middle-of-line, yields a significant number of failures in VLSI circuits. In this paper, we investigate the impact of time-dependent dielectric breakdown in all phases of fabrication processes (i.e., frontend/middle/backend-of-line) on static random access memory in modern microprocessors. With the analysis of potential resistive short defect locations in a memory cell, we propose a methodology for accurately estimating memory reliability degraded by time-dependent dielectric breakdown. Using activity profiles and device-level wearout models, we also propose a method for statistically estimating the lifetime of a memory cell. Using the simulation methodology, we investigate the lifetime degradation of a memory system while taking all three time-dependent dielectric breakdown mechanisms into account.

Bias temperature instability (BTI) is a major reliability concern in the current and upcoming technologies. Current mitigation techniques mainly target circuit and system levels through reducing the stimuli that govern BTI. Such mitigation techniques typically come with non-negligible overheads, which might not be acceptable—especially in smaller technology nodes where the available design margins are tighter. Semiconductor vendors report different BTI degradations in their technology and hence circuit designers need to consider such technology features when designing for reliability. Recently, TSMC reported that BTI strongly depends on the gate length ( ${L}$ ) of transistors in their 10nm technology node. In this brief, we are the first to investigate the role that gate length dependence of BTI may play as a new degree of freedom in the design for reliability. Based on the reported data from TSMC, we propose to incorporate the gate length dependency into a state-of-the-art physics-based BTI model. Then, we propose a new method of transistor stacking that optimizes circuits (e.g., SRAM cells) with respect to on/off current ratios in which ${L}$ -dependency of BTI is taken into account. Compared to state of the art, our approach results in BTI-hardened SRAM cells with 50% better on/off current ratio along with $3\times$ better reliability at the cost of a 20% area overhead.

Aggressively scaled devices with high power density wrapped around the low thermal conductivity material in narrow space are susceptible to self-heating effect, which includes serious mutual-heating due to proximity effect in multifinger/fin FETs. Obtaining local temperature instead of equivalent lumped temperature at device/circuit level quickly is crucial for designers to accurately predict front-end-of-line reliability (i.e., hot carrier injection, bias temperature instability, and time dependent dielectric breakdown) and achieve better thermal management. In this paper, we: 1) first propose an analytical model based on multistage thermal network to address effectively the self- and mutual-heating within the device; 2) validate the multistage network and proposed analytical model by COMSOL and SPICE simulation, respectively; and 3) utilize the model to investigate local temperature rise in multifinger and multifin FETs-based inverter and ring oscillator as well as provide thermal-aware IC design guideline for self-heating and reliability optimization. The results show that the analytical multistage thermal model can predict local temperature rise and quantify nonuniform temperature difference in full-frequency range, superior to the lumped thermal model. Moreover, the model can offer quick thermal analysis at the pre-Si stage for reliability prediction and thermal-aware design.

Reversible logic is an emerging nanotechnology used in the design and implementation of nanotechnology and quantum computing with the main goal of reducing physical entropy gain. Significant work have been produced in the design of fundamental reversible logic structures and arithmetic units, and recent developments in sequential design of reversible circuits has opened new avenues in the implementation of reversible combinational circuits, such as the design and implementation of static (SRAM) and dynamic random-access memory (DRAM). In this paper, a novel 4*4 MLMR gate is presented which is used for controlling the read/write logic of a SRAM cell. Next, a reversible SRAM cell is designed and verified. Then, a novel 4*4 Reversible Decoder (RD) gate, implemented as a 2-to-4 decoder with low delay and cost is presented and verified, and its implementation shown in the construction of a 4×2 reversible SRAM array. Next, a dual-port SRAM cell is presented and verified, and its implementation in a synchronous n-bit reversible dual-port SRAM array is shown. Then, a reversible DRAM cell is presented and verified. The control logic for writing to the DRAM based on Peres gates is shown. The control logic and the DRAM cell are then implemented in a reversible 4×4 DRAM array.

A built-in self-test (BIST) methodology to test system backplanes by using BIST functionality in each of its constituent boards is presented. Since the configurations of systems change frequently, at the system level, the proposed methodology employs a simple test schedule which can be easily changed whenever the system configuration is changed. Since the boards used in such systems are designed for use in a wide variety of systems, the proposed methodology defines the test objectives to be achieved by a board's BIST circuit in terms of the board's edge pin connections, independent of the configurations of the systems in which the board may be used. It is shown that the combination of the proposed test schedule and the availability, on each board in the system, of any BIST circuit that satisfies the proposed test objectives, guarantees safe testing of faults in backplanes. A programmable test architecture and an algorithm to program the architecture to obtain BIST that satisfies the test objectives is also presented. Finally, the applicability and effectiveness of the methodology is demonstrated via its application to multiple configurations of an example system that uses a VME backplane.

SRAM used for the FPGA, requires higher stability and low power consumption. 8T SRAM cell has degraded write stability with the decreasing supply voltages. 10T SRAM cell has higher write stability because of the cut-off switch employed in the pull-up path in one of the inverters. The design of SRAM array with low power consumption and higher stability is of major importance. So, 1Kb SRAM array using 8T and 10T SRAM cells has been designed and compared for different design metrics. Write 0 and Write 1 power is lower by 1.98×, 3.52× in 10T SRAM Array than 8T SRAM Array at 0.9VDD, SS corner. Due to the usage of High-Vth transistors in 10T SRAM cell, the Read power is lower by 1.6× than 8T SRAM Array for 0.9V VDD at SS Corner. The leakage power while holding 0 is lower by 1.13× in 10T SRAM array than 8T SRAM array at FF corner at 0.9V VDD. The design metrics are evaluated for a wide range of supply voltage. The designs are implemented in Cadence Virtuoso in 45nm Technology node.

System-level variation-aware aging simulator using a unified novel gate-delay model for bias temperature instability, hot carrier injection, and gate oxide breakdown

In this paper, a self-testable SiGe low noise amplifier (LNA) is designed and a Built-in-Self-Test (BIST) methodology is proposed for amplifiers embedded in RF systems. In this BIST methodology, the RF amplifier has the capability to simultaneously test multiple performance specifications on-chip, including Gain and PldB. The self-testable LNA can be placed in a testing mode, in which it self generates a signature of its health using oscillation principles. It eliminates the requirement of any external test stimulus for testing purposes, thus enables the possibility of self-testable RF designs. For the proof of concept, the presented SiGe LNA is designed to operate in the X-band (9.0 GHz) in a commercially-available 6 metal layer, 0.18 µm, 120 GHz SiGe BiCMOS platform. This self-testing design concept can be extended to CMOS amplifiers as well. Furthermore, in this paper, the built-in-self-test methodology is demonstrated using board-level as well as chip-level prototypes.

We develop a phenomenological theory of PBTI/TDDB reliability of HK/MG gate stack based on heterogeneous trap generation (TG) and structural relaxation in interfacial (IL) and HK layers. With independently measured parameters, we affirm that for typical HK/MG dielectrics (~1nm IL/3nm HK), significantly higher TG in HK dictates the features of positive bias temperature instability (PBTI) and induces dual-Weibull time dependent dielectric breakdown (TDDB). We also verify that larger relaxation energy in HK suppresses the contribution of HK to the stress induced leakage current (SILC). This framework helps us resolve broad range of puzzling PBTI, TDDB and SILC experiments regarding time evolution, voltage dependence and temperature activation, and establish an intrinsic correlation between SILC performance and PBTI/TDDB degradations in nMOS HK/MG dielectrics. We use this model to explore the trade-off between IL scaling and dielectric reliability, a discussion that will eventually be useful in optimizing the performance-reliability of CMOS technology with HK/MG stack.

Both negative bias temperature instability (NBTI) and time dependent dielectric breakdown (TDDB) are two major reliability issues for long term performance of high-k gate stacks. In this work, these two degradation mechanisms were extensively analyzed to explore any possible correlation in terms of defects formation. A variety of dielectric stacks were considered to perform NBTI and TDDB. It was observed that NBTI induced defects, generated at the interface and in the interfacial layer were somewhat identical to the defects that dominate the breakdown process.