TDDB-emerald: A methodology for estimating memory reliability degradation resulting from time-dependent dielectric breakdown

The time-dependent dielectric breakdown (TDDB) of Cu damascene interconnects was investigated, noting the time variations in stress-induced leakage current. Copper interconnects normally have symmetric current-voltage curves, which suggests that defects are distributed symmetrically between two Cu lines. Although the impact damage model satisfies this requirement, as does the thermochemical E-model, the Cu diffusion model does not. Without the barrier metal, Cu+ ions rapidly penetrate the dielectric film and form unstable conduction filaments. The leakage current fluctuates greatly due to the rapid Cu movement in the last stage of bias temperature stressing. These current fluctuations also appear in the triangular voltage sweep so that a spurious peak emerges, which is unrelated to the ionic displacement current. The extrinsic TDDB has a small field acceleration parameter (0.5 cm/MV); however, it switches to a large one (4.5 cm/MV) at electrical fields that are higher than 2 MV/cm. Another type of degradation is the thermal reaction between Cu and low-k. High-temperature annealing (>200 °C) generates shallow-energy-level defects in the SiO forbidden-energy gap. The shallow-energy-level defects have less impact on the TDDB lifetime although they cause a large Poole–Frenkel type current.

Ultra low-k films are used in advanced technologies as dielectric interlayers in Cu interconnects. Due to its high porosity, manufacturing reliable low-k films faces many challenges. This paper discusses the reliability of time dependent dielectric breakdown (TDDB). Degradation of the TDDB lifetime can be observed when there is an abnormal I–V breakdown. Our study characterized the interaction of the breakdown leakage to the etch profile. It has shown that the etch profile weak points have impacts on the TDDB lifetime. By characterizing the Cu etching profile and establishing inline correlations to its TDDB lifetime, a new evaluation method was identified to quickly and precisely reflect the TDDB lifetime performance.

In advanced technology node, the complexity of process, materials selection and limitation of tools' capability, becomes very challenging with respect to meet tight reliability targets. In our fabrication of low-k based BEOL integration scheme, we have demonstrated that by proper inline process characterization, feedback and control at critical process modules, a robust Time Dependent Dielectric Breakdown (TDDB) and Electromigration (EM) performance can be achieved. In this paper, we proposed a working model with inline process parameters characterization, reliability performance evaluation, root causes identification and solutions, to establish a relationship between inline process parameters and BEOL TDDB, EM performance. Our data shows that, to pass TDDB E-model (field driven), Mx final critical dimension (FCD) must be within very tight control of less than FCD target + 0.5nm, and greater than FCD target − 2nm. On the other hand, to pass TDDB SQRT E-model, FCD target − 2nm FCD target − 2nm is needed. Through this working model, we are able to justify and identify the critical process modules and to determine the process window to achieve robust BEOL TDDB and EM performance.

This work presents a systematic study of the off-state drain bias time dependent dielectric breakdown (TDDB) mechanism, especially for the short channel transistors in advanced FinFET technologies. The sub-threshold leakage current was found to play a key role in determining the off-state drain bias TDDB degradation. Short channel transistors show higher electric field (E-Field) near the drain side due to increase in sub-threshold leakage current and hence, the breakdown lifetime is seen to scale with decrease in channel length. Moreover, with additional process optimizations, such as source/drain proximity push, the sub-threshold leakage current increases which results in worse off-state TDDB and shorter lifetime during practical circuit stress conditions. Also, impact of body bias on sub-threshold current is also studied in this work.

Hexagonal boron nitride (h-BN) is a promising material for designing future electronic devices because of its superior dielectric properties. In this study, we fabricated bulk h-BN (sp2-bonded BN nano-network structure) on Si substrates using magnetically confined arc discharge plasma under various conditions. The effects of process gas conditions (Ar/N2 and N2) and impurity [tungsten (W)] incorporation were discussed. Regardless of the gas conditions, the presence of W atoms was found to significantly modulate the optical energy gap, which is supported by first-principles calculations. We investigated time-dependent dielectric breakdown (TDDB) mechanisms under constant voltage stress (CVS) and constant current stress (CCS). The time evolutions of the leakage current and the applied gate voltage during the TDDB measurements were analyzed to clarify the carrier-trapping and defect-generation mechanisms toward the final catastrophic dielectric breakdown. The field acceleration factors in the CVS-TDDB lifetime prediction fell within the general trend of SiO2-based films and were found to be a weak function of the gas condition and W concentration (CW), whereas the carrier-trapping and defect-generation dynamics during electrical stress depend on the gas conditions and CW. Based on the obtained results, we propose a prediction model for bulk h-BN degradation dynamics during CVS. We found that carrier trapping into preexisting sites and the probability of defect generation were enhanced by the bombardment of ions with higher energy during the bulk h-BN formation and a larger number of incorporated W atoms. These findings provide fundamental guidelines for the reliability assessment of bulk h-BN films for various applications.

Latch-up (LUP) [1] and time-dependent dielectric breakdown (TDDB) [2] are well-studied reliability issues. For an individual technology node, LUP is often studied at the transistor/gate level, while interconnect TDDB [3] is often studied from breakdown model and metal-dielectric material composition point of view. However, the complexity of their effects on the function of circuit design during chip assembly is expanding beyond a single device/gate, residing deep inside a chip, and increasing with the advance of technology. Modeling their influence on layouts of larger circuits has proven very challenging; attempts to completely simulate a large design block or full chip with reliable outcomes have not been promising so far, due to the enormous amount of data to be processed and the input of uncertain simulation factors. It is critical for both foundries and independent device manufacturers (IDMs) to provide useful and feasible design guidelines for designers to follow to achieve successful tape-out. In this paper, we present a static voltage propagation approach and design automation methodology to assist and enhance rule-based LUP and TDDB design reliability verification in the chip assembly stage.

This paper reviews the most encouraging process options for improving backend-of-line reliability performance in advanced technology nodes. Metal capping yields the best electromigration performance; however, this process is most challenging with respect to integration and may also suffer from significantly decreasing grain sizes in trench bottoms for future technologies. Furthermore, time-dependent dielectric breakdown has to be carefully evaluated. Alloying or silicidation techniques are less challenging to implement but can result in unacceptably high resistance increases. We analyze the respective results for each option and compare the performance on 45, 32, and 28nm technology nodes. In addition to electromigration and time-dependent dielectric breakdown, the impact of the various process options on stress migration performance is discussed.

Time Dependent Dielectric Breakdown (TDDB) in p-FETs with HfSiON/SiO 2 gate stacks under negative bias stress has been studied. It is shown that the shape parameter of Weibull distribution of T bd , β, is very small value independent of gate electrode materials. This small β seems to arise from the interface layer (I.L.) breakdown. Further experimental result reveals the existence of additional interface layer degradation mechanisms due to hydrogen in HfSiON. The reduction of hydrogen amount in high-k dielectrics leads to the longer-term reliability in metal-gate /high-k gate stacks.

As CMOS is being scaled down to 28nm node and beyond, it is necessary to reduce k value in order to improve RC delay. ULK (ultra-low k) (k<2.55) has been implemented into production from 45/40nm node. Compared with low-K film, ultra-low K film is more porous, softer and hydrophilic intrinsically. It is easy to be damaged by plasma, stress, thermal or aqueous environments. It brings more challenges for reliability improvement. This paper focuses mainly on ULK process optimization through simple key parameter optimization to improve voltage break down (VBD) and time-dependent dielectric breakdown (TDDB) and electro migration (EM) performance without scarifying RC delay.

In this paper, a new approach is presented for esti- mating the hot-carrier induced degradation in MOS transistors in VLSI circuits. With the decrease in feature size, many long-term reliability issues, such as HCE (Hot-Carrier Effect), TDDB (Time- Dependent Dielectric Breakdown), etc., can no longer be ignored during the design process. In this work we mainly concentrate on HCE; however, the approach can be applied to investigate other reliability issues. HCE is a long-term reliability issue that is caused by the cumulative effects of all possible inputs on the devices in the circuit over time. Existing techniques use deterministic circuit or timing simulation to estimate HCE and try to predict the age of the design by incorporating device degradation over time. As a result, all HCE simulators are too slow (especially if linked to SPICE-circuit simulators) for large circuits; and even when fast simulation techniques are used, user- specified deterministic input waveform are needed and, hence, the results can only represent a small sample of operating conditions. In this paper, we propose a probabilistic timing approach. The advantage of probabilistic simulation is that we can explore the cumulative effects of all possible input waveform combinations in one run. The approach has been implemented in a general- purpose simulator and tested on a number of typical examples and benchmarks.

We investigated the mechanisms of bias temperature instability (BTI) and time dependent dielectric breakdown (TDDB) of phase-controlled-Ni-FUSI/HfSiON that has an electrode of NiSi and Ni <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> Si. A NFET-PBTI did not degrade and the electron trap density remained low even with a higher Ni-content electrode. On the other hand, NFET-TDDB degraded with a Ni <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> Si electrode. The decrease was related to a degradation in insulator quality near the gate dielectrics/Si interface that was enhanced by a compressive mechanical strain due to the gate electrode. NBTI of PFET did not degrade with a Ni <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> Si electrode, but the main NBTI component changed from interface trap generation to hole trapping of the gate dielectrics. PFET-TDDB was improved by using NiSi and Ni <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> Si instead of p+ poly-Si. We attribute this improvement to a reduction in electron energy at the anode. Thus, the NFET: NiSi and PFET: Ni <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> Si is judged to be a superior combination for both of reliability and initial characteristics

Effects of total ionizing dose (TID) on the transient radiation upset sensitivity of commercial static random access memories (SRAMs) were investigated. Commercial SRAMs of three technology nodes were irradiated with Co-60 gamma rays for total dose effects and with pulsed x rays generated using a “Chen-Guang” accelerator for doserate effects. It is shown that TID irradiation and the memory pattern written to the memory array during TID irradiation can substantially affect the transient radiation upset sensitivity of all the SRAMs. First, the memory pattern written to the memory array during TID irradiation is more sensitive to pulsed x rays for all SRAMs. Second, the variation in transient radiation upset sensitivity with total dose has different tendencies for different SRAMs, but the static power current increased with the increase in total dose for all SRAMs. The increase in static power current with total dose and the increasing sensitivity of the memory pattern during TID irradiation are caused by the increasing TID induced leakage current, which results in an asymmetric noise margin of individual memory cells.

A low power CMOS Static Random Access Memory (SRAM) based Field Programmable Gate Arrays (FPGA) architecture is being presented in this paper. The architecture presented here is based on CMOS logic and CMOS SRAMs that are used for on-chip dynamic reconfiguration. This architecture employs the fast and low-power SRAM blocks that are based on 10T SRAM cells. These blocks are employed in fast access of the configuration bits by using the shadow SRAM technique. The dynamic reconfiguration delay is being hidden behind the computation delay through the use of shadow SRAM cells. The combined effect of both the SRAM memory cells and the shadow SRAM scheme enables to support in reducing the delay and also to achieve reduced power consumption. Experimental results show reduced delay of about 8.035ns and power consumption of about 0.015W for the 10T SRAM memory cell with an overhead in area, relative to 4T and 6T SRAM cells. Also, the experimental results include the values of delay of about 8.979ns and power consumption of about 0.052W, achieved for the LB of FPGA architecture which employs CMOS SRAMs using the 10T SRAM memory cells in it.

We present an electrical diagnosis methodology for a variety of wearout mechanisms, including back-end time-dependent dielectric breakdown (TDDB), electromigration, stress-induced voiding, gate oxide TDDB, and bias temperature instability, in an SRAM array. First, the built-in self-test (BIST) system detects wearout and identifies the locations of the faulty cells. Next, the physical location of the failure sites within SRAM cells is determined. There are some fault sites for different mechanisms which result in exactly the same electrical failure signature. For these faulty sites, the cause of failure probabilities for each wearout mechanism is estimated by matching the observed failure rate from BIST and the failure rate distribution computed by simulation and as a function of circuit use scenarios. The estimation of wearout distributions is helpful in determining the wearout limiting mechanisms in the field.

WITHDRAWN: Comparative analysis on low power SRAMs