Bulk-Si photonics technology for DRAM interface [Invited

We discuss the transient-enhanced diffusion of Sb, As, P, In, Ga, and B in ion-implanted Si, where the near-surface region has been amorphized by the dopant or by a self-implantation process. With Sb, a large transient diffusion enhancement is observed proportional to dopant concentration. For Sb, As, P, and In, the enhancement follows the relative interstitialcy diffusion coefficient. We believe this behavior is caused by stable implantation-induced point defects present in the amorphous surface layer, which decay during thermal processing to release high concentrations of self interstitials. This process occurs in competition with the solid phase epitaxial (SPE) growth process, and for high dopant concentrations can occur in the amorphous phase ahead of the crystallization front. We believe this may be the origin of the dopant redistribution which can occur during SPE growth, which sets the upper limit to the dopant concentration which can be incorporated in the lattice by SPE growth. These effects are reduced for Ga and are absent for B, although transient enhanced diffusion of these species can still occur from defects emitted from the damaged crystal underlying the original amorphous/crystalline interface.

Multitude applications of photonic devices and technologies for the generation and manipulation of arbitrary and random microwave waveforms, at unprecedented processing speeds, have been proposed in the literature over the past three decades. This class of photonic applications for microwave engineering is known as microwave photonics (MWP). The vast capabilities of MWP have allowed the realization of key functionalities which are either highly complex or simply not possible in the microwave domain alone. Recently, this growing field has adopted the integrated photonics technologies to develop microwave photonic systems with enhanced robustness as well as with a significant reduction of size, cost, weight, and power consumption. In particular, silicon photonics technology is of great interest for this aim as it offers outstanding possibilities for integration of highly-complex active and passive photonic devices, permitting monolithic integration of MWP with high-speed silicon electronics. In this article, we present a review of recent work on MWP functions developed on the silicon platform. We particularly focus on newly reported designs for signal modulation, arbitrary waveform generation, filtering, true-time delay, phase shifting, beam steering, and frequency measurement.

Point defect induced SPE growth of Ni implanted silicon

ABSTRACTThe initial stage of solid phase epitaxial (SPE) growth of GaAs films on the vicinal Si (001) substrate was investigated by high resolution transmission electron microscopy (H-RTEM). Cross-sectional [110] and [110] HRTEM images show that the SPE growth of crystalline GaAs islands from the amorphous phase proceeds via the formation of three-dimensional islands at the initial stage and islands' size and spacing are not critically dependent on the substrate tilt direction. The average vertical and lateral dimensions of islands were found to be 9 nm and 14 nm respectively, and the average island spacing was 10 nm. Moreover, many internal stacking faults (and/or microtwins) and a few dislocations have been already formed at this initial stage of growth. In addition, the critical thickness for misfit dislocation formation is found to depend upon the islands' lateral dimensions as well as the heights.

A cross-sectional transmisson electron microscope (XTEM) study of intrinsic solid-phase epitaxial (SPE) growth in self-ion-implanted (001) Si has been carried out. The activation energy of the self-ion-implanted silicon was measured to be 2.6±0.2 eV. The value is remarkably close to those obtained in the two most recent studies by other techniques. The pre-exponential factor is lower than that reported by Lietoila et al. [J. Appl. Phys. 53, 4399 (1982)] annealed under similar conditions. The variation in proximity to the surface and difference in the distribution of the microstructural defects in the two studies are suggested to be possible causes for the discrepancy. The advantages of utilizing the XTEM technique to study epitaxial growth of self-ion-implanted amorphous thin films are demonstrated. The accuracy in the XTEM measurement of the SPE regrowth rate in Si+-implanted (001) Si is discussed.

Quantum biosensors offer a promising route to overcome the sensitivity and specificity limitations of conventional biosensing technologies. Their ability to detect biochemical signals at extremely low concentrations makes them strong candidates for next-generation sensing systems. This paper reviews the current state of quantum biosensors and discusses their future implementation in chip-scale platforms that combine microelectronic and photonic technologies. It covers key quantum biosensing approaches including quantum dots (QDs), and nitrogen-vacancy (NV) centers. This paper also considers their potential compatibility with electronic integrated circuits (EICs), photonic integrated circuits (PICs) and integrated quantum photonic (IQP) systems for future biosensing applications. To our knowledge, this is the first review to systematically connect quantum biosensing technologies with the development of microelectronic and photonic chip-based devices. The goal is to clarify the technological trajectory toward compact, scalable, and high-performance quantum biosensing systems.

Present status of solid phase epitaxy of vacuum-deposited silicon

Silicon photonic wire waveguides, featuring very strong optical confinement and compatibility with silicon electronics, provide a compact photonic platform on which passive, dynamic, and active photonic devices can be integrated. We have already developed a low-loss waveguide platform and integrated various photonic devices. For passive devices, we have developed polarization-independent wavelength filters using a monolithically integrated polarization diversity circuit, in which waveguide-based polarization manipulation devices are implemented. The polarization-dependent loss of a ring resonator wavelength filter with polarization diversity is less than 1 dB. For dynamic devices, we have developed compact carrier-injection-type variable optical attenuators (VOAs). The length of the device is less than one millimeter, and the response time is nanosecond order. The device has already been made polarization independent. We have recently monolithically integrated these fast VOAs with low-dark-current germanium photodiodes and achieved synchronized operation of these devices. For nonlinear devices, a free-carrier extraction structure using a PIN junction implemented in the waveguide can increase the efficiency of nonlinear functions. For example, in a wavelength conversion based on the Four-wave-mixing effect, the conversion efficiency can be increased by 6 dB.

We are delighted to introduce a Special Issue on Optical Interconnects for the IET Optoelectronics magazine. This issue presents the current status as well as some of the outstanding progress that has been witnessed in the rapidly evolving area of optical interconnects. Today, data centres (DC) and high-performance computers are struggling with limited interconnect capacity and increased power consumption while trying to meet overwhelming bandwidth demands. As photonics technologies have been rapidly maturing, optical interconnects have come into the spotlight as the means to cope with the emerging bandwidth, energy, and capacity needs. As such, a wealth of photonic interconnect solutions across the DC hierarchy has unfolded, covering from electro-optic boards to transceiver development, on-chip and on-board switches and interconnects as well as novel noninvasive monitoring methods for light controlling for compensating thermal crosstalk, fabrication tolerances and unstable environmental conditions. At the same time, the increased penetration of optical interconnects in short-reach communications, such as board and chip levels, has triggered new challenges in photonics technologies calling for new innovations with respect to integration techniques and packaging methods. This Special Issue of IET includes integrated circuits, assembly techniques, systems-level architectures, and controlling methods related to short reach ‘chip-to-chip’, ‘in-the-box’, and ‘box-to-box’ communications. Specific areas covered by this special issue include: Silicon photonic transceiver technologies and flat DC topologies; High-speed electro-optic hosting boards and fast, energy-efficient electronics; DC switches and co-packaged optic (CPO) technologies; and Noninvasive controlling techniques for complex photonic integrated circuits. The four papers in this special section promote high-performance optical interconnect architectures and key technologies to tackle the rising bandwidth demands of DCs. They cover (a) co-packaged DC optics, (b) silicon technology transceiver modules and high-speed hosting boards for multisocket server board (MSB) interconnects and (c) automated controlling architecture for complex photonic systems; Items (b) and (c) draw from impressive achievements accomplished through the recently completed European H2020 Project ICT-STREAMS. This report written by C. Mickenberg tries to shed light on motivating factors behind co-packaged optics (CPO), the trade-offs involved and their potential impact on data centre network architectures. The article reviews the evolution of DC switch application-specific integrated circuit (ASICs) and DC optics, provides a future road map and finally discusses the potential impact of CPO on the network architecture. This topic is covered by two articles. The first, written by M. Morallis-Pegios, proposes using silicon photonics to advance interconnect throughput, socket connectivity and energy efficiency in MSB layouts by enabling a flat-topology wavelength division multiplexing (WDM) point-to-point optical MSB interconnect scheme. WDM silicon photonic transceivers coassembled with their electronic circuits achieving a 50-Gb/s line rate and 400-Gb/s aggregate data transmission are demonstrated. The article also proposes silicon photonic Arrayed Waveguide Grating Router (AWGRs) that can offer collision-less time-of-flight connectivity for up to 16 nodes. The second article covering that area is written by T. Lamprecht and reports on the development of electro-optic hosting boards for on-board transceiver subassemblies which is required to eventually form the Tb/s multi-socket onboard communication. The article also discusses the electrical interface as well as photonic board requirements, including the manufacturing technique and the assembly concept that was followed to deliver terabyte per second multichip optical communication. This article, written by F. Zanetto, introduces a novel dithering technique for real-time control of multiple cascaded photonic integrated devices, proposing a calibration-free strategy to support the development and real-life diffusion of increasingly complex photonic systems. The article elaborates on the implementation of a calibration-free automated control loop exploiting integral controllers to close a real-time feedback and stabilise the optimum working point of the employed photonic devices. The effectiveness of the proposed architectural approach is experimentally validated with the error-free routing and transmission of a 30-Gbit/s optical signal traversing a cascade of micro-ring resonator filters. All of the articles selected for this Special Issue present a wide variety of key topics and significant results addressing optical interconnects in high-performance data communication systems, including new progress on architectures, systems and packaging techniques as well as novel optimised controlling methods. As guest editors, we would like to thank all of the authors for their high-quality submissions that significantly contribute to the optical interconnect field. We would also like to thank the reviewers for their valuable and constructive technical comments that greatly enhance the Special Issue, because their feedback and comments ensure the high quality of the IET Optoelectronics Journal. We hope that this IET Special Issue will provide a useful reference of the state-of-the-art in optical interconnects to readers, and we anticipate such technological perspectives will stimulate new advancements and technological outcomes that will in turn enrich the growing field of optical interconnects. This work was supported by the E.C. through the H2020-ICT-STREAMS research project (688172).

The data rate of the dynamic random access memory (DRAM) interface has been greatly increased to reduce the performance gap between the DRAM and the central processing unit (CPU). The data rate of double-data rate (DDR) synchronous DRAM (SDRAM) is now exceeding 266 Mb/s/pin while the packet-based RAMBUS DRAM is offering up to 1066 Mb/s/pin data rate. The difference in the data rate is mainly due to their different channel structures. These DRAM interface channels are basically multi-drop bus where a driver should drive multiple loads. The maximum data rate is determined by how the multiple loads are configured. The data rate of the DRAM interface channel has been greatly increased and is expected to exceed 2 Gb/s/pin in the near future. To achieve this goal, the physical interface such as the bus structure should be optimized to minimize the timing uncertainty. The I/O timing circuitry plays an important role in determining the maximum data rate. Thus, the, circuit design should also be focused on minimizing timing uncertainty.

Solid-phase epitaxy (SPE), a solid-state phase transition of materials from an amorphous to a crystalline phase, is a convenient crystal growing technique. In particular, SPE can be used to grow α-Al2O3 epitaxially with a novel structure that provides an effective substrate for improved performance of light-emitting diodes (LEDs). However, the inevitable two-step phase transformation through the γ-Al2O3 phase hinders the expected improved crystallinity of α-Al2O3, and thereby further enhancement of LED performance. Herein, we provide a fundamental understanding of the SPE growth mechanism from amorphous to metastable γ-Al2O3 using transmission electron microscopy (TEM) and density functional theory (DFT) calculations. The nanobeam precession electron diffraction technique enabled clear visualization of the double-positioning domain distribution in the SPE γ-Al2O3 film and emphasized the need for careful selection of the viewing directions for any investigation of double-positioning domains. Void and stacking fault defects further investigated by high-resolution scanning TEM (STEM) analyses revealed how double-positioning domains and other SPE growth behaviors directly influence the crystallinity of SPE films. Additionally, DFT calculations revealed the origins of SPE growth behavior. The double-positioning γ-Al2O3 domains randomly nucleate from the α-Al2O3 substrate regardless of the α-Al2O3 termination layer, but the large energy requirement for reversal of the γ-Al2O3 stacking sequence prevents it from switching the domain type during the crystal growth. We expect that this study will be useful to improve the crystallinity of SPE γ- and α-Al2O3 films.

Single crystalline Ge compounds (SiGe, GeSn) have interesting electrical and optical properties [1], rendering them well-suited to a wide variety of applications. GeSn has been predicted to exhibit carrier mobilities exceeding that of Ge [2], which makes this material suitable as a channel material for high-speed complementary metal-oxide semiconductor (CMOS) technology [3]. In addition to increased carrier mobility, the GeSn material system is interesting for its optical properties. GeSn exhibits a direct band gap between 0.61 and 0.35 eV for Sn concentrations between 6 and 15 % [4]. This makes it much better fit for optoelectronic applications than Si and Ge, especially at long wavelengths.Epitaxial growth of GeSn on Si substrates poses several challenges including a limited solubility of Sn in Ge (0.5%), compositional fluctuations, Sn segregation and a large lattice mismatch (>4%). It is critical to suppress these effects while simultaneously optimizing the GeSn layer characteristics for the basis of high performance devices.Recently, we demonstrated the growth of single crystalline GeSn layers with excellent structural quality grown on Si(111) substrates, by solid phase epitaxy (SPE) of amorphous GeSn alloys[5]. This technique has an advantage in the realization of thin GeSn layers directly on Si. We do not use surfactants, a capping layer, nor a buffer layer. Amorphous GeSn layers are obtained by the co-evaporation of Ge and Sn atoms, with beam equivalent pressures of 1.33 x 10-7 Torr for Ge and 9 x 10-9 Torr for Sn, while exposing the substrate to a N2 flux with a beam equivalent pressure of about 1 x 10-5 Torr, at a deposition temperature around RT. Subsequent annealing transforms the amorphous GeSn into a single crystalline layer via solid phase epitaxy. Excellent structural quality is demonstrated for layers with up to 6.1 % of Sn. The GeSn layers show tensile strain (up to +0.34%), which lowers the difference between the direct and indirect band transition and makes this method promising for obtaining direct band gap group IV layers. GeSn with 4.5% Sn shows increased optical absorption compared to Ge and an optical band gap of 0.52 eV. Furthermore, the surface and interface are smooth (RMS roughness < 1 nm), despite the relaxation of the layers.Additional structural investigation by XRD and TEM showed the presence of twin defects in the GeSn layers after crystallization. These defects can have a significant impact on the carrier mobility and it is therefore important to suppress the formation of twin defects during crystallization. The formation of twin defects is likely related to the presence of contaminants, in particular oxygen, at the interface between the crystalline substrate and the amorphous layer leading to the roughening of the amorphous-crystalline interface during SPE growth. We have developed a 2-step deposition process which successfully suppresses the formation of such twin defects.Additionally, we demonstrate excellent electrical properties of the GeSn layers by the fabrication of depletion-mode GeSn pMOSFETs on Si(111) using SPE of amorphous GeSn layers, TaN/Al2O3 metal-gate/high-k gate stacks, and Ni-based metal S/D contacts. The GeSn MOSFET devices show +100% improvement in hole mobility with respect to bulk Si and good transfer characteristics with On/Off ratio of ~100 for ultrathin (<10 nm) GeSn layers on Si [6].Finally, we also demonstrate successful crystallization of amorphous SiGe layers, deposited by plasma enhanced chemical vapor deposition (PECVD) on Si substrates and annealing in N2 atmosphere. The SiGe layers show excellent structural quality for compositions ranging from Ge- to Si-rich.[1] J. Kouvetakis et al., Ann. Rev. Mater. Res. 36, 497 (2006)[2] J. D. Sau and M. L. Cohen, Phys. Rev. B 75, 045208 (2007)[3] C. Merckling et al., Appl. Phys. Lett. 11, 192110 (2011)[4] G. He and H. A. Atwater, Phys. Rev. Lett. 79, 1937 (1997)[5] R. R. Lieten et al., Appl. Phys. Lett. 102, 052106 (2013)[6] R. R. Lieten et al., Appl. Phys. Express 6, 101301 (2013)

Surface morphology and structure of Ge layer on Si(111) after solid phase epitaxy

ABSTRACTWe demonstrate the homoepitaxial growth of SrTiO3 prepared by the method of metallo-organic decomposition (MOD). Thin films of SrTiO3 are prepared by spin-coating and thermal decomposition of a solution of metallo-organic compounds, on single crystal, &lt;100&gt; oriented, SrTiO3 substrates and subsequently heat treated at temperatures ranging from 650°C to 1100°C for 30 minutes. Heat treatment at 1100°C results in the formation of single-crystal SrTiO3, perfectly aligned with respect to the underlying substrate.Ion-channeling analysis shows that the transformation to singlecrystal material proceeds epitaxially from the coating-substrate interface towards the surface of the sample. Transmission electron microscopy (TEM) studies of partially regrown samples reveal two distinct phases: an epitaxially aligned single-crystal phase, adjacent to the substrate, and a polycrystalline phase on top. On the basis of these observations, it is proposed that the crystallization of the MOD films involves the competition between two processes: layer-by-layer solid phase epitaxy and random nucleation and growth of crystallites. Layerby- layer epitaxy is the predominant crystallization mechanism unless it is inhibited by extrinsic factors like the contamination of the interface between the MOD film and the single-crystal substrate.

Specific energy consumption of dynamic random access memory module supply chain in Taiwan