Bus and instruction fault diagnosis

Faulty switches, broken interswitch connections and certain bridging faults in a Benes switching network can be identified using a sequence of faulty paths across the network. The method described may use on-line faulty-path data and is suitable for use in the diagnosis of intermittent faults. It is shown that a single faulty switch can be identified in less than four random faulty paths on average, after presentation of the initial faulty path. The method applies to other types of switching network and provides a similar performance.

This paper proposes a method based on chaotic spread spectrum sequence for synchronous online diagnosis of intermittent faults for complex and cable. networks, such as the aircraft power system. The novelties of the proposed method include: 1) since chaotic spread spectrum signals are sensitive to initial values, the number of chaotic sequences are not limited and the proposed method is not limited by the number of cables under monitoring; 2) with the self-correlation characteristic and cross-correlation characteristic of chaotic sequence, the proposed method can be extended to online diagnosis of multiple cable intermittent faults; and 3) the signal source impedance amplification method is proposed for intermittent arc faults of multiple cables, which improves the reflection coefficient and increases the accuracy of online detection and location of intermittent arc faults. A series of simulations and experiments on multiple cables with different intermittent fault modes are conducted to verify the effectiveness of the proposed approaches.

For avoiding false-alarm and diagnosing intermittent fault, based on the relationship analysis between intermittent fault and false-alarm, the intermittent fault diagnosis model of power system based on HMM (Hidden Markov Model)-SVM (Support Vector Machine) characteristics was constructed in this paper. By means of this model, the intermittent fault diagnosis procedure of power system based on HMM-SVM characteristics was built. Finally, the intermittent fault diagnosis simulation system of power system based on HMM-SVM characteristics was demonstrated and validated by QUEST software. The result showed that the proposed method was available, and can provided guidance for avoiding false-alarm and diagnosing intermittent fault, and support for stable performance in power system.

The huge processing power needed by multimedia applications has led to multimedia extensions in the instruction set of microprocessors which exploit subword parallelism. Examples of these extended instruction sets are the Visual Instruction Set of the UltraSPARC processor, the AltiVec instruction set of the PowerPC processor, the MMX and ISS extensions of the Pentium processors, and the MAX-2 instruction set of the HP PA-RISC processor. Currently, these extensions can only be used by programs written in assembly language, through system libraries or by calling specialized macros in a high-level language. Therefore, these instructions are not used by most applications. We propose two code generation techniques to produce native code using these multimedia extensions for programs written in a high-level language: classical vectorization and vectorization by unrolling. Vectorization by unrolling is simpler than classical vectorization since data dependence analysis is reduced to acyclic control flow graph analysis. Furthermore, we address the problem of unaligned memory accesses. This can be handled by both static analysis and dynamic runtime checking. Preliminary experimental results for a code generator for the UltraSPARC VIS instruction set show that speedups of up to a factor of 4.8 are possible, and that vectorization by unrolling is much simpler but as effective as classical vectorization.

Diagnosis of incipient parametric faults has been widely addressed and various model-based as well as data-based methods have been reported in the literature. In contrast to incipient faults, it is unknown if, when and for how long intermittent faults will reappear which makes their diagnosis and prognosis difficult. This paper addresses intermittent faults with a magnitude that increases over time. Such a sequence of intermittent faults may reach a failure alarm threshold and may eventually lead to a component or even a system failure. The proposed approach uses a diagnostic Bond Graph (DBG) model for an online detection, isolation and estimation of intermittent faults. Pulses of increasing height and varying width not equally spaced on the time evolution of residuals of Analytical Redundancy Relations (ARRs) obtained from an offline developed DBG indicate a degradation trend of a parameter or a variable. Certain values of this trend are concurrently extrapolated in a repeated failure prognosis resulting in a sequence of Remaining Useful Life (RUL) estimates. The proposed BG-based approach to a failure prognosis in the presence of intermittent faults can be combined with a previously presented BG-approach to incipient fault prognosis and is applicable to mode switching models. For illustration, it is applied in a case study to a small electronic circuit in an offline simulation. The case study also considers intermittent faults of constant magnitude.

The ISP (for Instruction Set Processor) notation was developed for a text [Bell& Newell, 1971] to precisely describe the programming level of a computer in terms of its Memory, Instruction Format, Data Types, Data Operations, Interpreting a Specific Instruction Set.

Deep model integrated with data correlation analysis for multiple intermittent faults diagnosis

This paper presents a new methodology for permanent and intermittent fault diagnosis, named faults latent nestling method (FLNM), using coloured Petri nets (CPNs). CPNs and FLNM method allow for an enhanced capability for synthesis and modelling of complex systems in contrast to the classical phenomena of combinational state explosion when using finite state machine based methods.

Diagnosis of intermittent scan chain failures still remains a hard problem. In this article, we demonstrate that the use of artificial neural networks (ANNs) can lead to significantly higher accuracy. The key of this method is a multistage process incorporating ANNs with gradually refined focuses. During this process, the final fault suspect is elected through multiple rounds of ANN inference, instead of just one round. At each stage, identification of a proper Affine Group, used as the “candidate set of scan cells for the next round of ANN inference,” will influence the final diagnostic accuracy. Thus, we propose a validation-based learning procedure for Affine Group derivation to further boost the final diagnostic accuracy. The experimental results on benchmark circuits have shown that this method is, on the average, 17.46% more accurate than a state-of-the-art commercial tool for intermittent stuck-at-0 faults.

The Internet and associated network technologies are an increasingly integral part of modem day working practices. With this increase in use comes an increase in dependence. For some time, commentators have noted that given the level of reliance on data networks, there is a paucity of monitoring tools and techniques to support them. As this area is addressed, more data regarding network performance becomes available. However, a need to automatically analyse and interpret this performance data now becomes imperative. The paper takes one-way latency as an example performance metric. The term 'data exception' is employed to describe delay data that is unusual or unexpected. Data exceptions can be used by network operators to assess the effect of network modifications, failures and usage, and can also help in the diagnosis of intermittent network faults. Automating the detection of data exceptions is a non-trivial process that is not well suited to a rule-based solution. The paper shows that data exceptions can be identified by the use of a two-stage approach. The Kolmogorov-Smirnov test can initially be applied to detect general changes in the delay distribution, a neural network can then be used to categorise the change. The approach is evaluated using a network simulation.

Controller Area Networks (CANs) play an important role in many safety-critical industrial systems, which places high demands on their reliability performance. However, the intermittent connection (IC) of network cables, a random and transient connectivity problem, is a common but hard troubleshooting fault that can cause network performance degradation, system-level failures, and even safety issues. Therefore, to ensure the reliability of CANs, a fault symptom association model-based IC fault diagnosis method is proposed. Firstly, the symptoms are defined by examining the error records, and the domains of the symptoms are derived to represent the causal relationship between the fault locations and the symptoms. Secondly, the fault probability for each location is calculated by minimizing the difference between the symptom probabilities calculated from the count information and those fitted by the total probability formula. Then, the fault symptom association model is designed to synthesize the causal and the probabilistic diagnostic information. Finally, a model-based maximal contribution diagnosis algorithm is developed to locate the IC faults. Experimental results of three case studies show that the proposed method can accurately and efficiently identify various IC fault location scenarios in networks.

Introduction: Despite all the control efforts made to reduce the prevalence of Tuberculosis (TB) in Malaysia, TB is still a leading cause of mortality among the communicable diseases with a rate of 5.37 per 100,000 population. It has also caused a significant economic burden to the government in the order of USD15 million per year as reported by World Health Organization in 2015. However, the long-term epidemiological and economic burden of TB management has not been established. Objectives: The objectives of this study are to evaluate the health and economic burden of TB management in Malaysia, and the cost-effectiveness of TB control programme by developing a dynamic transmission model. Methodology: A retrospective observational study was conducted in Selangor, including all TB patients first diagnosed in the year 2011. With the collected data, binary logistic regression analysis was carried out to determine the risk factors for incomplete treatment in TB patients. Costing study was also conducted to estimate the cost of TB management. The total cost of TB treatment was calculated by multiplying the frequency of health services utilisation with the unit cost obtained from the Medical Fee Act, 2014. Additionally, a dynamic transmission model was constructed to simulate the natural progression of TB in Malaysia over a 10-year horizon. This model was then used to project the annual rate of TB incidence. This study was conducted from government perspective. Furthermore, we conducted the cost-effectiveness of Xpert MTB/RIF test in Malaysia based on the model built. The results were expressed in cost per disability-adjusted life years (DALYs). A discount rate of 3% was considered for both costs and outcomes. One-way sensitivity analysis and probabilistic sensitivity analysis were performed to ensure consistency and robustness of the model outcomes. Results: A total of 555 cases of TB were identified for this study. On multivariate analysis, risk factors that were significantly associated with incomplete treatment included nationality, occupation and TBIS registry. There were also several factors found, associated with incomplete treatment on univariate analysis which included age, gender, main treatment centre, comorbidities, facility utilisation, HIV/AIDS and distance to main facility. An incomplete treatment would cause the government an average of RM901.63 per patient compared to a completed treatment where RM2,242.02 was needed for a non-hospitalised uncomplicated TB case. A further analysis showed that the cost of treating a case with comorbidities and hospital stays was 4.5 times of the cost of treating an uncomplicated TB case. This cost would further escalate if MDR-TB treatments were required, whereby the cost would be 28.5 times more than treating an uncomplicated TB case. Additionally, our projection suggests that TB notification rate (NR) will increase by 57.64% after 10 years. When this burden was translated into monetary terms, a 19.96% (RM31,876,721) increase in TB budget would be required in 2021 if the control strategies remain unchanged as in 2011. In the base case analysis, the incremental cost-effectiveness ratio was RM47,266.80 for the Xpert scenario versus the current practice, which is slightly more than 1 time gross domestic product (RM41,153.62 per capita in 2014). However, with the current evidence, the probabilistic sensitivity analysis showed that at the willingness to pay (WTP) threshold value of RM30,000 per DALY averted, Xpert scenario was cost effective in more than 95% of all simulations. Thus, it is cost effective to be implemented in Malaysia, provided the WTP threshold is set at 1 time gross domestic product per DALY averted. Conclusions: This study has successfully established the cost of TB management in Malaysia. Hospitalisation appeared to be the major cost drive for TB patients receiving TB treatment, thus strategies that could reduce the length of hospital stay without compromising the quality of care in TB treatments should be considered as future research. The dynamic transmission model has projected that the TB burden would continuously escalate. Thus, the future control strategies and new public health interventions could focus on early detection and treatment of TB such as TB education and adopting new diagnostic tools for rapid detection of TB. These could be the keys to bring Malaysia a step closer to TB elimination.

The simulation of parallel computers is discussed. In particular, a technique, called cross-profiling, that can be used to improve the efficiency of these simulations substantially is presented and evaluated. Cross-profiling, along with another simulation technique called execution-driven simulation, can be used to simulate one processor's instruction set (the target processor) with another processor that has a different instruction set (the host processor). Moreover, this technique is significantly faster than the usual method where several host instructions are executed to emulate the effect of executing a single instruction of the target processor. The cross-profiling technique is introduced, and it is shown how it can be combined with execution-driven simulation. The results of several experiments that demonstrate that the error introduced by cross-profiling is typically less than 1% are presented. >

It's like building a bridge. Once the main lines of the structure are right, then the details miraculously fit. The problem is the overall design. Freeman Dyson in Freeman Dyson: Mathematician, Physicist, and Writer, Interview with Donald J. Albers, The College Mathematics Journal, 25, No. 1, January 1994 . Now that we have been introduced to the fundamentals of Verilog, we make a slight change in course to return to the top level of the design flow shown previously in Figure 1.2. In particular, we now discuss the process by which we define the instruction set of a new processor. The instruction set architecture (ISA) of a processor defines all of the instructions available in the processor plus the storage elements that are accessible to the assembly language programmer. The contents of these storage elements, plus a few more that may not be directly accessible to the programmer, comprise the processor's state . In this chapter, we show how the ISA of a complete processor, which we call the Very Small Processor Architecture , or VeSPA for short, is defined, refined, and ultimately specified. This processor is quite simple, with only slightly more than a dozen instructions. However, it is a complete processor capable of executing programs written in a high-level language compiled with an appropriate compiler. We use this processor throughout the remainder of this text as a vehicle for demonstrating the entire processor design process when using the Verilog hardware description language. Instruction set design The design of an instruction set for a new processor is more of an art than a science.

The controller-area network (CAN) bus has a wide range of applications. It plays a key role in information transfer. In fact, a failure of the CAN bus causes information transfer to fail. Therefore, fault diagnosis of the CAN bus is necessary. In addition, CAN bus failures generally result from sample imbalance problems. Therefore, this study proposes a CAN bus fault diagnosis (CANFD) method that integrates a Laplace network (LaplaceCNN) and uses a class-imbalance dataset. The method first utilises the adaptive synthetic (ADASYN) oversampling algorithm to process the class-imbalance CANFD dataset. LaplaceCNN is trained on the processed balanced dataset to diagnose CAN bus faults. To collect the frequency-domain characteristics and feed them into the deep network, LaplaceCNN uses Laplace wavelet convolution as the initial layer of the network. Multiscale wide convolutional and dense residual blocks are proposed to enhance the feature extraction capability of LaplaceCNN and stabilise the model performance. Introducing focal loss further improves the performance of LaplaceCNN on a class-imbalanced dataset. Experiments demonstrate that the proposed method performs better in terms of fault diagnosis.