Compilation Techniques for Multimedia Processors

It's like building a bridge. Once the main lines of the structure are right, then the details miraculously fit. The problem is the overall design. Freeman Dyson in Freeman Dyson: Mathematician, Physicist, and Writer, Interview with Donald J. Albers, The College Mathematics Journal, 25, No. 1, January 1994 . Now that we have been introduced to the fundamentals of Verilog, we make a slight change in course to return to the top level of the design flow shown previously in Figure 1.2. In particular, we now discuss the process by which we define the instruction set of a new processor. The instruction set architecture (ISA) of a processor defines all of the instructions available in the processor plus the storage elements that are accessible to the assembly language programmer. The contents of these storage elements, plus a few more that may not be directly accessible to the programmer, comprise the processor's state . In this chapter, we show how the ISA of a complete processor, which we call the Very Small Processor Architecture , or VeSPA for short, is defined, refined, and ultimately specified. This processor is quite simple, with only slightly more than a dozen instructions. However, it is a complete processor capable of executing programs written in a high-level language compiled with an appropriate compiler. We use this processor throughout the remainder of this text as a vehicle for demonstrating the entire processor design process when using the Verilog hardware description language. Instruction set design The design of an instruction set for a new processor is more of an art than a science.

This article discusses a MATLAB-to-C vectorizing compiler that exploits custom instructions, for example, for Single Instruction Multiple Data (SIMD) processing and instructions for complex arithmetic present in Application-Specific Instruction Set Processors (ASIPs). Custom instructions are represented via specialized intrinsic functions in the generated code, and the generated code can be used as input to any C/C++ compiler supporting the target processor. Furthermore, the specialized instruction set of the target processor is described in a parameterized way using a target processor-independent architecture description approach, thus allowing the support of any processor. The compiler has been used for the generation of application code for two different ASIPs for several benchmarks. The code generated by the compiler achieves a speedup between 2× --74× and 2× --97× compared to the code generated by the MathWorks MATLAB-to-C compiler. Experimental results also prove that the compiler efficiently exploits SIMD custom instructions achieving a 3.3 factor speedup compared to cases where no SIMD processing is used. Thus the compiler can be employed to reduce the development time/effort/cost and time to market through raising the abstraction of application design in an embedded systems/system-on-chip development context.

The ISP (for Instruction Set Processor) notation was developed for a text [Bell& Newell, 1971] to precisely describe the programming level of a computer in terms of its Memory, Instruction Format, Data Types, Data Operations, Interpreting a Specific Instruction Set.

Application-specific instruction-set processors (ASIPs) allow the designer to extend the instruction set of the base processor with selected custom instructions to tailor-fit the application. In this paper, with the help of a motivational example, we first demonstrate that different custom instructions are vulnerable to faults with varying probabilities. This shows that by ignoring the vulnerability to faults, traditional methods of instruction set customization can provide no guarantees on the reliability of the system. Apart from such inherent disparity in error vulnerability across custom instructions, each custom instruction can have multiple implementation choices corresponding to varying hardened levels. Hardening reduces the vulnerability to errors but this comes at the overhead of area costs and reduced performance gain. In this paper, we propose a framework to select custom instructions and their respective hardening levels such that reliability is optimized while the performance gain is satisfied and area costs are met as well. Our framework is based on a novel analytical method to compute the overall system reliability based on the probability of failure of individual instructions. Wide range of experiments that were conducted illustrate how our tool navigates the design space to reveal interesting tradeoffs.

In recent years, the use of extensible processors has been increased. Extensible processors extend the base instruction set of a general-purpose processor with a set of custom instructions. Custom instructions that can be implemented in special hardware units make it possible to improve performance and decrease power consumption in extensible processors. The key issue involved is to generate and select automatically custom instructions from a high-level application code. In this paper, we propose an efficient and flexible algorithm for the exact enumeration of custom instructions. The algorithm can be tuned to generate all possible patterns or only connected patterns. Compared to a previously proposed well-known algorithm, our algorithm can achieve orders of magnitude speedup.

Incorporating user-oriented features usually found only in much larger computers, the first models of the Eclipse line, the $100 and $200, use a high speed micro-programmed central processor, and can run with either; core or semiconductor memories, or both. The core and semiconductor memories are available with an error detection and correction feature that can find and correct; single bit errors caused by the computer. The semiconductor memories use a high-speed cache to increase memory speed. The Eclipse $100, the smaller of the two computers, will be used by oems or by end users who need a smaller system to meet their requirements. The Eclipse $100 is 5-1/4 inches high, and holds six standard Data General printed circuit boards. It costs $9200, with 16k bytes of core memory, and $10,700 with 16k bytes of semiconductor memory. Eclipse $100 deliveries will begin in December. The Eclipse $200, a system-oriented computer that can hold 16 printed circuit boards, will be used by system builders or end users who will build large scale computing systems around it. The Eclipse $200 is 10-1/2 inches high, and costs $16,300 with 32k bytes of core memory, and $19,300 with 32k bytes of semiconductor memory. Deliveries of the Eclipse $200 will begin in February. The instruction set of both Eclipse computers is microprogrammed in the central processor. There are over 40 new instruction in the Eclipse computers. Programs written on Nova computers will run on either the Eclipse $100 or $200. The central processor includes a Writeable Control Store making up to 256, 56-bit words available to write specialized micro-programmed instructions. The instruction set is enhanced to help programmers writing in assembly language or high-level language programs. Hardware memory stacks, supported by comprehensive instructions, make programming more efficient, while block, word, byte and bit manipulation instructions improve system performance. Instructions are both single word and double word instructions.

Multimedia is a key element in human-computer interaction systems. Multimedia applications, however, are among the most dominant computing workloads driving innovations in high performance and low power imaging systems. Parallel implementations of multimedia applications mostly focus on the use of parallel computers. Modern general-purpose processors, however, have employed multimedia extensions (e.g., MMX, VIS, MAX, AltiVec) or subword parallel instructions to their instruction set architectures to improve the performance of multimedia. This paper quantitatively evaluates the impact of multimedia extensions on multiprocessor systems to exploit subword level parallelism (SLP) in addition to data level parallelism (DLP). Experimental results for a set of multimedia applications on a representative multiprocessor array shows that MMX (a representative Intel’s multimedia extension) achieve an average speedup ranging from 3x to 5x over the same baseline multiprocessor array. MMX also outperforms baseline in both area efficiency (a 13% increase) and energy consumption (a 73% decrease), resulting in better component utilization and sustainable battery life. These results demonstrate that MMX is a suitable candidate for mobile multimedia computing systems.KeywordsMobile multimedia computing systemsMultimedia extensionsMultiprocessor arraysParallel processing

The simulation of parallel computers is discussed. In particular, a technique, called cross-profiling, that can be used to improve the efficiency of these simulations substantially is presented and evaluated. Cross-profiling, along with another simulation technique called execution-driven simulation, can be used to simulate one processor's instruction set (the target processor) with another processor that has a different instruction set (the host processor). Moreover, this technique is significantly faster than the usual method where several host instructions are executed to emulate the effect of executing a single instruction of the target processor. The cross-profiling technique is introduced, and it is shown how it can be combined with execution-driven simulation. The results of several experiments that demonstrate that the error introduced by cross-profiling is typically less than 1% are presented. >

The level of support for high level programming languages (HLPLs), despite the claim of support by some of the newly introduced microprocessors, is inadequate despite the falling (rising) cost of hardware (software). Computer systems that are to be used to run programs written exclusively in HLPLs have a need for a multiprocessor/multiarchitecture microprocessor design (M3D); the personal/desk-top computers are prime examples. The HLPLs that will be used in programming these systems will be grouped according to their structures. Each group of languages will require their own instruction set; the hardware and software needs will determine the type of architecture configuration, i.e. aspects such as: register-to-register, memory-to-memory, stack, or a combination of these. The overall system should be divided up into functional units, e.g. ALU, compiler/translator, etc. Each functional or subfunctional unit will be implemented in software, firmware, hardware, or a combination of these with implementation decision based on the speed criticality, cost, technology, and the need to modify the unit. This approach will lead to a cop-down-design, and will also reduce the semantic gap, software and system cost, and down-time.

Multimedia instruction set extensions has become a prominent feature in desktop microprocessor platforms, promising superior performance on a wide range of floating-point and integer signal processing, multimedia, and scientific applications. Nevertheless, the question remains whether or not these multimedia extensions can be applied to improve the performance of general, integer intensive applications. The answer to this question is important and could be used to direct research and development of compiler algorithms and refinements to multimedia architectures. In this paper, we answer the question of whether integer programs exhibit enough sub-word level parallelism (SLP) to facilitate performance improvements through use of multimedia extensions. Using a highly optimizing compiler and a simulator for an aggressive SLP architecture, we measured available SLP in a range of integer benchmarks. Our measurements show that these applications exhibit significant levels of SLP. Using the most aggressive simulator settings, dynamic instruction count reductions of 17 to 36 percent were observed. However, detailed examination of the data indicates that much of this parallelism is equivalent to instruction-level parallelism (ILP) and could just as easily be exploited by a traditional ILP architecture. Our findings indicate that researchers should focus their efforts on exploiting SLP in floating-point intensive and multimedia applications.

A method for the identification of stuck-at bits on a data bus is described. Faulty data words are compared to isolate the stuck-at bits. A similar method can be used to identify an instruction which does not execute correctly in a processor instruction set. Here, faulty programmes, or faulty programme segments, are compared to isolate the faulty instruction. For both bus and instruction fault cases, probabilistic analyses are given with explicit formulas and data for the mean number of faulty samples required for diagnosis, and also the associated standard deviation. Both of these procedures use on-line data and are suitable for the diagnosis of intermittent faults.

Chapter 6 - Instruction Usage Examples

The architecture and instruction set of a second-generation VLSI digital signal processor are described. This processor represents a significant advance in VLSI digital signal processors. The device may be differentiated from its predecessors by the fact that it more closely resembles a true microprocessor than other DSP microcomputers. Its multiprocessor capabilities further distinguish it, allowing for much more flexibility in overall system design. The architecture of the device allows a dual bus structure to be maintained on-chip, while external bus hardware requirements are minimized via the multiplexing of these busses externally. Some of the notable features incorporated onto the device include two large on-chip RAM blocks, large external program/data address spaces, single-cycle multiply/accumulate instructions, hardware and instructions for efficient memory management, and a versatile multiprocessor interface.

Equivalent complex FIR (finite impulse response) lowpass filters with sampling rate reduction are described whereby the filter structure is matched to the instruction set of a special signal processor. These filters are suitable for application in FSK (frequency-shift keyed) modems, particularly in connection with the full-duplex two-wire technique without hybrids. Results are presented on the practical prototype of an FSK modem using the proposed approach. >

The design of an extremely high performance programmable digital filter of novel architecture, the LLL Programmable Digital Filter, is described. The digital filter is a high-performance multiprocessor having general purpose applicability and high programmability; it is extremely cost effective either in a uniprocessor or a multiprocessor configuration. The architecture and instruction set of the individual processor was optimized with regard to the multiple processor configuration. The optimal structure of a parallel processing system was determined for addressing the specific Navy application centering on the advanced digital filtering of passive acoustic ASW data of the type obtained from the SOSUS net. 148 figures. (RWR)