The Impact of Multimedia Extensions for Multimedia Applications on Mobile Computing Systems

Multimedia applications are among the most dominant computing workloads driving innovations in high performance and cost effective systems. In this regard, modern general-purpose microprocessors have included multimedia extensions (e.g., MMX, SSE, VIS, MAX, ALTIVEC) to their instruction set architectures to improve the performance of multimedia with little added cost to microprocessors. Whereas prior studies of multimedia extensions have primarily focused on a single processor, this paper quantitatively evaluates the impact of multimedia extensions on system performance and efficiency for different number of processing elements (PEs) within an integrated multiprocessor array. This paper also identifies the optimal PE granularity for the array system and implementation technology in terms of throughput, area efficiency, and energy efficiency using architectural and workload simulation. Experimental results with cycle accurate simulation and technology modeling show that MMX-type instructions (a representative Intel’s multimedia extensions) achieve an average speedup ranging from 1.24( (at a 65,536 PE system) to 5.65( (at a 4 PE system) over the baseline performance. In addition, the MMX-enhanced processor array increases both area and energy efficiency over the baseline for all the configurations and programs. Moreover, the highest area and energy efficiency are achieved at the number of PEs between 256 and 1,024. These evaluation techniques composed of performance simulation and technology modeling can provide solutions to the design challenges in a new class of multiprocessor array systems for multimedia.

This paper describes the architectural extensions to the PA-RISC 1.1 architecture to enable 64-bit processing of integers and pointers. It also describes MAX, the Multi-media Acceleration eXtensions which speed up the processing of multimedia and other applications with parallelism at the intra instruction, or subword, level. Other additions to the PA-RISC 2.0 architecture include performance enhancements with respect to memory hierarchy management, branch penalty reduction, and floating-point performance.

Multimedia instruction set extensions has become a prominent feature in desktop microprocessor platforms, promising superior performance on a wide range of floating-point and integer signal processing, multimedia, and scientific applications. Nevertheless, the question remains whether or not these multimedia extensions can be applied to improve the performance of general, integer intensive applications. The answer to this question is important and could be used to direct research and development of compiler algorithms and refinements to multimedia architectures. In this paper, we answer the question of whether integer programs exhibit enough sub-word level parallelism (SLP) to facilitate performance improvements through use of multimedia extensions. Using a highly optimizing compiler and a simulator for an aggressive SLP architecture, we measured available SLP in a range of integer benchmarks. Our measurements show that these applications exhibit significant levels of SLP. Using the most aggressive simulator settings, dynamic instruction count reductions of 17 to 36 percent were observed. However, detailed examination of the data indicates that much of this parallelism is equivalent to instruction-level parallelism (ILP) and could just as easily be exploited by a traditional ILP architecture. Our findings indicate that researchers should focus their efforts on exploiting SLP in floating-point intensive and multimedia applications.

Medical imaging is classified into different modalities such as ultrasound, X-ray, computed tomography (CT), positron emission tomography (PET), magnetic resonance imaging (MRI), single-photon emission tomography (SPECT), nuclear medicine (NM), mammography, and fluoroscopy. Medical imaging includes various imaging diagnostic and treatment techniques and methods to model the human body, and therefore, performs an essential role to improve the health care of the community. Medical imaging, scans (such as X-Ray, CT, etc.) are essential in a variety of medical health-care environments. With the enhanced health-care management and increase in availability of medical imaging equipment, the number of global imaging-based systems is growing. Effective, safe, and high-quality imaging is essential for the medical decision-making. In this chapter, we proposed a medical imaging-based high-performance hardware architecture and software programming toolkit called high-performance medical imaging system (HPMIS). The HPMIS can perform medical image registration, storage, and processing in hardware with the support of C/C++ function calls. The system is easy to program and gives high performance to different medical imaging applications.

In this paper, we present an implementation of a vectorizing C compiler for Intel's MMX (Multimedia Extension). This compiler would identify data parallel sections of the code using scalar and array dependence analysis. To enhance the scope for application of the subword semantics, our compiler performs several code transformations. These include strip mining, scalar expansion, grouping and reduction, and distribution. Thereafter inline assembly instructions corresponding to the data parallel sections are generated. We have used the Stanford University Intermediate Format (SUIF), a public domain compiler tool, for our implementation. We evaluated the performance of the code generated by our compiler for a number of benchmarks. Initial performance results reveal that our compiler generated code produces a reasonable performance improvement (speedup of 2 to 6.5) over the the code generated without the vectorizing transformations/inline assembly. In certain cases, the performance of the compiler generated code is within 85% of the hand-tuned code for MMX architecture.

The huge processing power needed by multimedia applications has led to multimedia extensions in the instruction set of microprocessors which exploit subword parallelism. Examples of these extended instruction sets are the Visual Instruction Set of the UltraSPARC processor, the AltiVec instruction set of the PowerPC processor, the MMX and ISS extensions of the Pentium processors, and the MAX-2 instruction set of the HP PA-RISC processor. Currently, these extensions can only be used by programs written in assembly language, through system libraries or by calling specialized macros in a high-level language. Therefore, these instructions are not used by most applications. We propose two code generation techniques to produce native code using these multimedia extensions for programs written in a high-level language: classical vectorization and vectorization by unrolling. Vectorization by unrolling is simpler than classical vectorization since data dependence analysis is reduced to acyclic control flow graph analysis. Furthermore, we address the problem of unaligned memory accesses. This can be handled by both static analysis and dynamic runtime checking. Preliminary experimental results for a code generator for the UltraSPARC VIS instruction set show that speedups of up to a factor of 4.8 are possible, and that vectorization by unrolling is much simpler but as effective as classical vectorization.

Application-specific extensions of a processor provide an efficient mechanism that meets the growing performance and power demands of portable embedded applications such as interactive multimedia communications. This work investigates the use of both the luminance and chrominance components in color image- and video-processing applications and proposes a color-aware instruction set extension (CAX) that improves the performance of color multimedia-processing applications. The CAX ISA is able to exploit a new level of subword parallelism not reachable by current multimedia extensions. Unlike typical multimedia extensions (e.g., Intel MMX, MIPS MDMX, and AMD 3DNow!), CAX instructions support parallel operations on two-packed 16-bit (6:5:5) YCbCr color pixels in a 32-bit datapath width and obtain substantial performance and code density improvements through direct support for color data processing rather than depending solely on generic subword parallelism. The results on a set of media benchmark applications indicate that the CAX versions achieve a speedup ranging from 3x to 5.8x while reducing energy consumption from 68% to 83% over the baseline versions on an identically-configured, dynamically-scheduled superscalar processor. The CAX versions also outperform the MDMX (MIPS multimedia extension) performance.

A novel reduced-size endoscope system based on a laser-scanning technology has been developed by the authors. This system employs specific silicon micromirrors and ensures a high-resolution color imaging with improved characteristics. A critical part of the device is its data-acquisition, control, and processing (DACP) system for real-time handling of the collected digital images. The supporting software is an event-driven application for the MS-Windows operating system that incorporates important features such as improved portability through the open PC architecture, cost effectiveness, high performance, and efficient scalability by using a symmetric multiprocessing desktop computer. In this paper, a presentation of the DACP system is performed with a focus in the software developed, which exploits the multithreading technology, resulting in a high-performance endoscope device

Recent developments in the design and fabrication of large two-dimensional arrays of optoelectronic devices for parallel optical processing and interconnections has impacted the need for high performance and cost effective optical imaging systems.

As wireless video products evolve, they demand more sophisticated processing at higher resolutions and frame rates. Computational performance and energy efficiency have become critical design issues. This paper presents the Quantized Color Pack eXtension (QCPX) combined with a loop unrolling (LU) technique to improve execution performance and energy efficiency of color image and video processing applications. QCPX applied to a 32-bit datapath processor supports parallel operations on two packed 16-bit YCbCr (Y: luminance, Cr and Cb: chrominance) color pixels, providing greater subword-level parallelism by increasing the number of smaller color pixels packed into a word. Instruction-level parallelism can be further enhanced through loop unrolling. These techniques provide greater performance and efficiency for multimedia workloads on mobile systems. Experimental results on a set of media benchmark applications indicate that the LU plus QCPX-optimized version achieves a speedup ranging from 3.8 to 7.9 while reducing the energy consumption from 76% to 87% over the baseline version on identically configured, dynamically scheduled ILP superscalar processors. The LU plus QCPX-optimized version also outperforms the LU plus MDMX-like (MIPS’s multimedia extension) version.

Efficient Parallel Nonlinear Multigrid Relaxation Algorithms for Low-Level Vision Applications

Multimedia and DSP applications have been widely present in embedded devices. Due to their intrinsic nature, such application domains are benefited from Data Level Parallelism (DLP) exploitation, which is mostly employed in current embedded platforms by using vectorization techniques extending the underlying ISA. However, such strategy relies on specific library which affects software productivity and compiler support, such as ARM auto-vectorization approach, which breaks binary compatibility. This work proposes a transparent Dynamic SIMD Assembler (DSA) that is capable of detecting vectorizable code regions at runtime without requiring specific library or compilers. As a case study, we coupled the DSA to a 128-bit wide ARM NEON Engine. Results show that the proposed approach shows performance improvements of 31% over the original execution (without DLP exploitation). In addition, Dynamic SIMD Assembler, besides keeping binary compatibility, outperforms ARM auto-vectorization technique in 6%.

Recent smart devices have adopted heterogeneous multi-core processors which have high-performance big cores and low-power small cores. Unfortunately, the conventional task scheduler for heterogeneous multi-core processors does not provide appropriate amount of CPU resources for multimedia applications (whose QoS is important to users), resulting in energy waste; it often executes multimedia applications and non-multimedia applications on the same core. In this paper, we propose an advanced task scheduler for heterogeneous multi-core processors, which provides appropriate amount of CPU resources for multimedia applications. Our proposed task scheduler isolates multimedia applications from non-multimedia applications at runtime, exploiting the fact that multimedia applications have a specific thread for video/audio playback (to play video/audio, a multimedia application should use a function that generates the specific thread). Since multimedia applications usually require a smaller amount of CPU resources than non-multimedia applications due to dedicated hardware decoders, our proposed task scheduler allocates the former to the small cores and the latter to the big cores. In our experiments on an Android-based development board, our proposed task scheduler saves system-wide (not just CPU) energy consumption by 8.9 percent, on average, compared to the conventional task scheduler, preserving QoS of multimedia applications. In addition, it improves performance of non-multimedia applications by 13.7 percent, on average, compared to the conventional task scheduler.

The Multi-Level Computing Architecture (MLCA) is a novel parallel System-on-a-Chip architecture targeted for multimedia applications. It features a top level controller that automatically extracts task level parallelism using techniques similar to how instruction level parallelism is extracted by superscalar processors. This allows the MLCA to support a simple programming model that is similar to sequential programming. In order to assist programmers to easily and efficiently port multimedia applications to the MLCA programming model, a compilation environment is designed. This compilation environment enhances parallelism in MLCA programs by applying three simple code transformations that are based on known compiler optimizations. In this paper, we describe the MLCA architecture, its programming model, its compilation environment and an evaluation of its performance. Our experimental evaluation with three real multimedia applications and an MLCA simulator shows that the MLCA is a viable architecture and scaling speedups can be obtained using the compilation environment with little programmer effort.

I/O parallelism is considered to be a promising approach to achieving high performance in parallel data warehousing systems where huge amounts of data and complex analytical queries have to be processed. This paper proposes a parallel secondary data cube storage structure (PHC for short) to efficiently support the processing of range sum queries and dynamic updates on data cube using parallel computing systems. Based on PHC, two parallel algorithms for processing range sum queries and updates are proposed also. Both the algorithms have the same time complexity, O(logd n/P). The analytical and experimental results show that PHC and the parallel algorithms have high performance and achieve optimum speedup.