Preliminary design of an advanced programmable digital filter network for large passive acoustic ASW systems. [Parallel processor

A finite impulse response (FIR) programmable filter is implemented using computation sharing multiplication (CSHM) technique to reduce power consumption and improve performance. Both carry select adders (CSLA) and carry look-ahead adders (CLA) are used to determine power consumption, throughput and area of the proposed design. A 10-tap programmable FIR digital filter was implemented in CMOS 180 nm technology and a maximum clock frequency of 1.42 GHz was achieved. The area is determined to be 516 K transistors with latency of 131 clock cycles and power consumption of 2.966 W.

A programmable FIR digital filter based on canonical-signed-digit (CSD) computation sharing multiplier is presented in this paper. The proposed CSD-based computation sharing multiplier can not only relax the critical path but also reduce the hardware cost compared to the binary computation sharing multiplier. It can reduce the cost by 44% of the binary computation sharing FIR filter with 112% clock speed. Moreover, the cost and speed of the programmable FIR digital filter are also simulated and analyzed in terms of the precomputation alphabet bitwidth, the multiplier resolution, and the number of filter tap. The results show that the optimal cost and speed can be more easily obtained at the same time in the CSD-based computation sharing programmable FIR filter than in the binary approach.

This paper presents the design and the implementation of a low power bang-bang all digital phase locked loop (BBADPLL). The design of the proposed architecture is based on the programmable coefficients of the digital loop filter (DLF) that manages the tradeoffs between stability and jitter of a closed loop. A proposed simple digital controlled oscillator (DCO) based on three stages ring oscillator provides a wide frequency range, and proven to be of lower area and power compared to arrayed DCO. The proposed design results in a significant reduction in the area and power compared to other time-to-digital converter (TDC) based ADPLL architectures. This reduction results from eliminating the need for complex, power, and area consuming TDC block, and arrayed DCO. A counter-based frequency acquisition loop using a binary search algorithm reduced the lock-in time significantly compared to similar work. The proposed BBADPLL architecture was implemented on TSMC CMOS 65nm technology with a frequency range 5–10GHz and a frequency resolution equals to 500MHz. The lock-in time is 2.4µs. The peak-to-peak period jitter and the RMS jitter at 10GHz are 1.49ps and 0.19ps, respectively. The total power consumed at 10GHz is only 2.7mWatt and the total area of the proposed ADPLL is 4372µm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , which is very small compared to other published architectures.

The architecture, salient applications, and design method of an experimental video finite impulse response (FIR) digital filter integrated circuit (IC) is described. The authors have used an improved multiplier/accumulator architecture to achieve high throughput and have included hardware to enhance testability. This chip covers many of the frequency filtering, decimation/interpolation, and other one- and two-dimensional digital signal processing applications. There are facilities on the device to allow cascading of several ICs for building higher-order filters or for obtaining other configurations. This very high performance programmable digital FIR filter circuit has been fabricated in 0.9- mu m CMOS technology using automatic custom CAD tools. Using such tools as automatic netlist optimizer and automatic layout, the authors created the layout mask from the block diagram in approximately 10 weeks. Although the device was targeted for video frequency applications, it functioned well beyond that range. >

This paper presents a fully integrated and spur-free fractional frequency synthesizer based on a low noise 42.5-GHz SiGe quad-core VCO locked on a standard 40-MHz crystal unit. Consequently, optimal SNR is obtained for narrow bandwidth. Reference spurs are below −80 dBc thanks to a programmable digital loop filter in the range of 0.5 kHz to 50 kHz. The PLL architecture digitally controls the phase offset for beam forming and linearizes the VCO to ensure constant cut-off frequency and optimal SNR. Contrary to two-point modulation which requires calibration, radar modulation is simply added in one point after loop filter and before VCO linearizer. These blocks - XO, PLL and frequency doubler - are packaged in a BGA substrate.

The architecture of a codec in which the echo cancellation is done in two stages, an analog hybrid to reduce the echo level at the input of the A/D converter and a programmable digital balance filter, is presented. The design problems connected with this architecture, such as the signal-to-noise performance of the A/D converter and the limiting effects of the variation of the analog components on the echo cancellation performance of the device and on the structure of the digital balance filters, are discussed. These results were used in the design of a single-power-supply CMOS device implemented in 1.5- mu m technology using Sigma Delta modulation techniques for A/D and D/A conversion. Its echo cancellation performance is sufficiently high that only one set of coefficients per national standard is necessary. >

A programmable digital filter workstation is discussed that provides classical analysis and design tools for the electrical engineering student. Further, through the data acquisition system, the student can test the design on actual audio signals online. With the provision of this feature within a single workstation, the user receives instant feedback as to the quality of the digital filter design. Some examples of digital filter design and actual time responses are presented to illustrate the features of the workstation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The Three-Array Processor (TAP III) beamforming system incorporating both wide-band time-domain beamforming and narrow-band frequency-domain beamforming is described. This paper briefly develops the beamforming theory and shows how the fast Fourier transform (FFT) is applied to accomplish frequency-domain beamforming. The frequency-domain beamformer operates in the frequency domain to form beams and power spectrum data over narrow frequency bands of interest. A real-time digital filtering technique is used to extract the narrow bands of interest from the broad-band input signal. The frequency-domain beamformer accomplishes real-time digital filtering and beamforming by using a high-speed array processor to do the complex calculations and data handling required by the algorithm. The time-domain beamformer operates in parallel with the frequency-domain beamformer to form up to 16 broad-band beams in the time domain. A programmable all-pass digital filter is used to create the fine time delays required by the time-domain beamformer.

The huge processing power needed by multimedia applications has led to multimedia extensions in the instruction set of microprocessors which exploit subword parallelism. Examples of these extended instruction sets are the Visual Instruction Set of the UltraSPARC processor, the AltiVec instruction set of the PowerPC processor, the MMX and ISS extensions of the Pentium processors, and the MAX-2 instruction set of the HP PA-RISC processor. Currently, these extensions can only be used by programs written in assembly language, through system libraries or by calling specialized macros in a high-level language. Therefore, these instructions are not used by most applications. We propose two code generation techniques to produce native code using these multimedia extensions for programs written in a high-level language: classical vectorization and vectorization by unrolling. Vectorization by unrolling is simpler than classical vectorization since data dependence analysis is reduced to acyclic control flow graph analysis. Furthermore, we address the problem of unaligned memory accesses. This can be handled by both static analysis and dynamic runtime checking. Preliminary experimental results for a code generator for the UltraSPARC VIS instruction set show that speedups of up to a factor of 4.8 are possible, and that vectorization by unrolling is much simpler but as effective as classical vectorization.

The architecture and instruction set of a second-generation VLSI digital signal processor are described. This processor represents a significant advance in VLSI digital signal processors. The device may be differentiated from its predecessors by the fact that it more closely resembles a true microprocessor than other DSP microcomputers. Its multiprocessor capabilities further distinguish it, allowing for much more flexibility in overall system design. The architecture of the device allows a dual bus structure to be maintained on-chip, while external bus hardware requirements are minimized via the multiplexing of these busses externally. Some of the notable features incorporated onto the device include two large on-chip RAM blocks, large external program/data address spaces, single-cycle multiply/accumulate instructions, hardware and instructions for efficient memory management, and a versatile multiprocessor interface.

The area and power consumption of oversampled data converters are governed largely by the associated digital decimation and interpolation filters. This paper presents an area- and power-efficient programmable digital filter for decimation and interpolation in digital-audio applications. Several architectural and implementation features reduce the complexity of the filter and allow its implementation in a die area of only 3670 mils/sup 2/ (2.37 mm/sup 2/). The filter is first described in the context of decimation for an oversampled A/D converter employing a second-order sigma-delta modulator. Extensions of the filter to accommodate other modulators, as well as to perform interpolation for oversampled D/A conversion, are then discussed.

Failure to account for time‐varying detection ranges when inferring space use of marine species from passive acoustic telemetry data can bias estimates and result in erroneous biological conclusions. This potential source of bias is widely acknowledged but often ignored in practice due to a lack of available statistical methods. Here, we describe and apply a spatial point process model for estimating individual centres of activity (COAs) from acoustic telemetry data that can be modified to account for both receiver‐ and time‐specific detection probabilities. We use simulation testing to evaluate the suitability of the proposed models for estimating COAs and compare their performance to that of the popular mean‐weighted COA method for a variety of scenarios. We illustrate how the approach can be applied to correct for variable detection ranges by integrating data from moored test tags and demonstrate how accounting for time‐varying detection probabilities can impact space use estimates by fitting the model to data collected from a black sea bass (Centropristis striata) on a receiver array off the east coast of the United States. The proposed model reduced bias in COA estimates, particularly when tagged individuals occurred along the periphery of the receiver array. The test tag‐integrated model largely corrected the bias associated with receiver‐ and time‐specific detection probabilities. When applied to the black sea bass detection data, the model revealed fine‐scale movements not apparent when detection ranges were assumed constant. Spatial management practices for coastal marine species are often based on trends in space use inferred from passive acoustic telemetry data, which can be misinterpreted when factors influencing detection ranges are not accounted for. Our approach provides a general framework for estimating individual COAs that can be modified on a study‐specific basis to ensure resulting patterns of space use reflect a species’ movements and behaviour, rather than variation in receiver detection ranges.

Equivalent complex FIR (finite impulse response) lowpass filters with sampling rate reduction are described whereby the filter structure is matched to the instruction set of a special signal processor. These filters are suitable for application in FSK (frequency-shift keyed) modems, particularly in connection with the full-duplex two-wire technique without hybrids. Results are presented on the practical prototype of an FSK modem using the proposed approach. >

Digital filters (Hamming, 1998; Chen, 2001) are versatile, practical and effective. They can be used in most computerized applications of modern technology and science. Nearly every person in technologically developed regions daily encounter digital filters in cars, dvdrecorders, computers, telecommunication systems etc. Usually, digital filters are designed and optimized by signal processing experts for standardized tasks in specific systems. Extensive work may result in advanced and complex filters. This is motivated by massive duplication. The marginal production cost for a filter is practically zero and the development cost per unit is negligible. The advantages of using digital instead of analogue filters are often profound. Not only are the costs negligible, their flexibility makes it possible to achieve superior results. Even unstable operations can be realized by means of reversed filtering. The limitations of digital filters are mainly mathematical, rather than physical as for analogue filters. Dynamic measurements condense observations into quantitative representations (Hessling, 2010a). Dynamic methods for improving, interpreting and assessing the quality of measurements are relatively scarce. These methods can be formulated in terms of ideal prototype systems acting on physical signals to produce the desired information. A dynamic calibration procedure is usually required to find the model from which such prototypes are determined. Ideal prototypes are approximated and optimized into realizable prototypes which can be cast into digital filters by means of sampling. These filters differ from most common filters of today. They are dedicated filters with a high level of adaptation and flexibility, designed to improve or simplify the evaluation of a wide range of measurements for many different purposes. The common denominator of all filters is that they are intended to provide a supporting link of standardized dynamic analysis between the ‘raw’ measurements and an inexperienced destined user. The digital filters and the measurement devices are preferably seamlessly integrated in the final application, which most often already has a computer program for administrating the measurement. The motivation for making any measurement is to extract information. The desired information is rarely identical to measured signals. Measured signals need to be processed or analyzed. Signals may be corrected. To determine how wrong the result might be, the uncertainty needs to be estimated. The measurement system may be one part of a complex dynamic system, for instance, an accelerometer attached to a vibrating vehicle. Sometimes transformations between various points in space, or electrical quantities etc. are required. We might be interested in the consequences of measured signals. The impact of interest is 6

Two ecological acoustic recorders were deployed in Southern Sri Lanka to study the presence of the assumed resident population of pygmy blue whales. A major shipping lane runs through this feeding area of the whales and it has been recognized by the International Whaling Commission as well as International Maritime Organization as a risk area for ship strikes. To implement any management practices to mitigate ship strikes, a solid scientific basis is needed. Such data must include information on migration and movement patterns of the whale population. Therefore, combining the passive acoustic monitoring data with existing visual transect survey results gives further insight to choosing suitable management practices to address the issue. Passive acoustic monitoring data indicate that at least part of the population is indeed resident in the area throughout the year but there is both seasonal and inter-annual variation in the acoustic activity of the whales. The acoustic data were further combined with data from oceanographic models and the results indicate there is no single parameter explaining the variation, although the acoustic activity has weak correlation with rainfall patterns. The pygmy blue whale call detections also appear to increase during periods of stronger upwelling in Southern Sri Lanka.