C/C++ Hardware Design for the Real World

In this chapter we discuss the topic of platform-based design, performance analysis and modeling of platforms for end-users from the standpoint of a provider of intellectual property – particularly, configurable and extensible processors – and of more complex aggregates of processors and other devices, which can be said to form a “configurable platform of configurable processors”. In particular, we answer the questions of what platform providers must provide in the way of models, characterization parameters and other important design data; the sources of these models and data, and ancillary design tools; the use model for the end user of the platform, and the current state of the art, and likely evolution of these trends. Being in the position of a provider of configurable processors brings a unique perspective to this analysis.

In this paper, a performance analysis of two alternative designs of SHA-1 hash function and a pure software version, implemented in a configurable and extensible embedded processor (Tensilica's Xtensa LX2) is presented. The first alternative is exploiting extensibility of incorporated platform; the second one is exploiting configurability and extensibility. These two alternatives are compared to the pure software implementation in the same processor. The results showed that exploiting both configurability and extensibility leads to high performance SHA-1 implementation. Up to 490% increase in terms of throughput is observed, while the area is significantly reduced by 28%. This work aims to offer base implementations for comparisons with future opts that authors are already working on.

Bacterial foraging driven exploration of multi cycle fault tolerant datapath based on power-performance tradeoff in high level synthesis

This chapter takes a look at the real life application of technologies and techniques as discussed in the previous chapters. The first section discusses the emerging markets and technological trends in the clothing industry with regards to virtual clothing technologies. This is followed by a discussion of virtual garment prototyping. This discussion addresses current design and manufacturing paradigms and the online customization of garments, as well as their associated benefits, limitations and future challenges that need to be tackled. A practical example of such online customization is demonstrated by means of MIRALab’s Virtual Try On. The chapter ends with a discussion of the importance of collaboration in the production of garments, addressing such topics as Product Data Management, Product Lifecycle Management and co-design. This is followed by a technical proposal of a virtual garment platform enabling co-design, ranging from low-level communication to higher level user-management.

This paper presents the development of high level synthesis tools for finite impulse response (FIR) filtering application on the embedded system. A hardware description language (HDL) is used to describe the structure and behaviour of the electronic circuits and digital logic circuits. The HDL coder is a high level synthesis tool that converts the C/C++ files into.ngc files and then to generate bitstream. MATLAB is supported with Vivado in order to generate the MATLAB programming on FPGA board. Based on the least mean square (LMS) algorithm, FIR filter is developed by MATLAB generated with the HDL coder and compatible with FPGA hardware. Then, the developed algorithm is implemented and automated the verification of HDL code on Xilinx Zedboard for FIR filtering and planning including with the cost estimation and hardware usage. Simulation implementation show that the experimental results of adaptive LMS-FIR from MATLAB and Vivado can perform well for system identification.

High-level synthesis (HLS) is the automatic compilation of software programs into custom hardware designs. With programmable hardware devices (such as FPGAs) now widespread, HLS is increasingly relied upon, but existing HLS tools are too unreliable for safety- and security-critical applications. Herklotz et al. partially addressed this concern by building Vericert, a prototype HLS tool that is proven correct in Coq (à la CompCert), but it cannot compete performance-wise with unverified tools. This paper reports on our efforts to close this performance gap, thus obtaining the first practical verified HLS tool. We achieve this by implementing a flexible operation scheduler based on hyperblocks (basic blocks of predicated instructions) that supports operation chaining (packing dependent operations into a single clock cycle). Correctness is proven via translation validation: each schedule is checked using a Coq-verified validator that uses a SAT solver to reason about predicates. Avoiding exponential blow-up in this validation process is a key challenge, which we address by using final-state predicates and value summaries. Experiments on the PolyBench/C suite indicate that scheduling makes Vericert-generated hardware 2.1× faster, thus bringing Vericert into competition with a state-of-the-art open-source HLS tool when a similar set of optimisations is enabled.

In the high-level synthesis (HLS) domain, more and more often the simulation vectors are specified at algorithmic level focussing on functional behavior. Due to the HLS and the inherent changes of the cycle-by-cycle behavior, simulation vector sets (SVS) specifying synchronous behavior cannot be reused on register transfer level (RTL). An automatic transformation of the algorithmic SVS is necessary to avoid a manual and time-consuming transformation phase. One critical part of the transformation process is to determine the mapping of the I/O operations of the algorithmic specification and of the I/O operations of the algorithmic SVS. Therefore, this paper presents three alternatives to solve this mapping problem, and describes their advantages, as well as their disadvantages.

This paper presents practical usage of C language based high level synthesis. Initially, our system LSI design flow is introduced. Then, applicable area of this tool flow is explained and various merits are discussed such as enabling concurrent design of hardware and software, high reusability of behavioral descriptions and flexibility and compactness of C synthesis based configurable processor, by using industrial design examples. Some statistical data are shown to demonstrate efficiency of C-based high level synthesis compared with RTL-based design.

It is generally accepted that a custom hardware implementation of a set of computations will provide superior speed and energy efficiency relative to a software implementation. However, the cost and difficulty of hardware design is often prohibitive, and consequently, a software approach is used for most applications. In this article, we introduce a new high-level synthesis tool calledLegUpthat allows software techniques to be used for hardware design. LegUp accepts a standard C program as input and automatically compiles the program to a hybrid architecture containing an FPGA-based MIPS soft processor and custom hardware accelerators that communicate through a standard bus interface. In the hybrid processor/accelerator architecture, program segments that are unsuitable for hardware implementation can execute in software on the processor. LegUp can synthesize most of the C language to hardware, including fixed-sized multidimensional arrays, structs, global variables, and pointer arithmetic. Results show that the tool produces hardware solutions of comparable quality to a commercial high-level synthesis tool. We also give results demonstrating the ability of the tool to explore the hardware/software codesign space by varying the amount of a program that runs in software versus hardware. LegUp, along with a set of benchmark C programs, is open source and freely downloadable, providing a powerful platform that can be leveraged for new research on a wide range of high-level synthesis topics.

This paper introduces co-processor synthesis -- a methodology that provides design benefits by implementing hardware co-processors directly from embedded software. The paper examines the design benefits in this new approach vs behavioral synthesis and configurable processor methodologies.

Spatial computing architectures pose an attractive alternative to mitigate control and data movement overheads typical of load-store architectures. In practice, these devices are rarely considered in the HPC community due to the steep learning curve, low productivity and lack of available libraries for fundamental operations. High-level synthesis (HLS) tools are facilitating hardware programming, but optimizing for these architectures requires factoring in new transformations and resources/performance trade-offs. We present FBLAS, an open-source HLS implementation of BLAS for FPGAs, that enables reusability, portability and easy integration with existing software and hardware codes. FBLAS' implementation allows scaling hardware modules to exploit on-chip resources, and module interfaces are designed to natively support streaming on-chip communications, allowing them to be composed to reduce off-chip communication. With FBLAS, we set a precedent for FPGA library design, and contribute to the toolbox of customizable hardware components necessary for HPC codes to start productively targeting reconfigurable platforms.

Domain-specific systems improve the performance of specific applications compared to general-purpose processing systems by deploying custom hardware accelerators. These hardware accelerators are generated using high-level synthesis (HLS) tools. The HLS tools enable a comprehensive design space exploration, optimizing the accelerators' compute performance. However, they often ignore the challenges of implementing the accelerators in a system-on-chip, particularly how they access memory. Our work introduces a buffering system design that improves accelerators' memory accesses by intelligently employing burst transactions to prefetch useful data from external memory to on-chip local buffers. Our design is dynamic, parametric, and transparent to the accelerators generated by HLS tools. We derive the buffering system parameters using appropriate compiler-based analysis passes and memory channel latency constraints. The proposed buffering system design results in, on average, 8.8× performance improvements while lowering memory channel utilization by 53.2% for a set of PolyBench kernels.

In the previous chapter we have considered shape detection per se and have decided (with a little biased guidance!) that parametric transformation is a good way of partitioning points on the boundary of a shape (Edge Image Data) into sets. Each set is then labelled by the parameters associated with the shape formed by those points. In order to be able to put such a theoretically powerful technique to good use it is necessary not just to ‘know’ about it but to understand it in a way that enables it to be implemented and manipulated to best advantage. However, the process of integral transformation is not an intuitively obvious one. Difficulty in visualizing the transformation process and its results may be compounded in that the intended user may not feel happy or safe handling sophisticated mathematical concepts. It is to these people that this chapter is addressed.

Chapter 5 - Conversion of existing biogas plants to waste-integrated biorefineries

The challenges of new embedded applications have conflicting requirements: complex algorithms, evolving standards, shorter product cycles dictate programmable solutions, and yet, high data bandwidth, compute power and lower power consumption dictate carefully crafted hardwired functional modules. An application specific instruction set processor (ASIP) is ideally suited to provide most of the advantages of hardwired logic, while maintaining the time-to-market and programmability advantages of a general purpose processor. This paper presents the unique blend of high compute performance and i/o bandwidth of the configurable and extensible Xtensa LX ASIP architectures. Xtensa LX provides high compute performance with wide instruction words using multiple operation slots that enable superscalar performance suitable for data-intensive applications. Xtensa LX also provides high I/O bandwidth through its multiple load/store units that provide parallel low latency access or external DMA access to local memories and virtually unlimited number of ports and queues directly connected to the processor core functional units and system control registers, which remove the I/O bottleneck of traditional processors. The advantages of Xtensa LX features are proven with their impressive performance results: 171.6 ConsumerMark on out-of-the-box simulation of EEMBC consumer suite and a BDTIsimMark2000^™ score of 6150 at 370MHz.