The Configurable Processor View of Platform Provision

In this paper, a performance analysis of two alternative designs of SHA-1 hash function and a pure software version, implemented in a configurable and extensible embedded processor (Tensilica's Xtensa LX2) is presented. The first alternative is exploiting extensibility of incorporated platform; the second one is exploiting configurability and extensibility. These two alternatives are compared to the pure software implementation in the same processor. The results showed that exploiting both configurability and extensibility leads to high performance SHA-1 implementation. Up to 490% increase in terms of throughput is observed, while the area is significantly reduced by 28%. This work aims to offer base implementations for comparisons with future opts that authors are already working on.

In previous chapters we have seen how system-level virtual prototypes get created and how they are often partitioned into pieces intended to be implemented as either software or hardware. This partitioning was done to manage costs and performance and to optimize many other attributes of the system. For the parts of the system intended to be hardware, several choices still remain. It is possible that those functionalities can be implemented using off-the-shelf components, such as processors or DSPs, or as components that require small extensions in order to meet the necessary requirements, such as configurable and extensible processors. It is likely that there will be a few components for which dedicated custom hardware is required and we now need to refine those models in ways that make them more amenable to the transformation process that is often called behavioral synthesis or high-level synthesis.

This work presents a SystemC-based design of custom SIMD instructions for accelerating media and telecom codes on a next-generation configurable, extensible processor. The SS_SPARC processing platform, incorporates a generic vector unit which can be extended with pipelined, SIMD computation units (datapaths) designed either with established (RTL-based) or in this case, hybrid (SystemC-RTL) methodologies. This work elaborates on a custom methodology for automatically encapsulating the data-parallel sections of the MPEG-4 XviD the G723.1 and G729A reference codes into a SystemC wrapper which is subsequently synthesized to RTL with a commercial SystemC-synthesis tool. The resulting RTL is then attached to the exposed vector unit of the SS_SPARC engine. The authors present results from a standard-cell RTL synthesis campaign and the VLSI implementation of a high-end (8-contexts, 256 bit) and a low-end (2-context, 128 bit) configuration of the vector engine for the workloads of interest

Opening Platforms: How, When and Why?

The study of climate-relevant processes in the atmosphere using airborne platforms is an important contribution to understanding our environment. The deployment of remote sensing instruments on aircraft or balloons requires powerful computer systems for data acquisition and instrument control. The ongoing trend towards further miniaturisation of instruments, with increasingly complex measurement tasks and higher data rates for use over longer flight durations, requires a new generation of control and processing units. These units must be significantly reduced in mass, volume and power consumption. In addition, a shift in data management from storage and post-processing to real-time data processing is required to reduce the increasing amounts of data and to transmit them to ground stations.Based on years of experience with the GLORIA (Gimballed Limb Observer for Radiance Imaging of the Atmosphere) instrument and its current miniaturised version, GLORIA-Lite, a modular and reconfigurable data acquisition and processing platform has been developed. This platform is specifically designed to meet the demanding requirements of future long-duration flights in harsh environments, with significant optimisations in weight, volume and power consumption. Using state-of-the-art multi-processor system-on-chip (MPSoC) modules, the platform enables real-time data processing while significantly reducing the need for data storage or transmission. Redundancy in hardware and software using the multiple processor cores, together with a supervisor circuit, makes the platform ready for harsh environments. Thanks to its compact form factor, the ruggedised and fully reprogrammable hardware is adaptable to a wide range of applications, further enhancing its versatility and potential for use in various scientific and technological missions.This presentation will show the prototype of the new processing platform, which will be used together with the GLORIA-Lite instrument during an upcoming balloon campaign. First processing steps and performance analysis will be presented.

Based on the whole process of computer-aided technology, a 3D animation data processing development platform based on artificial intelligence is designed and implemented. A random forest model for animation data processing and development is designed to mine the experience that can guide animation generation from the accumulated animation data. Based on the design goal and implementation principle of animation data processing and development platform, the attributes and categories of random forest model are abstracted. After standardizing a large number of historical data, the training sample set is obtained, and the random forest model is obtained after training. The parameters of the random forest model are continuously optimized by experiments, so that the learning model can better guide the dynamic animation data processing and development platform to generate animation to the satisfaction of users. The designed three-dimensional animation data processing and development platform interacts with the animation generation module, users, and system administrators. It can continuously receive the sample data of the animation generation module, automatically expand the number of training samples, analyze the status of the sample database, and put forward suggestions to the system administrator to update the learning model, so as to realize the initiative of learning. The experimental results show that the designed 3D animation data processing and development platform is effective and feasible.

Previously, collecting, storing, owning and, if necessary, digitizing data was vital for any data-driven application. Nowadays, we are swimming in data, whereby one could postulate that we are drowning. However, downloading vast data to local storage and subsequent in-house processing on dedicated hardware is inefficient and not in line with the big data processing philosophy. While the FAIR principles are fulfilled as the data is findable, accessible, and interoperable, the actual reuse of the data to gain new insights depends on the data user’s local capabilities. Scientists aware of the potentially available data and processing capabilities are still not able to easily leverage these resources as required to perform their work; while the analysis gap entailed by the information explosion is being increasingly highlighted, remediation lags.The core objective of the FAIRiCUBE project is to enable players from beyond classic Earth Observation (EO) domains to provide, access, process, and share gridded data and algorithms in a FAIR and TRUSTable manner. To reach this objective, we are creating the FAIRiCUBE HUB, a crosscutting platform and framework for data ingestion, provision, analysis, processing, and dissemination, to unleash the potential of environmental, biodiversity and climate data through dedicated European data spaces.In order to gain a better understanding of the various obstacles to leveraging available assets in regard to both data as well as analysis and processing modalities, several use cases have been defined addressing diverse aspects of European Green Deal (EGD) priority actions. Each of the use cases has a defined objective, approach, research question and data requirements.The use cases selected to guide the creation of the FAIRiCUBE HUB are as follows:Urban adaptation to climate change Biodiversity and agriculture nexus Biodiversity occurrence cubes Drosophila landscape genomics Spatial and temporal assessment of neighborhood building stock Many of the issues encountered within the FAIRiCUBE project are formally considered solved. Catalogues are available detailing the available datasets, standards define how the datasets are to be structured and annotated with the relevant metainformation. A vast array of processing functionality has emerged that can be applied to such resources. However, while all this is considered state-of-the-art in the EO community, there is a subtle delta blocking access to wider communities that could make good use of the available resources pertaining to their own domains of work. These include, but are not limited to:Identifying available data sources Determining fitness for use Interoperability of data with divergent spatiotemporal basis Understanding access modalities Scoping required resources Providing non-gridded data holdings in a gridded manner There is great potential in integrating the diverse gridded resources available from EO sources within wider research domains. However, at present, there are subtle barriers blocking this potential. Within FAIRiCUBE, these issues are being collected and evaluated, mitigation measures are being explored together with researchers not from traditional EO domains, with the goal of breaking down these barriers, and enabling powerful research and data analysis potential to a wide range of scientists.

The race towards further density increase in CMOS circuit integration is entering a new era where choices are needed for the device shrink. Beyond 20nm, a consensus says that MOSFETs will go fully depleted. They can either be 2D or 3D, i.e. 2D fully depleted silicon films on Oxide (FDSOI) or 3D with fully depleted silicon fins. We believe that FDSOI films allow continuing smoothly Moore's Law without introducing drastic design disruptive steps [1]. We have developed FDSOI Process and Design Platforms that are in the shrink trend from previous generations. Moreover, since FDSOI devices are compatible with the Bulk design rules and constraints, it becomes possible, within the same technology node, to hit the performance boost usually targeted with the next one. This has become of utmost importance today where the introduction of a new node gets complex and costly because of the delay to get appropriate advanced Lithography tools. In this presentation, we review the challenges for the 20nm FDSOI nodes by looking at performance, power and process complexity.

Performance analyses for embedded software construction with existing components require knowledge of performance characteristics of both application software and operating system (OS) services, especially those services that are critical for real-time applications. Since end users normally do not control the structure and implementation of OS services, but have to use them to meet the system-level performance constraints, it is essential and critical to characterize the performance of OS services with measurements. As such measurements are taken for performance analysis, not for comparison, the measurement methods should be different from those traditionally, used for comparison. In this paper we present an end-to-end method for measuring the performance of timing and scheduling services in selected real-time OSs for the performance modeling and analysis. The proposed method takes the factors of both OS implementations and application configurations into account to obtain the measured performance close to what applications will experience at runtime. The results have shown that the performance characteristics of OS services can be measured without instrumenting the kernel source code, and hence, can be reused for the analysis of a family of applications.

With the growing popularity of using multiprocessors in embedded systems, teaching multiprocessors in universities is becoming more and more important. FPGA-based configurable processors offer a low-cost, fast turnaround, and versatile design and implementation platform for this challenging task. This paper presents an introductory embedded systems design course that integrates configurable processors, FPGAs, and multiprocessor design and implementation. We emphasize hands-on hardware-software codesign skills by a series of carefully designed tutorials, lab assignments, and a comprehensive project on the Altera DE2 FPGA development board. Developing and teaching such a new course with no appropriate textbook available is quite challenging. The course has been popular and well received as reflected by the students evaluation and feedback.

Given the rapid expansion in cloud computing in the past few years, there is a driving necessity of having cloud workloads running on a backend servers analyzed and characterized for performance and power consumption. In this research, we focus on Hadoop framework and Memcached, which are distributed model frameworks for processing large scale data intensive applications for different purposes. Hadoop is used for short jobs requiring low response time; it is a popular open source implementation of MapReduce for the analysis of large datasets, while Memcached is a high performance distributed memory object caching system that could speed up throughput of web applications by reducing the effect of bottlenecks on database load. In this paper, we characterize different workloads running on Hadoop framework and Memcached for different processor configurations and microarchitecture parameters. We implement an analytical estimation model for performance and power using different server processor microarchitecture parameters. The proposed analytical estimation model uses analytical method to scale different processor microarchitecture parameters such as CPI with respect to processor core frequency. We also propose an analytical model to estimate power consumption scaling for different processor core frequency. The combination of both performance and power consumption analytical models enables the estimation of performance per watt for different cloud benchmarks. The proposed estimation models are verified to estimate power and performance with less than 10% error deviation.

With the miniaturization of integrated circuit technology and process, chips are getting smaller and smaller, and thus it results in fan-out packaging with RDL process was derived to extend the ball grid array design space. The applicable range of RDL now includes products in the fields of Networking, HPC, AI and even SiPh. And the new package types comprised of the RDL process include e-WLB, chip first FOCoS, chip last FOCoS, FO-PoP and 2.5D IC etc. The total pin count in FOCoS packaging can be more than ten times than that the pin counts in a large FCBGA packaging; the FOCoS package layout density can reach tens or even hundreds of times than FCBGA. High density and complex connectivity in FOCoS cause more difficult using traditional EDA tool for packaging design. In addition, the RDL process manufacturing equipment is different from that for traditional packaging substrate and it is more like the foundry process, so it is required to consider design rule check and LVS check flow compatible to IC design flow except for the package layout. It is necessary to have different methods and tools from that in the past to complete a reliable design. In this paper, there is an introduction about the new design flow and platform for high density package design and it describes the new design platform could overcome the difficulties of layout on high-density packages such as FOCoS. And then talking about FOCoS Assembly Design Kit (ADK) to provide to the IC or system designers, especially the new design rule checking tools and procedure, as well as example about how DRC tools plays an important role in RDL process improvement and design. In addition to checking the design rule for the layout, verifying the interconnections between the components in the package after design is very important to FOCoS packaging which is generally used in multiple dice integration such as homogeneous and heterogeneous integration design.

In offshore structural engineering, buoyant leg storage and regasification platform (BLSRP) is one of the recent innovative structural forms that is archived to suit industrial requirements. Proposed platform consists of a deck, which is connected to six buoyant leg structures (BLSs) through the hinged joints while BLS units are connected to the seabed using taut-mooring tethers. The conceived structural form is a hybrid concept, which restrains transfer of both rotational and translational responses from the BLS units to the deck and vice versa. The main advantage is the improved functionality in terms of increase in the storage and regasification capacity of liquefied natural gas. Experimental investigations are carried out on a scaled model of BLSRP (1:150) under regular waves for two different wave approach angles. Free vibration tests are carried out on the scaled model to estimate the natural periods; results show that BLSRP resembles a tethered compliant structure like tension leg platform (TLP) except showing relatively higher stiffness in the yaw degree-of-freedom. Geometric design of BLS units ensures a good recentring capability of the deck in all the translational degrees-of-freedom. Lesser heave response of deck, in comparison to that of the BLS units ensures comfortable and safe operability. Attempted study is a prime-facie towards design and development of offshore production and process platforms that can reduce the cost of oil and gas exploration.

Conceptual design, performance and stability analysis of a 200 passengers Blended Wing Body aircraft

Tomographic imaging is an important disease diagnosis method. Specific image workstation is usually needed to process and visualize 3D medical image gathered from tomographic imaging equipments, because this process is computation intensive. Specific image workstation is large and expensive, which limits size and price of medical tomographic imaging system. To break these limits, this paper presents an embedded 3D medical image processing and visualization platform based on common dual-core processor. The proposed system parallelizes 3D medical image processing and visualization computing process to meet system real-time requirements. Main contributions of this paper includes analysis of core 3D medical data processing and visualization algorithm, program parallelization method analysis and implementation, system performance measurement and analysis. Program analysis results show that the proposed system fully utilizes hardware resource, and meets low-end and space-efficient medical imaging system requirements.