SystemC-defined SIMD instructions for a CMP/SMT ASIC platform

In this chapter we discuss the topic of platform-based design, performance analysis and modeling of platforms for end-users from the standpoint of a provider of intellectual property – particularly, configurable and extensible processors – and of more complex aggregates of processors and other devices, which can be said to form a “configurable platform of configurable processors”. In particular, we answer the questions of what platform providers must provide in the way of models, characterization parameters and other important design data; the sources of these models and data, and ancillary design tools; the use model for the end user of the platform, and the current state of the art, and likely evolution of these trends. Being in the position of a provider of configurable processors brings a unique perspective to this analysis.

Accelerating program performance via short SIMD vector units is very common in modern processors, as evidenced by the use of SSE, MMX, and AltiVec SIMD instructions in multimedia, scientific, and embedded applications. To take full advantage of the vector capabilities, a compiler needs to generate efficient vector code automatically. However, most commercial and open-source compilers still fall short of using the full potential of vector units, and only generate vector code for simple loop nests. In this poster, we present the design and implementation of an auto-vectorization framework in the back-end of a dynamic compiler that not only generates optimized vector code but is also well integrated with the instruction scheduler and register allocator. Additionally, we describe a vector instruction selection algorithm based on dynamic programming. Our results obtained in JikesRVM dynamic compilation environment show performance improvement of up to 57.71% on an Intel Xeon processor, compared to non-vectorized execution.

This article describes our approach to teaching graduate students in education and computer science about the design of instructional software. The course is taught by instructional television (ITV) and involves the use of a computer bulletin board system. Students complete software projects using a variety of commercial authoring tools. Student reactions to the nature of the course are described as well as lessons learned.

We present a fiber-based photonic computing concept and system which rely on incoherent data encoding and scalable architecture. Our results suggest projected performance of >1,000,000 Tera operations per second (TOPs) and efficiency of >1000 TOPs/Watt.

Commercial high-level synthesis tools typically produce statically scheduled circuits. Yet, effective C-to-circuit conversion of arbitrary software applications calls for dataflow circuits, as they can handle efficiently variable latencies (e.g., caches), unpredictable memory dependencies, and irregular control flow. Dataflow circuits exhibit an unconventional property: registers (usually referred to as “buffers”) can be placed anywhere in the circuit without changing its semantics, in strong contrast to what happens in traditional datapaths. Yet, although functionally irrelevant, this placement has a significant impact on the circuit’s timing and throughput. In this work, we show how to strategically place buffers into a dataflow circuit to optimize its performance. Our approach extracts a set of choice-free critical loops from arbitrary dataflow circuits and relies on the theory of marked graphs to optimize the buffer placement and sizing. Our performance optimization model supports important high-level synthesis features such as pipelined computational units, units with variable latency and throughput, and if-conversion. We demonstrate the performance benefits of our approach on a set of dataflow circuits obtained from imperative code.

Implementation-aware selection of the custom instruction set for extensible processors

VLSI implementation issues for the 2-D Fermat number transform

Owing to the fundamental nature and a broad range of applications, minimum spanning tree problems have been widely studied in the field of network flows. Most of the previous works reported are sequential or synchronous parallel algorithms which have a polynomial time dependence on the problem size. This paper describes a connectionist architecture based on the binary relation inference network, which can be implemented as a uniform feedback arrangement using conventional maximum and minimum circuits as basic building blocks. The network has shown promise in obtaining the global optimal solution in a timeindependent of the problem size. This is due to the parallel and asynchronous operating nature of the network, and each computational unit can process information asynchronously, or in the continuous-time domain, without the need of precise synchronization with other units of the network. A particular implementation uses commonly available analogue electronic components, and the network is able to give the global optimal solution within the microseconds range. In addition, the voltage-mode approach using analogue VLSI design techniques in implementing the network is presented. The limiting factors of the performance of the analogue and VLSI implementation circuit are discussed.

An experimental approach is chosen to investigate the performance of a fine-grained dataflow architecture for numerically intensive digital signal processing (DSP) applications. The focus is on the behavior of pipelined data-parallel algorithms. However, the granularity of the high-level language programming blocks is not explicitly optimized to balance computation and communication; a natural and logical fine-grained decomposition of problems is used instead. The authors interpret their empirical data by means of parameters such as a number of instructions per generic unit of computation, a density of precedence relations, and a serial fraction. The performance and limitations of fine-grained general-purpose dataflow computing are discussed. >

This paper presents a new approach to the design of integer wavelet filters and an efficient VLSI architecture for low power implementation. Instead of using the lifting scheme, power-of-two wavelet coefficients are derived directly from the roots of the half-band filter. Based on the integer wavelets, we introduce a fast integer Discrete Wavelet Transformation (IntDWT). The proposed integer transform for (9,7) filters requires only 17 integer additions and 15 shift operations. It, however, achieves the same coding efficiency as the floating-point approach. In the proposed VLSI architecture, several optimization techniques are used to remove the redundancy of computational units along the data path. The hardware and software simulation results show that both high performance and low power consumption for DWT chipset can be accomplished at the algorithm architecture level.

In this paper we present new architectures for the design of modulo 2/sup n//spl plusmn/1 adders, which are based on the use of the same design block. Our design block incorporates a parallel-prefix carry computation unit with a carry increment stage. VLSI implementations of the proposed architectures in a static CMOS technology reveal their superiority against all already known architectures when the area * time/sup 2/ product is used as a metric and n > 8.