Can beyond-CMOS devices illuminate dark silicon?

The advent of Dark Silicon as result of the limit on Dennard scaling forced modern processor designs to reduce the chip area that can work on maximum clock frequency. This effect reduced the free gains from Moore's law. This work introduces a less conservative dark silicon estimate based on chip components power density and technological process, so that designers could explore architectural resources to mitigate it. We implemented our dark silicon estimation tool on top of MultiExplorer and evaluated on a set of Intel Pentium and AMD K8/10 multicore processors built on transistor technologies from 90nm down to 32nm. Our contributions are twofold: (1) Our experiments have shown dark silicon estimates up to 8.26% of the chip area compared to a baseline 90nm real processor, we also evaluated clock frequency behavior based on Dennard scaling and obtained up to 15.65% dark silicon on chip area. (2) We designed and showed that a dark silicon aware Design Space Exploration (DSE) strategy can minimize chip dark area while increasing performance at design time. Our results on DSE found dark silicon free multicore platforms while providing 3.6 speedup.

Starting in 2004, the microprocessor industry has shifted to multicore scaling---increasing the number of cores per die each generation---as its principal strategy for continuing performance growth. Many in the research community believe that this exponential core scaling will continue into the hundreds or thousands of cores per chip, auguring a parallelism revolution in hardware or software. However, while transistor count increases continue at traditional Moore's Law rates, the per-transistor speed and energy efficiency improvements have slowed dramatically. Under these conditions, more cores are only possible if the cores are slower, simpler, or less utilized with each additional technology generation. This paper brings together transistor technology, processor core, and application models to understand whether multicore scaling can sustain the historical exponential performance growth in this energy-limited era. As the number of cores increases, power constraints may prevent powering of all cores at their full speed, requiring a fraction of the cores to be powered off at all times. According to our models, the fraction of these chips that is "dark" may be as much as 50% within three process generations. The low utility of this "dark silicon" may prevent both scaling to higher core counts and ultimately the economic viability of continued silicon scaling. Our results show that core count scaling provides much less performance gain than conventional wisdom suggests. Under (highly) optimistic scaling assumptions--- for parallel workloads ---multicore scaling provides a 7.9× (23% per year) over ten years. Under more conservative (realistic) assumptions, multicore scaling provides a total performance gain of 3.7× (14% per year) over ten years, and obviously less when sufficiently parallel workloads are unavailable. Without a breakthrough in process technology or microarchitecture, other directions are needed to continue the historical rate of performance improvement.

Dark silicon is an emerging problem in multi-core processors, where it is not possible to enable all cores simultaneously because of either insufficient parallelism in software applications or because of high-spatial power densities that generate hot-spot constraints. Superlattice-based thermoelectric cooling (TEC) is a promising technology that offers large heat pumping capability and the ability to target hot spots of each core independently. In this paper, we devise novel system-level methods that address the two main sources of dark silicon using superlattice TECs. Our methods leverage the TECs in conjunction with dynamic voltage and frequency scaling and number of threads to maximize the performance of multi-core processor under thermal and power constraints. Using an experimental setup based on a quad-core processor, we provide an evaluation of the trade-offs among performance, temperature and power consumption arising from the use of superlattice-based TECs. Our results demonstrate the potential of this emerging cooling technology in mitigating dark silicon problems and in improving the performance of multi-core processors.

Data with increasing bandwidth requires future general-purpose as well as application specific microprocessors to improve performance endlessly. Transistor scaling, novel transistor structures, novel state-of-art VLSI design techniques and new computer architectures are the key drivers for boosting power and performance of microprocessors. Unfortunately, the processor cooling technique is unable to keep pace with higher density of transistors and high performance. For appropriate trade-offs between performance and limitation of power dissipation, dark silicon has appeared in the current processors. With the number of transistors increasing in future chips, we could envision that next generation processors might be getting darker and darker. This compromise could reduce multiple-core processors' efficiency. In this paper, power dissipation and circuit optimization are discussed in an attempt to mitigate dark silicon for future processors. A power monitor and its algorithm are proposed mainly to explain how to efficiently regulate voltage and power in the future processors with multiple cores.

Moore’s Law scaling has last for almost half century, leading to a tremendous performance/area improvement and cost reduction. Unfortunately, in the past decade, severe challenges have been faced by the CMOS technology as the technology node enters sub-100nm region. To sustain the growing transistor performance and density, many novel device technologies are proposed in the past decade to augment or even replace the conventional Si CMOS technology with Cu interconnect. For the device innovation, ever since the discovery of graphene with excellent physical and electrical properties, much interest has been drawn in the electron-device community and graphene-based FETs have been introduced. Based on the property of the angular dependent transmission probability of electrons observed in GPNJs, an enhanced device structure is presented. More elaborate physical models are also developed to better evaluate the upper limit of delay and power consumptions of GPNJ circuits, including ON resistance, leakage current, contact resistance, and footprint area. For the low-power applications, TFETs show promise in overcoming the power wall faced by thermionic FETs by allowing significant reduction in the supply voltage. The analytical device-level models for TFETs are developed to efficiently evaluate the overall system-level metrics. It is demonstrated that the IV characteristics of a TFET behaves like a Si CMOS switch, but it provides much lower leakage current and ultra-low supply voltage at the cost of low ON current. For the interconnect technology, as the conventional Cu interconnect scales, the resistance per unit length increases dramatically because of 1) the smaller cross-sectional area and 2) the severe size effects at sub-20nm nodes. To alleviate the interconnect challenge, a novel local interconnect structure and hybrid Al-Cu interconnect architecture are proposed and benchmarked against their copper counterpart in terms of energy and energy-delay product. Alternatively, carbon-based interconnects, such as graphene sheets and carbon nanotubes, are also potential candidates because of their outstanding electrical properties. However, graphene is a two-dimensional structure, and increasing the interconnect pitch does not lower the resistance as fast as it does in copper interconnects. Hence, comparing graphene and copper interconnects strongly depends on the interconnect pitch. As a result, system-level analyses are essential to better understand and evaluate the overall benefits of graphene interconnects. Different from existing system-level performance simulators that are based on cycle-accurate simulations, the present methodology employs three hierarchies of compact analytical models on material, device and interconnect, and system levels, respectively. Significant acceleration is achieved in the simulation speed, making multi-parameter optimization feasible. This run-time efficiency is crucial because many novel device concepts have fundamentally different operational principles, and their on/off currents and input capacitances vary drastically in accordance with their design parameters. This methodology allows technologies to evaluate various trade-offs among key design parameters and to maximize the overall chip throughputs or energy efficiencies of processors in a highly efficient way. For the validation of the proposed methodology, simulation results are compared and well matched with eight commercially available Intel multi-core processors across three technology generations from 65nm to 32nm technology nodes. For the GPNJ-based processors, the proposed design methodology is applied to efficiently perform device-, circuit-, and system-level co-optimization. For given power density and die size area budgets, various device-level parameters, including supply voltage, control voltage, gap distance, and oxide thickness, are optimized for a GPNJ core, where 2.1X throughput improvement is observed for a sharp-corner GPNJ core. This advantage is predominantly because of the smaller output resistance, which reduces both device and interconnect delay and saves the power for repeaters. For the TFET based processors, the results indicate that TFETs have excellent performance at the low power density range due to the low supply voltage. The limitations imposed by the interconnects and the large leakage current at high supply voltage restrict the driving current, leading to a lower performance of the TFETs at a high power density. For the emerging interconnect technology, the proposed Al-Cu hybrid interconnect technology is evaluated by replacing short narrow local signal interconnects by Al interconnects. Six interconnect architecture options are analyzed and their optimal aspect ratio and chip frequency are predicted for five technology generations. The optimization and benchmarking results indicate that the potential improvement in chip clock frequency can be between 50 to 100% for the 7nm technology node. A comprehensive optimization/benchmarking is also performed for the multi-layer graphene interconnects. The results show that a single core using graphene interconnects have a higher throughput within the same power density and die size area because of the power saving offered by the low capacitance graphene interconnects.

To satisfy growing computational demands of modern applications, significant enhancements have been introduced in the contemporary processor architectures with the aim to increase their attainable performance, such as increased number of cores, improved capability of memory subsystem and enhancements in the processor pipeline [1]. Therefore, the performance improvements are usually coupled with an increased complexity at the architecture level, which imposes additional challenges when designing, prototyping and optimizing the execution of real-world applications on a given compute platform. Since the application performance depends on multiple factors, e.g., multi-threading, vectorization efficiency and memory accesses, achieving the most efficient execution is not a trivial task, especially when aiming at fully exploiting the capabilities of modern multi-core processors.

Multimedia designs are among the most complex leading-edge integrated circuits that are made today. In this session, CAD architects for three industry-leading multimedia products will discuss new challenges that arise across the CAD flow - from system and architecture level through physical implementation - as we approach billion-transistor devices.The first talk will focus on system-level specification and codesign of embedded software for a multimedia processor. The second talk will discuss new time and space challenges for verification methodologies, which must be met to address the requirements of graphics processor time-to-market pressures. The third talk will discuss CAD challenges unique to a pioneering high-speed, multi-core processing engine for gaming and entertainment platforms.

Design methodologies for Hitachi's RISC microprocessors and microcontrollers are discussed. One of the processors is a high-end PA-RISCTM. The others, the PA/50 and the SH series microcontroller, are low power and low cost processors. Low cost processors require small chip sizeand short design time. To shorten the architecture level design time, we have developed a RT-level behavior simulation tool based on C language. And to reduce the total design time, we use a gate-level synthesis program from the behavior model description. This approach resulted in the low power 42 MIPS/W PA-RISCTM processor (the PA/50, which run at a 33 MHz clock rate) being completed within 15months. Another approach to minimizing chip size while maintaining high performance is to reduce the design turnaround time by using microcode instead of direct wired logic design. We wrote 480-word microcodes equivalent to a 5.8K transistor logic. After assigning the control stages for the microcode fields, we used an in-house logic synthesis and optimized for performance and chip size. The CPU core of the SH series microcontroller occupies only 8 mm2 including CPU core and multiplier circuit. The processor reaches 16 MIPS at 20 MHz. It took 17 man-months to realize a minimum 8 mm2 chip. The total control logic consists of 27 thousand transistors.

The RISC-V instruction set architecture (ISA) is gaining wide adoption in domains such as IoT, embedded systems, and academic research due to its open-source, modular, and flexible design. A CPU core that is both efficient and easily verified is a basic prerequisite for such applications. In this work, we present the design and implementation of a Verilog HDL-based 32-bit single-cycle RISC-V processor that supports the RV32I instruction set. The processor integrates an Arithmetic Logic Unit (ALU), Register File, Control Unit, and Memory into a structured and modular datapath. Simulation and functional verification were performed using Eda Playground, where the correctness of instruction execution was confirmed through waveform analysis. The result of ALU operations is governed by the opcode and operands, where arithmetic operations (e.g., addition) perform A+B, logical operations (e.g., AND) perform <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{A} \wedge \mathrm{B}$</tex>, and memory instructions handle load/store between registers and memory. Status flags such as zero, carry, negative, and overflow are updated accordingly. The proposed design demonstrates improved efficiency through optimized control logic and reduced critical path delay, ensuring faster instruction execution in single-cycle operation. This processor serves as a foundational model for future enhancements such as pipelined or low-power architectures aimed at increasing performance and energy efficiency. The proposed modular top-level architectural synthesis approach improves scalability, verification simplicity, and enables seamless extension toward pipelined RISC-V architectures.

The emerging technology of the System-on-Chip (SoC) is presenting new challenges at both the hardware and software stages of the design process. At present, system software engineers, e.g. high-level programming language (e.g. C/C++) compiler writers for processor cores, are working at the abstraction level of instruction set architecture (ISA) and its compiler optimization. On the other hand, the hardware engineers for the processor cores and other devices are working at a lower level abstraction level, e.g. RTL level, and using hardware description languages (e.g. VHDL, Verilog) and associated silicon compiler tools. Problems of communication gaps between the two world continue to exist due to the different abstraction levels, and the use of different design languages, incompatible tools and fragmented design flow, etc.In this talk, we discuss such gaps with examples illustrating the limits of optimization that can be performed from the hardware/software alone. With the demand of aggressive exploitation of instruction-level parallelism with high-performance uniprocessor core as well as the need of multiprocessor cores - such gaps must be bridged. Such optimization includes instruction scheduling; register allocation, loop scheduling, locality optimization, etc. Such gaps also affect software debugging (including performance debugging) as well as hardware verification.We briefly outline solution challenges and opportunities in this direction.

The nonstop scaling of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) is considered a driving force in semiconductor technology, allowing higher integration densities, enhanced performance, and reduced power consumption. However, fundamental challenges arise as device dimensions shrink to the nanoscale, such as short-channel effects, threshold voltage variation, leakage currents, and gate oxide tunneling. This study critically surveys these scaling limitations and shows potential solutions, such as high-k gate dielectrics, metal gate integration, and novel device architectures. Other transistor designs, including FinFETS, Gate-All-Around (GAA) transistors, and emerging beyond-CMOS devices, are assessed for their potential to extend Moore's Law. This study also addresses advancements in materials, including two-dimensional (2D) semiconductors and carbon-based nanostructures, that offer promising substitutes to conventional silicon technology. Regardless of these innovations, significant obstacles remain in achieving fabrication, reliability, and cost-effectiveness at sub-5nm nodes. This review paper provides insights into current progress and future guide for nanoscale MOSFET development, comprehensively assessing the challenges and opportunities in next-generation transistor technology. The findings aim to guide researchers and industry professionals toward sustainable semiconductor scaling approaches.

The problem of identifying intersections between two sets of d -dimensional axis-parallel rectangles appears frequently in the context of agent-based simulation studies. For this reason, the High Level Architecture (HLA) specification—a standard framework for interoperability among simulators—includes a Data Distribution Management (DDM) service whose responsibility is to report all intersections between a set of subscription and update regions. The algorithms at the core of the DDM service are CPU-intensive, and could greatly benefit from the large computing power of modern multi-core processors. In this article, we propose two parallel solutions to the DDM problem that can operate effectively on shared-memory multiprocessors. The first solution is based on a data structure (the interval tree) that allows concurrent computation of intersections between subscription and update regions. The second solution is based on a novel parallel extension of the Sort Based Matching algorithm, whose sequential version is considered among the most efficient solutions to the DDM problem. Extensive experimental evaluation of the proposed algorithms confirm their effectiveness on taking advantage of multiple execution units in a shared-memory architecture.

Recent CPU widely utilizes cache memory or cache to decrease access speed gap between the CPU and the main memory. However, the cache occupies a large part of the processor's energy consumption. Furthermore, due to the characteristics of SRAMs, it is hard to reduce the supply voltage of the cache compared to that of the CPU core. Thus, dynamic voltage and frequency scaling (DVFS) which is widely used to reduce the processor's energy consumption does not reduce cache energy significantly. To confront this problem, we investigated a method which applies different power and speed design caches and switching them in proportion to the DVFS activity. Our proposal modifies the L1 cache hierarchy to L1 low-speed cache and L1 high-speed cache and selects them or access in sequential in proportion to DVFS activity to reduce cache energy demand. We confirmed that the proposal has a potential for further reduction of cache energy consumption with both cache design simulation and processor architecture level simulation.