On the Dark Silicon Automatic Evaluation on Multicore Processors

Starting in 2004, the microprocessor industry has shifted to multicore scaling---increasing the number of cores per die each generation---as its principal strategy for continuing performance growth. Many in the research community believe that this exponential core scaling will continue into the hundreds or thousands of cores per chip, auguring a parallelism revolution in hardware or software. However, while transistor count increases continue at traditional Moore's Law rates, the per-transistor speed and energy efficiency improvements have slowed dramatically. Under these conditions, more cores are only possible if the cores are slower, simpler, or less utilized with each additional technology generation. This paper brings together transistor technology, processor core, and application models to understand whether multicore scaling can sustain the historical exponential performance growth in this energy-limited era. As the number of cores increases, power constraints may prevent powering of all cores at their full speed, requiring a fraction of the cores to be powered off at all times. According to our models, the fraction of these chips that is "dark" may be as much as 50% within three process generations. The low utility of this "dark silicon" may prevent both scaling to higher core counts and ultimately the economic viability of continued silicon scaling. Our results show that core count scaling provides much less performance gain than conventional wisdom suggests. Under (highly) optimistic scaling assumptions--- for parallel workloads ---multicore scaling provides a 7.9× (23% per year) over ten years. Under more conservative (realistic) assumptions, multicore scaling provides a total performance gain of 3.7× (14% per year) over ten years, and obviously less when sufficiently parallel workloads are unavailable. Without a breakthrough in process technology or microarchitecture, other directions are needed to continue the historical rate of performance improvement.

Nonlinear digital filters play an important role in digital signal processing applications. In this brief, a novel architecture is proposed for the hardware implementation of fixed and runtime variable window length one-dimensional median filters. In the proposed architecture, the maximum working clock frequency is almost independent of the median filter window length, whereas the hardware complexity is proportional to the number of samples in the window. This feature enables the construction of filters with relatively large window lengths with negligible reduction in the maximum clock frequency, whereas in previous architectures, the maximum clock frequency significantly drops as the window length is increased. The benchmark results show the efficiency of the proposed architecture in comparison with state-of-the-art techniques.

There is one, and only one way, consistent with fundamental physics, that the\nefficiency of general digital computation can continue increasing indefinitely,\nand that is to apply the principles of reversible computing. We need to begin\nintensive development work on this technology soon if we want to maintain\nadvances in computing and the attendant economic growth.\n NOTE: This paper is an extended author's preprint of the feature article\ntitled "Throwing Computing Into Reverse" (print) or "The Future of Computing\nDepends on Making it Reversible" (online), published by IEEE Spectrum in\nAug.-Sep. 2017. This preprint is based on the original draft manuscript that\nthe author submitted to Spectrum, prior to IEEE edits and feedback from\nexternal readers.\n

Heterogeneous multiprocessor platforms are becoming widespread in the embedded system domain, mainly for the opportunity to improve timing performance and to minimize energy/power consumption and costs. Therefore, when using such platforms, it is important to adopt a Design Space Exploration (DSE) strategy that considers compromises among different objectives. Existing DSE approaches are generally based on evolutionary algorithms to solve Multi-Objective Optimization Problems (MOOPs) by minimizing a linear combination of weighted cost functions (i.e., Weighted Sum Method, WSM). In this way, the main issues are related to reduce timing execution while trying to improve the evolutionary algorithm performance, introducing strategies that attempt to bring better solutions. Code parallelization is one of the most used approaches in this field, but no standard methods have been released since different aspects could affect the performance. This approach leads to exploit parallel and distributed processing elements in order to implement evolutionary algorithms. In the latter case, if we consider genetic algorithms, it is possible to talk about Parallel Genetic Algorithms (PGA). Considering this context, this paper focuses on DSE for heterogeneous multi-processor embedded systems and introduces an improvement that reduces execution time using parallel programming languages (i.e., OpenMP) inside the main genetic algorithm approach, while trying to lead to better partitioning solutions. The descriptions of the adopted DSE activities and the OpenMP implementation, validated by means of a case study, represent the core of the paper.

This introduction to the special issue discussesdark silicon--chip area that must remain unclocked or underclocked--and highlights the five articles in the issue.

Moore's law is related to the scaling law founded on the work of Dennard, known as Dennard scaling. Dennard scaling is specifically related to power scaling in complementary metal-oxide semiconductor transistors. One of the factors that drive Moore's law is the scalability of semiconductor feature sizes. Another driving force for Moore's law is derived from economics the financial viability of shrinking the size of the transistor gate length or introducing new materials. The critical economic aspect contained in Moore's law is that, as technology evolves and advances to new heights, a larger amount of functionality can be offered at the same cost associated with a particular component count and cost. Apart from the enabling technologies on which researchers, manufacturers and scientists rely to ensure that Moore's law continues, several future-generation technologies are also in development stages. As technologies advance in complexity, the manufacturing processes involved also increase in complexity, which has a direct impact on manufacturing costs.

The widening gap between the fast-increasing transistor budget but slow-growing power delivery and system cooling capability calls for novel architectural solutions to boost energy efficiency. Leveraging the fact of surging “dark silicon” area, we propose a hybrid scheme to use both on-chip and off-chip voltage regulators, called “AgileRegulator”, for a multicore system to explore both coarse-grain and fine-grain power phases. We present two complementary algorithms: Sensitivity-Aware Application Scheduling (SAAS) and Responsiveness-Aware Application Scheduling (RAAS) to maximally achieve the energy saving potential of the hybrid regulator scheme. Experimental results show that the hybrid scheme achieves performance-energy efficiency close to per-core DVFS, without imposing much design cost. Meanwhile, the silicon overhead of this scheme is well contained into the “dark silicon”. Unlike other application specific schemes based on accelerators, the proposed scheme itself is a simple and universal solution for chip area and energy trade-offs.

The "new Dark Silicon" model benchmarks transistor technologies at the architectural level for multi-core processors.

In this paper, we propose a high throughput and data reuse architecture for de-blocking filter in H.264/AVC. There are two SRAMs exploited in the design. One is 144times32 bits single-port SRAM, and the other is 16times32 bits two-port SRAM. We use the group-of-pixel access method to store the pixels in SRAMs instead of the column-of-pixel or row-of-pixel approach. In the algorithm level, we modify the filtering order in the de-blocking filter without violating the H.264/AVC standard. Therefore, we efficiently use the data reuse skill to reduce the access frequency of SRAMs. We implement this architecture with UMC 0.18 mum cell library, and the maximum clock frequency we can achieve is 100 MHz. The simulation results show that the total number of logic gate counts is 16.6k. When the clock frequency equals 100 MHz, it can process 14619 macroblocks in 1/30 second. In other words, we achieve 4XGA (2048times1536) @30 frames/sec when we set the clock frequency to 85 MHz

A fully integrated 2-D linear filter including a line buffer for a 7*7 kernel is presented. To run the filter in real time at video clock frequencies, an array of pipelined carry-save adders was used as a very fast arithmetic unit. The filter chip contains 292451 transistors on a silicon area of 135 mm/sup 2/. The maximum clock frequency under worst-case conditions for technology and temperature was simulated to be 20 MHz. The main blocks are designed as independent parameterizable modules. The line buffer and the arithmetic unit are available as macros in a standard cell library for semicustom design. With these macros a semicustom chip for image enhancement in a X-ray system was produced. This chip works with a system frequency of 13 MHz. The line buffer module is used in another full-custom image processing chip-a two-dimensional rank order filter with a kernel size of also 7*7. This chip contains more than 300000 transistors on a silicon area of 103 mm/sup 2/. In this case the module containing the 1-D FIR (finite impulse response) filters is replaced by additional pixel delays and a sorter module. Simulations have shown that the chip could work with clock frequencies up to 20 MHz.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Transforms like Discrete Fourier Transform (DFT) are a major block in communication systems such as OFDM, etc. This paper reports architecture of a DFT core using new distributed arithmetic (NEDA) algorithm. The advantage of the proposed architecture is that the entire transform can be implemented using adder/subtractors and shifters only, thus minimising the hardware requirement compared to other architectures. The proposed design is implemented for 16 - bit data path (12 - bit for comparison) considering both integer representation as well as fixed point representation, thus increasing the scope of usage. The proposed design is mapped on to Xilinx XC2VP30-7FF896 FPGA, which is fabricated using 130 nm process technology. The hardware utilization of the proposed design on the mapped FPGA is 295 slices, 478 4-input LUTs and 304 slice flip flops. The maximum on board frequency of operation of the proposed design is 79.339 MHz. The proposed design has 72.27% improvement in area, 10.31% improvement in both maximum clock frequency and throughput when compared to other designs.

We give an efficient algorithm for solving the following scheduling problem to optimality: Assign n jobs to m processors such that they all meet a common deadline T and energy consumption is minimized by appropriately controlling the clock frequencies of the processors. Jobs are malleable, i.e., their amount of parallelism can be flexibly adapted. In contrast to previous work on energy efficient scheduling we allow more realistic energy consumption functions including a minimum and maximum clock frequency and a linear term in energy consumption. We need certain assumptions on the speedup function of the jobs that we show to apply for a large class of practically occurring functions.KeywordsSchedule ProblemEnergy FunctionEnergy UsageFrequency ScalingBend PointThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Due to the downscaling of transistor feature sizes, nowadays integrated circuits are more vulnerable to various effects that can cause faults during operation. Appropriate mechanisms for handling these faults in the field are required to meet certain dependability demands nonetheless. At the same time, the overhead in chip area and power consumption that is caused by such fault tolerance techniques needs to be reasonable. This calls for a dependability aware design space exploration which carefully evaluates the costs and benefits of various fault tolerant implementations of the system. This paper first introduces a tool that supports this design space exploration for hardware redundancy based fault tolerance. Among other features, it offers very fast overhead estimations for the supported set of fault tolerance techniques. The paper describes in detail how the estimations of the power overhead are performed. The accuracy of these estimations is evaluated by comparison with power analysis results obtained by a commercial EDA tool.

Designing secure systems is a complex task, particularly for designers who are no security experts. Cyber security plays a key role in embedded systems, especially for the domain of the Internet of Things (IoT). IoT systems of this kind are becoming increasingly important in daily life as they simplify various tasks. They are usually small, either embedded into bigger systems or battery driven, and perform monitoring or one shot tasks. Thus, they are subject to manifold constraints in terms of performance, power consumption, chip area, etc. As they are continuously connected to the internet and utilize our private data to perform their tasks, they are interesting for potential attackers. Cyber security thus plays an important role for the design of an IoT system. As the usage of security measures usually increases both computation time, as well as power consumption, a conflict between these constraints must be solved. For the designers of such systems, balancing these constraints constitutes a highly complex task. In this paper we propose a novel approach for considering possible security attacks on embedded systems, simplifying the consideration of security requirements immediately at the start of the design process. We introduce a security aware design space exploration framework which based on an architectural, behavioral and security attack description, finds the optimal design for IoT systems. We also demonstrate the feasibility and the benefits of our framework based on a door access system use case.

3D Integration emerges as an attractive option to sustain Moore's law as well as to enable More-than-Moore. Design and test techniques and methodologies for 3D designs are imperative to realise 3D integration; novel architectures and design space exploration at the architectural level are also essential to leverage 3D integration technologies for performance gain. This special issue of IET Computers & Digital Techniques covers various perspectives of designing future 3D ICs. A call for papers for this special issue was announced in May 2009. All submissions went through the regular review process of JETC. After review and appropriate revisions, seven papers on diverse topics related to 3D integration were accepted for this special issue.