Throwing computing into reverse

The advent of Dark Silicon as result of the limit on Dennard scaling forced modern processor designs to reduce the chip area that can work on maximum clock frequency. This effect reduced the free gains from Moore's law. This work introduces a less conservative dark silicon estimate based on chip components power density and technological process, so that designers could explore architectural resources to mitigate it. We implemented our dark silicon estimation tool on top of MultiExplorer and evaluated on a set of Intel Pentium and AMD K8/10 multicore processors built on transistor technologies from 90nm down to 32nm. Our contributions are twofold: (1) Our experiments have shown dark silicon estimates up to 8.26% of the chip area compared to a baseline 90nm real processor, we also evaluated clock frequency behavior based on Dennard scaling and obtained up to 15.65% dark silicon on chip area. (2) We designed and showed that a dark silicon aware Design Space Exploration (DSE) strategy can minimize chip dark area while increasing performance at design time. Our results on DSE found dark silicon free multicore platforms while providing 3.6 speedup.

Starting in 2004, the microprocessor industry has shifted to multicore scaling---increasing the number of cores per die each generation---as its principal strategy for continuing performance growth. Many in the research community believe that this exponential core scaling will continue into the hundreds or thousands of cores per chip, auguring a parallelism revolution in hardware or software. However, while transistor count increases continue at traditional Moore's Law rates, the per-transistor speed and energy efficiency improvements have slowed dramatically. Under these conditions, more cores are only possible if the cores are slower, simpler, or less utilized with each additional technology generation. This paper brings together transistor technology, processor core, and application models to understand whether multicore scaling can sustain the historical exponential performance growth in this energy-limited era. As the number of cores increases, power constraints may prevent powering of all cores at their full speed, requiring a fraction of the cores to be powered off at all times. According to our models, the fraction of these chips that is "dark" may be as much as 50% within three process generations. The low utility of this "dark silicon" may prevent both scaling to higher core counts and ultimately the economic viability of continued silicon scaling. Our results show that core count scaling provides much less performance gain than conventional wisdom suggests. Under (highly) optimistic scaling assumptions--- for parallel workloads ---multicore scaling provides a 7.9× (23% per year) over ten years. Under more conservative (realistic) assumptions, multicore scaling provides a total performance gain of 3.7× (14% per year) over ten years, and obviously less when sufficiently parallel workloads are unavailable. Without a breakthrough in process technology or microarchitecture, other directions are needed to continue the historical rate of performance improvement.

With Moore's law supplying billions of transistors on-chip, embedded systems are undergoing a transition from single-core to multi-core to exploit this high transistor density for high performance. However, there exists a plethora of multi-core architectures and the suitability of these multi-core architectures for different embedded domains (e.g., distributed, real-time, reliability-constrained) requires investigation. Despite the diversity of embedded domains, one of the critical applications in many embedded domains (especially distributed embedded domains) is information fusion. Furthermore, many other applications consist of various kernels, such as Gaussian elimination (used in network coding), that dominate the execution time. In this paper, we evaluate two embedded systems multi-core architectural paradigms: symmetric multiprocessors (SMPs) and tiled multi-core architectures (TMAs). We base our evaluation on a parallelized information fusion application and benchmarks that are used as building blocks in applications for SMPs and TMAs. We compare and analyze the performance of an Intel-based SMP and Tilera's TILEPro64 TMA based on our parallelized benchmarks for the following performance metrics: runtime, speedup, efficiency, cost, scalability, and performance per watt. Results reveal that TMAs are more suitable for applications requiring integer manipulation of data with little communication between the parallelized tasks (e.g., information fusion) whereas SMPs are more suitable for applications with floating point computations and a large amount of communication between processor cores.

Digital atomic scale fabrication an inverse Moore's Law – A path to atomically precise manufacturing

: Moore's Law: The number of transistors that can be placed on a micro-circuit doubles every 18-24 months, resulting in a rapid turnover in generations of microcircuits. There are almost as many opinions about how long Moore's Law will be applicable as there have been technological advances since the Law was first annunciated in 1965. The majority of industry experts however believe that the physical limits of silicon based advancements will be reached by the end of the decade. Microelectronics obsolescence will remain a challenge as industry and academia alike are hard at work on marketing post-silicon applications. New atomic compounds such as gallenium arsenide and ferritin may replace silicon substrates within integrated circuits while entirely new technologies like quantum computing may transform the entire industry. The point is that while Moore's Law will end relatively soon innovation will not--and DoD program managers (PM) will still have to manage obsolescence.

The widening gap between the fast-increasing transistor budget but slow-growing power delivery and system cooling capability calls for novel architectural solutions to boost energy efficiency. Leveraging the fact of surging “dark silicon” area, we propose a hybrid scheme to use both on-chip and off-chip voltage regulators, called “AgileRegulator”, for a multicore system to explore both coarse-grain and fine-grain power phases. We present two complementary algorithms: Sensitivity-Aware Application Scheduling (SAAS) and Responsiveness-Aware Application Scheduling (RAAS) to maximally achieve the energy saving potential of the hybrid regulator scheme. Experimental results show that the hybrid scheme achieves performance-energy efficiency close to per-core DVFS, without imposing much design cost. Meanwhile, the silicon overhead of this scheme is well contained into the “dark silicon”. Unlike other application specific schemes based on accelerators, the proposed scheme itself is a simple and universal solution for chip area and energy trade-offs.

Summary form only given: Modern FPGA platforms have capabilities that are well suited to assume a more central role in the implementation of complex embedded processing systems. The aggressive adoption of Moore's Law and the application of emerging 3D stacked silicon interconnect technology have resulted in the growth of FPGA capacity that outperforms Moore's Law. In particular, FPGAs are well placed to be at the heart of complex signal processing, packet processing and high performance computing applications because of their high computational efficiency matched by high bandwidth concurrent memory access and rich on-chip interconnectivity, all of this combined with complete programmability and best in industry power efficiency. The key to unleashing the full horsepower of FPGA platforms to the system designer is, first of all, a hardware platform that allows tight integration between the processor, the programmable logic and the memory. Second, the hardware architecture has to be supported by a programming flow that abstracts the hardware implementation details and provides seamless and efficient mapping of system functions on multiple processor cores and programmable hardware functions. Finally, a programmable infrastructure has to be provided that targets specific requirements for packet processing or signal processing or high performance computing.

The acceleration of new developments in semiconductor design and manufacturing technology in keeping up with Moore's Law has introduced significant new challenges for device designers as well as manufacturing organizations. Short channel effects, multi-level interconnect cross talk problems, and new materials such as low K dielectric, copper, and silicon on insulator have made modeling and simulation of semiconductor devices and processes extremely difficult. Many times this results in failure to meet performance targets in first silicon introduction. The high cost of mask sets, together with the opportunity costs related to time-to-market, drives the need for shorter and fewer redesign cycles, making effective transistor level design debug a necessity. To make things even more difficult, the transition to flip chip packaging and multiple interconnect metal layers makes backside probing the only effective way to perform node level analysis. This paper describes these new challenges in detail, and the use of photon probing technology as an effective way to address them. The use of a time resolved photon emission microscope allows measuring performance at the critical node level. This is done by collecting the photons, emitted by carriers that are accelerated in the pinch off region during CMOS transistor switching. This enables optimization of device speed paths, and resolution of problems such as race conditions and contentions, encountered during design debug and failure analysis cycles.

Moore's Law has set great expectations that the performance/price ratio of commercially available semiconductor devices will continue to improve exponentially at least until the end of the next decade. Although the physics of nanoscale silicon transistors alone would allow these expectations to be met, the physics of the metal wires that connect these transistors will soon place stringent limits on the performance of integrated circuits. We will describe a Si-compatible global interconnect architecture - based on chip-scale optical wavelength division multiplexing - that could precipitate an "optical Moore's Law" and allow exponential performance gains until the transistors themselves become the bottleneck. Based on similar fabrication techniques and technologies, we will also present an approach to an optically-coupled quantum information processor for computation beyond Moore's Law, encouraging the development of practical applications of quantum information technology for commercial utilization.

Multipliers have been key and critical components for most application-specific and general-purpose computer architectures. However, these architectures have been transitioning towards multiple cores that can process large amounts of data through parallel approaches to computation. Unfortunately, traditional arithmetic functional units that worked well for single-core architectures have the side-effect of incurring large amounts of area and power. Consequently, multi-core computer architecture need new ways of thinking about increased throughput to handle large amounts of data. This paper presents a recursive high radix divide unit that is modified to handle both multiplication and division targeted at multi-core architectures. Results are obtained with a 65nm technology and show a significant decrease in area and power while still maintaining a low total latency by utilizing high radix encoding within the functional unit. More importantly, because the datapath unit requires complex recoding, it does not increase its latency as the bit size increases. Therefore, these units can occupy low amounts of area while still maintaining high amounts of processing power.

To satisfy the increasing demands in computing throughput, new processor designs are frequently expanding their support for parallel operations, including multiple memory controllers, caches, and various I/O devices, but especially multiple processor cores. For developers of real-time embedded systems with security and/or safety-critical computing requirements, the advent of processors that include multiple cores has created a fundamental problem: how to satisfy certification considerations so that safety and/or security related applications can execute on real-time multi-core based partitioning enforcing systems. This paper examines some architectural considerations that may be taken into account as part of safety and/or security certification of a partitioning operating system that supports the scheduling of multiple applications on a multi-core processor. In particular, it covers a set of considerations and challenges associated with using multiple cores as part of an architecture that supports simultaneous execution of applications on different cores and as part of an architecture that supports simultaneous use of multiple cores cooperatively within an application. This includes high-level considerations of safety and security topics such as, shared resource management, caching, covert channels, and fault management. In addition, it examines the use of synchronous time-scheduling controls as a means to resolve some of the safety and security related issues. This paper, by examining and detailing some of the high-level safety and security considerations associated with multi-core processor architectures, is intended to demonstrate the benefits of utilizing synchronous time-scheduling controls across the entire multi-core processor as a means to resolve some of the issues. Developers of real-time embedded systems can maximize the benefit of multi-core processors through understanding the types of architectural features that may be necessary to resolve specific safety and/or security issues.

In the last decade, we have seen how Moore's law has lost its validity because it has reached the physical limit of miniaturization of components and the problem of thermal dissipation increasing with the chip’s clock frequency. For this reason, multi-core architectures were born, and quantum computing is being looked at as a possible solution for more computing power. The aim of this article is to demonstrate the possibility to realize computer architectures using multi-value logic. The objective is reached when we are able to translate any MVL function into the corresponding MVL circuit. The method proposed is completely independent of the basis adopted in the MVL domain and the physical quantity used to represent or transfer the domain values. Thus, this approach provides a new theoretical and practical context for applying new technologies or polymorphic materials, which can represent multiple values. In order to give concreteness to the analyzed theoretical aspects, we will represent a case study based on a classical combinational circuit, the summing circuit using LTspice® XVII (© Analog Device Corporation) as simulation environment has been carried out. The results show that it is possible to build MVL combinatorial circuits, although there are limitations because the proposed solution is just a proof of concept. The method can also be successfully applied to sequential MVL circuits, which are not the subject of the present article.

Since the invention of the transistor, clock frequency increase was the primary method of improving computing performance. As the reach of Moore's law came to an end, however, technology driven performance gains became increasingly harder to achieve, and the research community was forced to come up with innovative system architectures. Today increasing parallelism is the primary method of improving performance: single processors are being replaced by multiprocessor systems and multicore architectures. The challenge faced by computer architects is to increase performance while limited by cost and power consumption. The appearance of cheap and fast interconnection networks has promoted designs based on distributed memory computing. Most modern massively parallel computers, as reflected by the Top 500 list, are clusters of workstations using commodity processors connected by high speed interconnects. Today's massively parallel systems consist of hundreds of thousands of processors. Software technology to program these large systems is still in its infancy. Optimizing communication has become a key to overall system performance. To cope with the increasing burden of communication, the following methods have been explored: (i) Scalability in the messaging system: The messaging system itself needs to scale up to the 100K processor range. (ii) Scalable algorithms reducing communication: As the machine grows in size the amount of communication also increases, and the resulting overhead negatively impacts performance. New programming models and algorithms allow programmers to better exploit locality and reduce communication. (iii) Speed up communication: reducing and hiding communication latency, and improving bandwidth. Following the three items described above, this thesis contributes to the improvement of the communication system (i) by proposing a scalable memory management of the communication system, that guarantees the correct reception of data and control-data, (ii) by proposing a language extension that allows programmers to better exploit data locality to reduce inter-node communication, and (iii) by presenting and evaluating a cache of remote addresses that aims to reduce control-data and exploit the RDMA native network capabilities, resulting in latency reduction and better overlap of communication and computation. Our contributions are analyzed in two different parallel programming models: Message Passing Interface (MPI) and Unified Parallel C (UPC). Many different programing models exist today, and the programmer usually needs to choose one or another depending on the problem and the machine architecture. MPI has been chosen because it is the de facto standard for parallel programming in distributed memory machines. UPC was considered because it constitutes a promising easy-to-use approach to parallelism. Since parallelism is everywhere, programmability is becoming important and languages such as UPC are gaining attention as a potential future of high performance computing. Concerning the communication system, the languages chosen are relevant because, while MPI offers two-sided communication, UPC relays on a one-sided communication model. This difference potentially influences the communication system requirements of the language. These requirements as well as our contributions are analyzed and discussed for both programming models and we state whether they apply to both programming models.

Data with increasing bandwidth requires future general-purpose as well as application specific microprocessors to improve performance endlessly. Transistor scaling, novel transistor structures, novel state-of-art VLSI design techniques and new computer architectures are the key drivers for boosting power and performance of microprocessors. Unfortunately, the processor cooling technique is unable to keep pace with higher density of transistors and high performance. For appropriate trade-offs between performance and limitation of power dissipation, dark silicon has appeared in the current processors. With the number of transistors increasing in future chips, we could envision that next generation processors might be getting darker and darker. This compromise could reduce multiple-core processors' efficiency. In this paper, power dissipation and circuit optimization are discussed in an attempt to mitigate dark silicon for future processors. A power monitor and its algorithm are proposed mainly to explain how to efficiently regulate voltage and power in the future processors with multiple cores.

With the development of high‐performance computing, it is possible to solve large‐scale computing problems. However, the irregularity and access characteristics of computing problems bring challenges to the realisation and performance optimisation. Improving the performance of a single core makes it challenging to maintain Moore's law, and multi‐core processors emerge. A chip brings together multiple universal processor cores of equal status and has the same structure supported by an isomorphic multi‐core processor. In high‐performance computing, the granularity of computing tasks leads to the complexity of scheduling strategies. Satisfying high system performance, load balancing and processor fault tolerance at a minimum cost is the key to task scheduling in the high‐performance field, especially in specific multi‐core hardware architecture. In this study, global real‐time task scheduling is implemented in a high‐performance multi‐core system. The system adopts the hybrid scheduling among clusters and the intelligent fitting within clusters to implement the global real‐time task scheduling strategy. In the cluster scheduling policy, tasks are allowed to preempt the core with low priority, and the priority of tasks that access memory is dynamically improved, higher than that of all the tasks without memory access. An intelligent fitting method is also proposed. When the data read by the task is in the cache and the cache access ability value of the task is within a reasonable threshold, the priority of the task is promoted to the highest priority, preempting the core without the access memory task. The results show that the intelligently fitting global scheduling strategy for multi‐core systems has better performance in the nuclear utilisation rate and task schedulability.