Parallelized benchmark-driven performance evaluation of SMPs and tiled multi-core architectures for embedded systems

Technological advancements in the silicon industry, as predicted by Moore's law, have enabled integration of billions of transistors on a single chip. To exploit this high transistor density for high performance, embedded systems are undergoing a transition from single-core to multi-core. Although a majority of embedded wireless sensor networks (EWSNs) consist of single-core embedded sensor nodes, multi-core embedded sensor nodes are envisioned to burgeon in selected application domains that require complex in-network processing of the sensed data. In this paper, we propose an architecture for heterogeneous hierarchical multi-core embedded wireless sensor networks (MCEWSNs) as well as an architecture for multi-core embedded sensor nodes used in MCEWSNs. We elaborate several compute-intensive tasks performed by sensor networks and application domains that would especially benefit from multi-core embedded sensor nodes. This paper also investigates the feasibility of two multi-core architectural paradigms-symmetric multiprocessors (SMPs) and tiled many-core architectures (TMAs)-for MCEWSNs. We compare and analyze the performance of an SMP (an Intel-based SMP) and a TMA (Tilera's TILEPro64) based on a parallelized information fusion application for various performance metrics (e.g., runtime, speedup, efficiency, cost, and performance per watt). Results reveal that TMAs exploit data locality effectively and are more suitable for MCEWSN applications that require integer manipulation of sensor data, such as information fusion, and have little or no communication between the parallelized tasks. To demonstrate the practical relevance of MCEWSNs, this paper also discusses several state-of-the-art multi-core embedded sensor node prototypes developed in academia and industry. We further discuss research challenges and future research directions for MCEWSNs.

Schedulers for symmetric multiprocessing (SMP) machines use sophisticated algorithms to schedule processes onto the available processor cores. Hardware-dependent code and the use of locks to protect shared data structures from simultaneous access lead to poor portability, the difficulty to prove correctness, and a myriad of problems associated with locking such as limiting the available parallelism, deadlocks, starvation, interrupt handling, and so on. In this work we explore what can be achieved in terms of portability and simplicity in an SMP scheduler that achieves similar performance to state-of-the-art schedulers. By strictly limiting ourselves to only lock-free data structures in the scheduler, the problems associated with locking vanish altogether. We show that by employing implicit cooperative scheduling, additional guarantees can be made that allow novel and very efficient implementations of memory-efficient unbounded lock-free queues. Cooperative multitasking has the additional benefit that it provides an extensive hardware independence. It even allows the scheduler to be used as a runtime library for applications running on top of standard operating systems. In a comparison against Windows Server and Linux running on up to 64 cores we analyze the performance of the lock-free scheduler and show that it matches or even outperforms the performance of these two state-of-the-art schedulers in a variety of benchmarks.

Wireless internet access technologies have significant market potential, especially the WiMAX protocol which can offer data rate of tens of Mbps. A significant demand for embedded high performance WiMAX solutions is forcing designers to seek single-chip multiprocessor or multi-core systems that offer competitive advantages in terms of all performance metrics, such as speed, power and area. Through the provision of a degree of flexibility similar to that of a DSP and performance and power consumption advantages approaching that of an ASIC, emerging dynamically reconfigurable processors are proving to be strong candidates for future high performance multi-core processor systems. This paper presents several new single-chip multi-core architectures, based on newly emerging dynamically reconfigurable processor cores, for the WiMAX physical layer. A simulation platform is proposed in order to explore and implement various multi-core solutions combining different memory architectures and task partitioning schemes. The paper describes the architectures, the simulation environment, several task partitioning methods and demonstrates that up to 4.9x speedup can be achieved by employing five dynamically reconfigurable processor cores each having individual local memory units.

To meet the needs of AI design in analog IC design automation and especially in big data applications, the application of sensitive and precise Graph Neural Network (GNN) recognition will become increasingly necessary. This sensitive GNN recognition is needed to accommodate the highly stringent trade-offs on analog IC design requirements, combined with the increasingly large learning data requirements. Furthermore, more precise GNN recognition will be a fundamental requirement for a more sensitive system to accommodate noise in floating point (FP) calculations, namely inaccuracies and imprecision in IEEE 754 FP calculations. In this study, by refining a previously proposed method that uses the output vector representation (OVR) of the untrained Graph Neural Network (GNN), and by exploiting the numerical reproducibility error in FP calculations, a method for measuring the sensitivity and precision of GNNs for use in analog IC design recognition has been proposed. The results of the sensitivity and precision measurements of the proposed method show a complex combination of effects between dataset quality (the presence or absence of data duplication), the sensitivity of the GNN to distinguish each feature in the dataset, the complexity of the calculations that occur in the GNN, and the level of quality of the FP calculations performed by the processing unit related to the non-ideal FP calculations. With certain GNN configurations, the proposed method also succeeded in measuring the difference in FP calculation quality of Central Processing Unit (CPU) and Graphics Processing Unit (GPU), where, for big data applications, from the tests carried out, the maximum amount of data that can be distinguished by the CPU is 25 to 100 times more than with the GPU. Because it only uses untrained GNN OVR and does not involve any training process in obtaining results, the proposed method is still unable to obtain a correlation with the final value of GNN performance after training is complete. The measurement method using GNN OVR involving the learning process is future work.

This paper describes the comprehensive verification effort of the IBM System z10™ processor chipset, which consists of the z10™ quad-core central processor chip and the companion z10 symmetric multiprocessor (SMP) chip. The z10 processor chipset represented a significant redesign of its predecessor and thus presented a new challenge to ensure complete functional correctness of the product before the construction of actual system hardware. The z10 microprocessor pipeline was completely redesigned to support a doubling of the operating frequency. It also includes new hardware performance features, such as enhanced branch prediction, a reoptimized cache hierarchy, hardware-based prefetching, and a hardware implementation of decimal floating-point arithmetic in IEEE formats. In addition, there were significant hardware changes in the SMP storage hierarchy for optimized data latency performance. These changes include a new system topology, interprocessor book protocol, larger SMP size, and various aggressive cache ownership schemes. Key verification innovations are described, and a direct relationship to improved z10 system quality is provided for most cases.

Recently, it has been proven that retransmission based on Network Coding (NC) can greatly improve the performance of wireless networks with broadcast erasure channels. However, network coding also introduces additional delay at the both sending and receiving sides, resulting in the decline of the Quality of user Experience (QoE). In this paper, we consider the users' waiting time and the decoding delay as the performance metrics and then propose MixCode, a NC-based loss recovery method, to improve the delay performance in heterogeneous wireless networks. MixCode incorporates Opportunistic Network Coding (ONC) with Random Linear Network Coding (RLNC), where a NC packet can be decoded by simply XORing operation at some destinations, but by Gaussian elimination at other destinations. Simulation results show that our proposed algorithm can efficiently reduce both the waiting time and the decoding delay in comparison with the existing NC-based schemes.

This paper presents two complementary statistical computing frameworks that address challenges in parallel processing and the analysis of massive data. First, the <b>foreach</b> package allows users of the R programming environment to define parallel loops that may be run sequentially on a single machine, in parallel on a symmetric multiprocessing (SMP) machine, or in cluster environments without platform-specific code. Second, the <b>bigmemory</b> package implements memory- and file-mapped data structures that provide (a) access to arbitrarily large data while retaining a look and feel that is familiar to R users and (b) data structures that are shared across processor cores in order to support efficient parallel computing techniques. Although these packages may be used independently, this paper shows how they can be used in combination to address challenges that have effectively been beyond the reach of researchers who lack specialized software development skills or expensive hardware.

There is one, and only one way, consistent with fundamental physics, that the\nefficiency of general digital computation can continue increasing indefinitely,\nand that is to apply the principles of reversible computing. We need to begin\nintensive development work on this technology soon if we want to maintain\nadvances in computing and the attendant economic growth.\n NOTE: This paper is an extended author's preprint of the feature article\ntitled "Throwing Computing Into Reverse" (print) or "The Future of Computing\nDepends on Making it Reversible" (online), published by IEEE Spectrum in\nAug.-Sep. 2017. This preprint is based on the original draft manuscript that\nthe author submitted to Spectrum, prior to IEEE edits and feedback from\nexternal readers.\n

The symmetric multiprocessing (SMP) cluster system, which consists of shared memory nodes with several multicore central processing units connected to a high-speed network to form a distributed memory system, is the most widely available hardware architecture for the high-performance computing community. Today, the Message Passing Interface (MPI) is the most widely used parallel programming paradigm for SMP clusters, in which the MPI provides programming both for an SMP node and among nodes simultaneously. However, Unified Parallel C (UPC) is an emerging alternative that supports the partitioned global address space model that can be again employed within and across the nodes of a cluster. In this paper, we describe a hybrid parallel programming paradigm that was designed to combine MPI and UPC programming models. This paradigm&amp;amp;apos;s objective is to mix the MPI&amp;amp;apos;s data locality control and scalability strengths with UPC&amp;amp;apos;s fine-grain parallelism and ease of programming to achieve multiple-level parallelism at the SMP cluster, which itself has multilevel parallel architecture. Utilizing a proposed hybrid model and comparing MPI-only to UPC-only implementations, this paper presents a detailed description of Cannon&amp;amp;apos;s algorithm benchmark application with performance results of a random-access benchmark and the Barnes--Hut N-Body simulation. Experiments indicate that the hybrid MPI+UPC model can significantly provide performance increases of up to double in comparison with UPC-only implementation, and up to 20% increases in comparison to MPI-only implementation. Furthermore, an optimization was achieved that improved the hybrid performance by an additional 20%.

The performance of microprocessors has increased exponentially for over 35 years. However, process technology challenges, chip power constraints, and difficulty in extracting instruction-level parallelism are conspiring to limit the performance of future individual processors. To address these limits, the computer industry has embraced chip multiprocessing (CMP), predominately in the form of multiple high-performance superscalar processors on the same die. We explore the trade-off between building CMPs from a few high-performance cores or building CMPs from a large number of lower-performance cores and argue that CMPs built from a larger number of lower-performance cores can provide better performance and performance/Watt on many commercial workloads. We examine two multi-threaded CMPs built using a large number of processor cores: Sun's Niagara and Niagara 2 processors. We also explore the programming issues for CMPs with large number of threads. The programming model for these CMPs is similar to the widely used programming model for symmetric multiprocessors (SMPs), but the greatly reduced costs associated with communication of data through the on-chip shared secondary cache allows for more fine-grain parallelism to be effectively exploited by the CMR Finally, we present performance comparisons between Sun's Niagara and more conventional dual-core processors built from large superscalar processor cores. For several key server workloads, Niagara shows significant performance and even more significant performance/Watt advantages over the CMPs built from traditional superscalar processors.

In recent literature, network coding has emerged as a promising information theoretic approach to improve the performance of both peer-to-peer and wireless networks. It has been widely accepted and acknowledged that network coding can theoretically improve network throughput of multicast sessions in directed acyclic graphs, achieving their cut-set capacity bounds. Recent studies have also supported the claim that network coding is beneficial for large-scale peer-to-peer content distribution, as it solves the problem of locating the last missing blocks to complete the download. We seek to perform a reality check of using network coding for peer-to-peer live multimedia streaming. We start with the following critical question: How helpful is network coding in peer-to-peer streaming? To address this question, we first implement the decoding process using Gauss-Jordan elimination, such that it can be performed while coded blocks are progressively received. We then implement a realistic testbed, called Lava, with actual network traffic to meticulously evaluate the benefits and tradeoffs involved in using network coding in peer-to-peer streaming. We present the architectural design challenges in implementing network coding for the purpose of streaming, along with a pull-based peer-to-peer live streaming protocol in our comparison studies. Our experimental results show that network coding makes it possible to perform streaming with a finer granularity, which reduces the redundancy of bandwidth usage, improves resilience to network dynamics, and is most instrumental when the bandwidth supply barely meets the streaming demand.

Network coding has recently attracted attention as a substantial improvement to packet retransmission schemes in wireless multicast broadcast services (MBS). Since the problem of finding the optimal network code maximizing the bandwidth efficiency is hard to solve and hard to approximate, two main network coding heuristic schemes, namely opportunistic and full network coding, were suggested in the literature to improve the MBS bandwidth efficiency. However, each of these two schemes usually outperforms the other in different receiver, demand, and feedback settings. The continuous and rapid change of these settings in wireless networks limits the bandwidth efficiency gains if only one scheme is always employed. In this paper, we propose an adaptive scheme that maintains the highest bandwidth efficiency obtainable by both opportunistic and full network coding schemes in wireless MBS. The proposed scheme adaptively selects, between these two schemes, the one that is expected to achieve the better bandwidth efficiency performance. The core contribution in this adaptive selection scheme lies in our derivation of performance metrics for opportunistic network coding, using random graph theory, which achieves efficient selection when compared to appropriate full network coding parameters. To compare between different complexity levels, we present three approaches to compute the performance metric for opportunistic coding using different levels of knowledge about the opportunistic coding graph. For the three considered approaches, simulation results show that our proposed scheme almost achieves the bandwidth efficiency performance that could be obtained by the optimal selection between the opportunistic and full coding schemes.

네트워크 코딩(Network Coding)은 통신망의 성능 향상에 도움을 줄 수 있으나 이의 소프트웨어적 구현은 부호화/복호화 단계에서 매우 큰 지연시간을 유발할 수 있어 이를 줄일 수 있는 병렬화된 구현이 필수적이라 할 수 있다. 본 논문에서는 랜덤 리니어 네트워크 코딩(Random Linear Network Coding)과 랜덤 리니어 네트워크 코딩의 단점을 보완하고자 최근 제안된 파이프라인 네트워크 코딩(Pipeline Network Coding)의 병렬처리 성능을 비교한다. 또한, 네트워크 코딩의 CPU에서의 병렬처리 기법과 GPGPU(General Purpose Graphics Processing Units)에서의 병렬처리 기법을 비교하여 네트워크 코딩의 사용 시 그 파라미터에 따라 적절한 병렬처리 기법을 선택할 필요성이 있음을 보여준다. Network coding has been shown to improve various performance metrics in network systems. However, if network coding is implemented as software a huge time delay may be incurred at encoding/decoding stage so it is imperative for network coding to be parallelized to reduce time delay when encoding/decoding. In this paper, we compare the performance of parallelized decoders for random linear network coding (RLC) and pipeline network coding (PNC), a recent development in order to alleviate problems of RLC. We also compare multi-threaded algorithms on multi-core CPUs and massively parallelized algorithms on GPGPU for PNC/RLC.

The Internet of Things (IoT) is an emerging network that integrates the physical world and cyberspace through wireless technologies. Due to the ever-growing number of connected devices in IoT, the generated data traffic grows exponentially, so do the bad signal-to-noise-ratio and packets collision. For the past decade, such issue is answered with the deployment of rateless erasure code (REC) and network coding (NC), where promising network throughput is obtained with the trade-off in the computational intensive algorithm, namely Gaussian elimination (GE). Many papers, which have attempted to accelerate the computing speed of GE with graphics processing unit (GPU), have neglected the fact that majority of the network traffic are short messages of tens packets in their studies. This paper has found that GPU can further be utilised to decode many messages in parallel, leading to significant speedup. In this paper, we parallelise the GE in terms of XOR row operations, matrix multiplication and bulk decoding of thousand of messages. Our experimental results demonstrated that a speedup of factor of 6 is achievable with the state-of-the-art GPU as compared to XEON E3 CPU.

This study examines vectorized programming for finite impulse response image filtering. Finite impulse response image filtering occupies a fundamental place in image processing, and has several approximated acceleration algorithms. However, no sophisticated method of acceleration exists for parameter adaptive filters or any other complex filter. For this case, simple subsampling with code optimization is a unique solution. Under the current Moore’s law, increases in central processing unit frequency have stopped. Moreover, the usage of more and more transistors is becoming insuperably complex due to power and thermal constraints. Most central processing units have multi-core architectures, complicated cache memories, and short vector processing units. This change has complicated vectorized programming. Therefore, we first organize vectorization patterns of vectorized programming to highlight the computing performance of central processing units by revisiting the general finite impulse response filtering. Furthermore, we propose a new vectorization pattern of vectorized programming and term it as loop vectorization. Moreover, these vectorization patterns mesh well with the acceleration method of subsampling of kernels for general finite impulse response filters. Experimental results reveal that the vectorization patterns are appropriate for general finite impulse response filtering. A new vectorization pattern with kernel subsampling is found to be effective for various filters. These include Gaussian range filtering, bilateral filtering, adaptive Gaussian filtering, randomly-kernel-subsampled Gaussian range filtering, randomly-kernel-subsampled bilateral filtering, and randomly-kernel-subsampled adaptive Gaussian filtering.