A New Approach for Designing of Computer Architectures Using Multi-Value Logic

The recent advancements in multivalued logic gates represent a rapid paradigm shift in semiconductor technology toward a new era of hyper Moore's law. Particularly, the significant evolution of materials is guiding multivalued logic systems toward a breakthrough gradually, whereby they are transcending the limits of conventional binary logic systems in terms of all the essential figures of merit, i.e., power dissipation, operating speed, circuit complexity, and, of course, the level of the integration. In this review, recent advances in the field of multivalued logic gates based on emerging materials to provide a comprehensive guideline for possible future research directions are reviewed. First, an overview of the design criteria and figures of merit for multivalued logic gates is presented, and then advancements in various emerging nanostructured materials—ranging from 0D quantum dots to multidimensional heterostructures—are summarized and these materials in terms of device design criteria are assessed. The current technological challenges and prospects of multivalued logic devices are also addressed and major research trends are elucidated.

Moore's Law is slowing down but the transistor density is expected to increase by ∼50 in the next 30 years while the power consumed by each transistors will decrease by ∼75. Potential further continuation of Moore's Law via: 1. Spintronics — which could revolutionize computer architecture away from von Neumann model, 2. Memristors — which potentially allows one to do what human brain does in a shoe box instead of a computer the size of a city requiring a nuclear power plant, 3. Graphene with 1 The clock speed, and 4. Quantum Computing. Advances made in meta materials. Iowa Un. demonstrated 6 dB stealthing from 8–10 GHz using thin, stretchable meta material skin that can be conformal on target. The Army Research Laboratory in Adelphi MD has developed a low profile λ/20 thick meta material 250–505 MHZ antenna. Kymeta demonstrated December 2013 transmission to satellites and back using laptop size 20 and 30 GHz antennas which use meta material resonators to effect the phase shifting. For the first time a clear explanation of how this antenna works given. PATRIOT has GaN active electronically scanned arrays (AESAs) which gives 360° coverage without mechanical rotation. AMDR handles >30 times more targets and has >30 times sensitivity of SPY-1D(V). Can now put a 32 element 60 GHz T/R array on a chip. All the RF circuitry for mm-wave radars is put on a chip. Such radars and phased arrays could cost just a few dollars. Major advances in printed flexible electronic circuits with diodes operating at 1.6 GHz and the potential for operation at 2.4GHz, the Wi-Fi band. A low profile dual polarized tightly coupled dipole antenna (TCDA) has been developed which provides a 20:1 bandwidth and has λ /40 thickness. The latest type of phased array is the MIMO radar phased array which has been shown to provide orders of magnitude better accuracy and resolution as well as better GMTI performance than conventional arrays. However, as summarized here, more recently this author has shown that conventional arrays can do just as well if properly used without suffering MIMO's signal processing load and waveform design problems.

Low-power circuit designs are required for battery-operated devices. A transistor needs to be small enough to be integrated onto a single chip. Therefore, CNTFET technology has been widely used to design nanoscale circuits for energy-efficient integration. Multiple-valued logic is utilised to reduce the circuit complexity by minimizing the interconnections. Compared to binary circuits, MVL circuits are more noise sensitive. As a result, it’s essential to consider noise margin into account when designing sustainable and reliable ternary circuits. The paper proposes a standard ternary inverter and compares noise margin, power consumption, delay, and PDP measurements with existing standard ternary inverters. The proposed STI has a 68.6% higher noise margin than the existing designs and 82%, 80%, and 91% improvements in power consumption, PDP, and delay, respectively, over existing circuits.

Since the invention of the transistor, clock frequency increase was the primary method of improving computing performance. As the reach of Moore's law came to an end, however, technology driven performance gains became increasingly harder to achieve, and the research community was forced to come up with innovative system architectures. Today increasing parallelism is the primary method of improving performance: single processors are being replaced by multiprocessor systems and multicore architectures. The challenge faced by computer architects is to increase performance while limited by cost and power consumption. The appearance of cheap and fast interconnection networks has promoted designs based on distributed memory computing. Most modern massively parallel computers, as reflected by the Top 500 list, are clusters of workstations using commodity processors connected by high speed interconnects. Today's massively parallel systems consist of hundreds of thousands of processors. Software technology to program these large systems is still in its infancy. Optimizing communication has become a key to overall system performance. To cope with the increasing burden of communication, the following methods have been explored: (i) Scalability in the messaging system: The messaging system itself needs to scale up to the 100K processor range. (ii) Scalable algorithms reducing communication: As the machine grows in size the amount of communication also increases, and the resulting overhead negatively impacts performance. New programming models and algorithms allow programmers to better exploit locality and reduce communication. (iii) Speed up communication: reducing and hiding communication latency, and improving bandwidth. Following the three items described above, this thesis contributes to the improvement of the communication system (i) by proposing a scalable memory management of the communication system, that guarantees the correct reception of data and control-data, (ii) by proposing a language extension that allows programmers to better exploit data locality to reduce inter-node communication, and (iii) by presenting and evaluating a cache of remote addresses that aims to reduce control-data and exploit the RDMA native network capabilities, resulting in latency reduction and better overlap of communication and computation. Our contributions are analyzed in two different parallel programming models: Message Passing Interface (MPI) and Unified Parallel C (UPC). Many different programing models exist today, and the programmer usually needs to choose one or another depending on the problem and the machine architecture. MPI has been chosen because it is the de facto standard for parallel programming in distributed memory machines. UPC was considered because it constitutes a promising easy-to-use approach to parallelism. Since parallelism is everywhere, programmability is becoming important and languages such as UPC are gaining attention as a potential future of high performance computing. Concerning the communication system, the languages chosen are relevant because, while MPI offers two-sided communication, UPC relays on a one-sided communication model. This difference potentially influences the communication system requirements of the language. These requirements as well as our contributions are analyzed and discussed for both programming models and we state whether they apply to both programming models.

A number of novel voltage-mode multiple-valued logic circuits are introduced. Adopting the main features of the true single-phase clocked logic, efficient quaternary logic dynamic and pseudo-static latches, dynamic and static master-slave storage units, and uni-signal controlled pass gates are proposed. These circuits use two kinds of MOS transistors, i.e., enhancement and depletion mode, each of which has two threshold voltages. The proposed circuits exhibit regular, modular, and iterative structure, which means that the MVL circuits are VLSI implementable and can be easily re-designed for any radix of an arithmetic system. Since we use only clock signal, the derived circuits have low power dissipation. Comparisons with existing circuits prove substantial improvements in terms of speed, power consumption, and transistor count.

Over the past two decades, the clock speed, and hence, the singlecore performance of microprocessors has already stagnated. Following this, the recent faltering of Moore's law due to the CMOS fabrication technology reaching its unavoidable physical limit has presaged daunting challenges for designing power-efficient and ultrafast microprocessors. To overcome these challenges, vigorous efforts have been made to develop new more-than-Moore technologies and architectures for computing. Among these, nanophotonic integrated circuits based computing architectures have shown revolutionary potential. Among recent demonstrations of nanophotonic circuits for computing, a polymorphic, nanophotonic ALU (PoN-ALU) carries a notable importance since it has shown very high flexibility, high speed, and low power consumption for computing. In this paper, we carry out a design space exploration of this PoN-ALU to derive new design guidelines that can help scale the speed and energy efficiency of PoNALU even further.

Background: Passwords are still the predominant way of authentication in information systems, and are mostly at user's responsibility. They conceive, use, re-use, abuse and forget passwords. In absence of strict password policies and at minimum required user training, passwords tend to be short, easy to remember, connected to the user's personal or professional life and consequently easy to break. The additional problem with passwords is their aging: Moore's law is affecting the available computing power to crack passwords and those deemed secure today may easily be broken in the near future. Objective: The aim of this paper is to study various scenarios of the effect the Moore's law is having on passwords and their security. In addition, advancements in other fields, e.g. quantum computing and Internet of Things, are taken into the account. Method: We analyzed various password types and the lengths required to withstand an off-line brute-force attack. The analysis was performed under various scenarios and combinations thereof: the Moore's law will continue to be in the effect for years to come with varying parameters, quantum computing will become feasible, improvements in hash tables computations will speed up the cracking process, and others. Results: The paper shows the minimum password length in characters for each password type under various scenarios. Even the most optimistic scenario shows that the minimum required password length today should be of 11 randomly drawn characters, rendering most of the passwords inappropriate due to their poor memorability. Conclusion: The current textual passwords are cursed by the Moore's law and other advancements in the field. Soon, classical textual passwords will need to be replaced by other mechanisms, which are, fortunately, already emerging.

There is one, and only one way, consistent with fundamental physics, that the\nefficiency of general digital computation can continue increasing indefinitely,\nand that is to apply the principles of reversible computing. We need to begin\nintensive development work on this technology soon if we want to maintain\nadvances in computing and the attendant economic growth.\n NOTE: This paper is an extended author's preprint of the feature article\ntitled "Throwing Computing Into Reverse" (print) or "The Future of Computing\nDepends on Making it Reversible" (online), published by IEEE Spectrum in\nAug.-Sep. 2017. This preprint is based on the original draft manuscript that\nthe author submitted to Spectrum, prior to IEEE edits and feedback from\nexternal readers.\n

Compared to multi-valued logic (MVL) with conventional 2-state FETs with a single threshold, MVL computing architectures, based on 4-state SWS (Spatial wavefunction switched) and QDG (quantum dot gate)-FETs having multiple thresholds, results in reduced device count, higher clock (CLK) speed, and lower power consumption. We have experimentally shown multi-state characteristics in SWS-FETs as well as QDG-FETs. This paper presents a novel QDG-SWS-FET that: (1) functions as a multi-bit FET for efficient low-power logic, (2) can be configured as a quantum dot (QD) nonvolatile random access memory (NVRAM), and (3) is suitable for in-memory MVL computing architecture that are compatible with sub-7nm technology nodes. A QDG-SWS-FET with the addition of a control gate dielectric layer functions as a NVRAM cell. Furthermore, it is shown that one single SWS-QD-NVRAM cell gives the functionality of a 1-bit NAND. We have developed circuit/device models and performed quantum simulations for novel multi-layer quantum dot/quantum well FETs and NVRAMs. Our simulations have shown 4-states/2-bit output-input transfer characteristics in SWS-CMOS inverters and NAND gates using two Si/SiGe quantum well channels.

Multipliers have been key and critical components for most application-specific and general-purpose computer architectures. However, these architectures have been transitioning towards multiple cores that can process large amounts of data through parallel approaches to computation. Unfortunately, traditional arithmetic functional units that worked well for single-core architectures have the side-effect of incurring large amounts of area and power. Consequently, multi-core computer architecture need new ways of thinking about increased throughput to handle large amounts of data. This paper presents a recursive high radix divide unit that is modified to handle both multiplication and division targeted at multi-core architectures. Results are obtained with a 65nm technology and show a significant decrease in area and power while still maintaining a low total latency by utilizing high radix encoding within the functional unit. More importantly, because the datapath unit requires complex recoding, it does not increase its latency as the bit size increases. Therefore, these units can occupy low amounts of area while still maintaining high amounts of processing power.

: Moore's Law: The number of transistors that can be placed on a micro-circuit doubles every 18-24 months, resulting in a rapid turnover in generations of microcircuits. There are almost as many opinions about how long Moore's Law will be applicable as there have been technological advances since the Law was first annunciated in 1965. The majority of industry experts however believe that the physical limits of silicon based advancements will be reached by the end of the decade. Microelectronics obsolescence will remain a challenge as industry and academia alike are hard at work on marketing post-silicon applications. New atomic compounds such as gallenium arsenide and ferritin may replace silicon substrates within integrated circuits while entirely new technologies like quantum computing may transform the entire industry. The point is that while Moore's Law will end relatively soon innovation will not--and DoD program managers (PM) will still have to manage obsolescence.

Wireless internet access technologies have significant market potential, especially the WiMAX protocol which can offer data rate of tens of Mbps. A significant demand for embedded high performance WiMAX solutions is forcing designers to seek single-chip multiprocessor or multi-core systems that offer competitive advantages in terms of all performance metrics, such as speed, power and area. Through the provision of a degree of flexibility similar to that of a DSP and performance and power consumption advantages approaching that of an ASIC, emerging dynamically reconfigurable processors are proving to be strong candidates for future high performance multi-core processor systems. This paper presents several new single-chip multi-core architectures, based on newly emerging dynamically reconfigurable processor cores, for the WiMAX physical layer. A simulation platform is proposed in order to explore and implement various multi-core solutions combining different memory architectures and task partitioning schemes. The paper describes the architectures, the simulation environment, several task partitioning methods and demonstrates that up to 4.9x speedup can be achieved by employing five dynamically reconfigurable processor cores each having individual local memory units.

With Moore's law supplying billions of transistors on-chip, embedded systems are undergoing a transition from single-core to multi-core to exploit this high transistor density for high performance. However, there exists a plethora of multi-core architectures and the suitability of these multi-core architectures for different embedded domains (e.g., distributed, real-time, reliability-constrained) requires investigation. Despite the diversity of embedded domains, one of the critical applications in many embedded domains (especially distributed embedded domains) is information fusion. Furthermore, many other applications consist of various kernels, such as Gaussian elimination (used in network coding), that dominate the execution time. In this paper, we evaluate two embedded systems multi-core architectural paradigms: symmetric multiprocessors (SMPs) and tiled multi-core architectures (TMAs). We base our evaluation on a parallelized information fusion application and benchmarks that are used as building blocks in applications for SMPs and TMAs. We compare and analyze the performance of an Intel-based SMP and Tilera's TILEPro64 TMA based on our parallelized benchmarks for the following performance metrics: runtime, speedup, efficiency, cost, scalability, and performance per watt. Results reveal that TMAs are more suitable for applications requiring integer manipulation of data with little communication between the parallelized tasks (e.g., information fusion) whereas SMPs are more suitable for applications with floating point computations and a large amount of communication between processor cores.

Tremendous amounts of data are being generated and should be processed during the massive employment of artificial intelligence and edge/cloud computing, necessitating computers with higher capabilities. However, as Moore's Law approaches its limit, enhancing computing capability through transistor miniaturization is becoming less feasible. New strategies for “more-than-Moore” are highly preferred to drive future technological advancements. Multiple-valued logic, especially ternary logic with its superior data density compared to traditional binary logic, offers a viable route to augment computing capability while reducing chip interconnections and dynamic power consumption. Despite the growing interest in ternary logic within academia and industry, its practical application remains limited due to the increased transistor count and connections required by earlier logic gate implementations. In this thesis, we present efficient implementation methods of basic ternary logic gates based on emerging nano-electronics including two-dimensional material-based transistors. The fabricated ternary devices show high performance in DC gain and low power consumption. Additionally, compact models of the devices have been established and calibrated, facilitating the circuit design and simulation in Electronic Design Automation (EDA) tools. At the circuit level, this thesis introduces novel ternary arithmetic circuits, including adders and multipliers, that are optimized for low power consumption and minimal delay. Finally, we showcase the practical benefits of ternary logic systems in data processing through the implementation of carry-free arithmetic circuits, underscoring their potential as a transformative computing paradigm.

Binary linear feedback shift registers (LFSR's) have acquired great importance in their implementation of a method of data compaction used in the testing of digital circuits. In this paper a new idea is examined: using multiple-valued LFSR's for the testing of MVL circuits and of binary circuits. For MVL circuits a non-binary LFSR avoids the need of decoding the signals and its implementation requires fewer digits than the binary tester. For binary circuits, a multi-valued LFSR tester shows higher effectiveness while maintaining a smaller implementation. An analysis is given of fault coverage for binary and multi-valued circuits, and optimal implementations of multi-valued LFSR's are presented.