Applications of multi-valued logic to testing of binary and MVL circuits

Automatic Test Pattern Generation (ATPG) is one of the core algorithms in testing of digital circuits and systems. Based on a given fault model a list of all faults to be tested, i.e. the fault list, is being created. For each fault in this list, one test pattern is generated (this pattern may cover other faults). Thereby, the order of the faults is crucial. In industrial ATPG, typically a simple list is used as fault list until today. In this work, we introduce a two-dimensional fault list and different strategies to order this list. The target is to reduce the number of generated patterns. The techniques are implemented in an industrial ATPG-framework. They are evaluated on industrial circuits. The results are discussed and a general purpose strategy is given.

Automatic Test Pattern Generation (ATPG) is one of the core algorithms in testing of digital circuits and systems. Due to recent advances in algorithms to solve Boolean Satisfiability (SAT), there is a renewed interest in SAT-based ATPG. While the early approaches only used two-valued logic, modern tools have to use multiple values to model unknown values and tri-state elements for buses. In this paper we present a detailed study on how to chose the multi-valued encoding for SAT-based ATPG. The techniques have been implemented and evaluated on large industrial benchmarks.

Techniques for SAT-based constrained test pattern generation

The paper shows an influence of a choice of autonomous testing structure on fault coverage in synchronous digital sequential circuit testing. In order to increase testability of sequential circuit during testing, its memory module usually undergoes a disconnection. At the time the testing structure gains access to no-primary output of the testing circuit. The circuit undergoes transformation into combinational circuit. A possibility of disconnection of a memory module results from including of multifunctional registers which execute a circuit memory function. It turns out that high fault coverage may often be gained without disconnection of the module. Thus, it is not necessary to apply such registers. Therefore the complexity of circuit is limited as far as a circuit area overhead for its application and additional mode control during its work are concerned. Nevertheless, it is not always possible. Even partial disconnection of memory modules during testing phase enables to increase fault coverage due to increasing circuit testability. Simulation studies carried out on a considerate amount of ISCAS'89 testing circuits set show rightness of introduced conception of sequential circuits testing without interference with its memory function. An important factor enabling suggested approach is an adequate choice of autonomous testing structure.

Researchers have proposed different methods for testing digital systems and circuits in the last couple of decades. The need for testing digital logic circuits has become more important than ever due to the growing complexity of such systems. During the design phase, testing is focusing on design defects, as well as manufacturing and wear out type of defects. Failures in digital systems could be caused, for example, by design errors, the use of inherently probabilistic devices, and manufacturing variability. As a way to test digital systems in a more efficient way, automated test generation has been proposed to automatically create tests that can quickly and accurately identify faulty components. Examples of such techniques are the sequential test generation, the scan path testing, and the random test generation techniques. With the research domain becoming more mature and growing, it is essential to systematically identify, analyze, and classify these contributions. We performed a systematic mapping study of automated test generation for digital circuits aimed at providing an overview of the application of these techniques. We focused on three of the most widely-used and well-supported hardware description languages (HDLs) for digital systems: Verilog, SystemVerilog, and VHDL. Our results suggest that the majority of the test generation methods for digital circuits are focused on the behavioral and register-transfer design levels. Fault-independent and fault-oriented test generation are the most frequently reported types of test generation methods, while HDL model simulation is the most common test generation technology used to search for test cases in these academic studies. While the results are suggesting a growing interest in this area, the majority of articles are published as conferences papers. Our results show that only 31% of the methods are implemented as software tools and only 63% of all contributions are actually generating executable test cases. This study makes three important contributions, (i) a state-of-the-art of test generation for digital system designs research is provided, (ii) the reported characteristics are identified in both the primary papers and experimental reports, (iii) gaps and opportunities for future test generation for digital system designs research are identified.

Low-power circuit designs are required for battery-operated devices. A transistor needs to be small enough to be integrated onto a single chip. Therefore, CNTFET technology has been widely used to design nanoscale circuits for energy-efficient integration. Multiple-valued logic is utilised to reduce the circuit complexity by minimizing the interconnections. Compared to binary circuits, MVL circuits are more noise sensitive. As a result, it’s essential to consider noise margin into account when designing sustainable and reliable ternary circuits. The paper proposes a standard ternary inverter and compares noise margin, power consumption, delay, and PDP measurements with existing standard ternary inverters. The proposed STI has a 68.6% higher noise margin than the existing designs and 82%, 80%, and 91% improvements in power consumption, PDP, and delay, respectively, over existing circuits.

In the last decade, we have seen how Moore's law has lost its validity because it has reached the physical limit of miniaturization of components and the problem of thermal dissipation increasing with the chip’s clock frequency. For this reason, multi-core architectures were born, and quantum computing is being looked at as a possible solution for more computing power. The aim of this article is to demonstrate the possibility to realize computer architectures using multi-value logic. The objective is reached when we are able to translate any MVL function into the corresponding MVL circuit. The method proposed is completely independent of the basis adopted in the MVL domain and the physical quantity used to represent or transfer the domain values. Thus, this approach provides a new theoretical and practical context for applying new technologies or polymorphic materials, which can represent multiple values. In order to give concreteness to the analyzed theoretical aspects, we will represent a case study based on a classical combinational circuit, the summing circuit using LTspice® XVII (© Analog Device Corporation) as simulation environment has been carried out. The results show that it is possible to build MVL combinatorial circuits, although there are limitations because the proposed solution is just a proof of concept. The method can also be successfully applied to sequential MVL circuits, which are not the subject of the present article.

Digital LSI circuits, and digital blocks in many cases fulfill a succession of operation from limited collection. In this paper computer modeling of LSI logical circuits represents logical signals on the pins. For a computer-aided design it is very important to develop the collection of tests for digital LSI circuits for proving the successfulness of design. The most productive and economical test set could be generated if a formal description of digital block or system possible input data domain is known. The input data domain structure are analyzed and described for digital blocks and systems with finite alphabet of functions. The formal description of input data domain for each function of digital block or system are proposed. Proposed description has the form of labeled directed graph describing the sequence of input logical signals with timing constrains.

The testing of digital logic circuits has become quite complex owing to miniaturisation and its associated increase in circuit function per unit area. Methods have been devised for testing ASIC products and, latterly, board level products. A new method (BILCO) is presented for probing asynchronous combinational logic circuits using a novel development of scan path principles.

Many universities use the metal gate PMOS process for educational laboratory projects in the fabrication of integrated circuits. A semiconductor parameter analyzer is often used for testing the transistors, resistors and inverters on their test chips. The semiconductor parameter analyzer cannot be used for testing a digital circuit with a large number of inputs and outputs. A low cost digital circuit tester has been created using a personal computer and additional boards for output and input. Lab View software was used to create a graphical interface with the test system. The test system has been used to functionally test multiplexers, demultiplexers, full-adders and other digital integrated circuits. The test system generates a plot of input and output voltages versus time very similar to a digital circuit simulator output.

A low-overhead scheme for achieving complete (100%) fault coverage during built-in self test of circuits with scan is presented. It does not require modifying the function logic and does not degrade system performance (beyond using scan). Deterministic test cubes that detect the random-pattern-resistant (r.p.r.) faults are embedded in a pseudorandom sequence of bits generated by a linear feedback shift register (LFSR). This is accomplished by altering the pseudorandom sequence by adding logic at the LFSR's serial output to fix certain bits. A procedure for synthesizing the bit-fixing logic for embedding the test cubes is described. Experimental results indicate that complete fault coverage can be obtained with low hardware overhead. Further reduction in overhead is possible by using a special correlating automatic test pattern generation procedure that is described for finding test cubes for the r.p.r. faults in a way that maximizes bitwise correlation.

A number of novel voltage-mode multiple-valued logic circuits are introduced. Adopting the main features of the true single-phase clocked logic, efficient quaternary logic dynamic and pseudo-static latches, dynamic and static master-slave storage units, and uni-signal controlled pass gates are proposed. These circuits use two kinds of MOS transistors, i.e., enhancement and depletion mode, each of which has two threshold voltages. The proposed circuits exhibit regular, modular, and iterative structure, which means that the MVL circuits are VLSI implementable and can be easily re-designed for any radix of an arithmetic system. Since we use only clock signal, the derived circuits have low power dissipation. Comparisons with existing circuits prove substantial improvements in terms of speed, power consumption, and transistor count.

An efficient method to determine linear feedback connections in shift registers that generate maximal length pseudo-random up and down binary sequences

The test pattern generator produces test vectors that are applied to the tested circuit during pseudo-random testing of combinational circuits. The nature of the generator thus directly influences the fault coverage achieved. In this paper we discuss the influence of the type of pseudo-random pattern generator on stuck-at fault coverage. Linear feedback shift registers (LFSRs) are mostly used as test pattern generators, and the generating polynomial is primitive to ensure the maximum period. We have shown that it is not necessary to use primitive polynomials, and moreover that their using is even undesirable in most cases. This fact is documented by statistical graphs. The necessity of the proper choice of a generating polynomial and an LFSR seed is shown here, by designing a mixed-mode BIST for the ISCAS benchmarks.An alternative to LFSRs are cellular automata (CA). We study the effectiveness of CA when used as pseudo-random pattern generators. The observations are documented by statistical results.

Due to the increasing use of portable computing and wireless communications systems, energy consumption is of major concern in today's VLSI circuits. With that in mind we present an energy conscious weighted random pattern testing technique for Built-In-Self-Test (BIST) applications. Energy consumption during BIST operation can be minimized while achieving high fault coverage. Simple measures of observability and controllability of circuit nodes are proposed based on primary input signal probability (probability that a signal is logic ONE). Such measures help determine the testability of a circuit. We developed a tool, POWERTEST, which uses a genetic algorithm based search to determine optimal weight sets (signal probabilities or input signal distribution) at primary inputs to minimize energy dissipations. The inputs conforming to the primary input weight set can be generated using cellular automata or LFSR (Linear Feedback Shift Register). We observed that a single input distribution (or weights) may not be sufficient for some random-pattern resistant circuits, while multiple distributions consume larger area. As a trade-off, two distributions have been used in our analysis. Results on ISCAS benchmark circuits show that energy reduction of up to 97.82% can be achieved (compared to equi-probable random-pattern testing with identical fault coverage) while achieving high fault coverage.