Bit-fixing in pseudorandom sequences for scan BIST

In the Reconfigurable System-On-a-Chip (RSOC), an FPGA core is embedded to improve the design flexibility of SOC. In this paper, we demonstrate that the embedded FPGA core is also feasible for use in implementing the proposed hybrid pattern Built-In Self-Test (BIST) in order to reduce the test cost of SOC. The hybrid pattern BIST, which combines Linear Feedback Shift Register (LFSR) with the proposed on-chip Deterministic Test Pattern Generator (DTPG), can achieve not only complete Fault Coverage (FC) but also minimum test sequence by applying a selective number of pseudorandom patterns. Furthermore, the hybrid pattern BIST is designed under the resource constraint of target FPGA core so that it can be implemented on any size of FPGA core and take full advantage of the target FPGA resource to reduce test cost. Moreover, the reconfigurable core-based approach has minimum hardware overhead since the FPGA core can be reconfigured as normal mission logic after testing such that it eliminates the hardware overhead of BIST logic. Experimental results for ISCAS 89 benchmarks and a platform FPGA chip have proven the efficiency of the proposed approach.

A new technique called input reduction is proposed for built-in self test (BIST) test pattern generator (TPG) design and test set compaction. This technique analyzes the circuit function and identifies sets of compatible and inversely compatible inputs; inputs in each set can be combined into a test signal in the test mode without sacrificing fault coverage, even if they belong to the same circuit cone. The test signals are used to design BIST TPGs that guarantee the detection of all detectable stuck-at faults in practical test lengths. A deterministic test set generated for the reduced circuit obtained by combining inputs into test signals is usually more compact than that generated for the original circuit. Experimental results show that BIST TPGs based on input reduction achieve complete stuck-at fault coverage in practical test lengths (/spl les/2/sup 30/) for many benchmark circuits. These are achieved with low area overhead and performance penalty to the circuit under test. Results also show that the memory storage and test application time for external testing using deterministic test sets can be reduced by as much as 85%.

A new algorithm for the reseeding of multiple polynomial LFSR for pseudorandom test pattern generation (PRPG) is proposed in this paper. It is based on the Gauss-elimination procedure and the deterministic test set generated by an ATPG software system for combinational circuits. In addition to the general LFSR model, we also provide two further improvements, ms1p and 1smp, to minimize the hardware overhead. Experimental results were obtained on ISCAS-85 benchmark circuits to demonstrate the effectiveness of this methodology. Complete fault coverage is achieved in all circuits. Low hardware overhead is also maintained with a reasonable test length. >

A new algorithm for the reseeding of multiple polynomial LFSR for pseudorandom test pattern generation (PRPG) is proposed in this paper. It is based on the Gauss-elimination procedure and the deterministic test set generated by an ATPG software system for combinational circuits. In addition to the general LFSR model, we also provide two further improvements, ms1p and 1smp, to minimize the hardware overhead. Experimental results were obtained on ISCAS-85 benchmark circuits to demonstrate the effectiveness of this methodology. Complete fault coverage is achieved in all circuits. Low hardware overhead is also maintained with a reasonable test length. >

When using Built-In Self Test (BIST) for testing VLSI circuits, a major concern is the generation of proper test patterns that detect the faults of interest. Usually a linear feedback shift register (LFSR) is used to generate test patterns. We first analyze the probability that an arbitrary pseudo-random test sequence of short length detects all faults. The term short is relative to the probability of detecting the fault having the fewest test patterns. We then show how to guide the search for an initial state (seed) for a LFSR with a given primitive feedback polynomial so that all the faults of interest are detected by a minimum length test sequence. Our algorithm is based on finding the location of test patterns in the sequence generated by this LPSR. This is accomplished using, the theory of discrete logarithms. We then select the shortest subsequence that includes test patterns for all the faults of interest, hence resulting in 100% fault coverage. >

A challenging issue is the derivation of a finite test suite from a given LOTOS specification modeled by a labeled transition system (LTS) such that complete fault coverage is guaranteed for a certain class of implementations with respect to a particular conformance relation. It is shown in this paper that this problem can be solved by translating an LTS into an input/output finite state machine (FSM) for trace or failure semantics, respectively, and subsequently applying existing FSM-based methods for test derivation with complete fault coverage. It is also demonstrated that the obtained tests can be further optimized taking into account the specifics of the FSMs constructed from the LTSs.KeywordsTest SuiteFinite State MachineLabel Transition SystemConformance TestingImplementation Under TestThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Many Built-in Self Test (BIST) pattern generators use Linear Feedback Shift Registers (LFSR) to generate test sequences. In this paper, we address the generation of deterministic pairs of patterns for delay faults testing with LFSRs. A new synthesis procedure for a n-size LFSR is given and guarantees that a deterministic set of n precomputed test pairs is embedded in the maximal length pseudo-random test sequence of the LFSR. Sufficient and necessary conditions for the synthesis of this pseudo-deterministic LFSR are provided and show that at-speed delay faults testing becomes a reality without any additional cost for the LFSR. Moreover, since the theoretical properties of LFSRs are preserved, our method could be beneficially used in conjunction with any other technique proposed so far.

Safety-critical technology rests on optimised and effective testing techniques for every embedded system involved in the equipment. Pattern generator (PG) such as linear feedback shift register (LFSR) is used for fault detection and useful for reliability and online test. This study presents an analysis of the LFSR, using a known automatic test PG (ATPG) test set. Two techniques are undertaken to target difficult-to-detect faults with their respective trade-off analysis. This is achieved using Berlekamp-Massey (BM) algorithm with optimisations to reduce area overhead. The first technique (concatenated) combines all test sets generating a single polynomial that covers complete ATPG set (baseline-C). Improvements are found in Algorithm 1 reducing polynomial size through Xs assignment. The second technique uses non-concatenated test sets and provides a group of LFSRs using BM without including any optimisation (baseline-N). This algorithm is further optimised by selecting full mapping and independent polynomial expressions. Results are generated using 32 benchmarks and 65 nm technology. The concatenated technique provides reductions on area overhead for 90.6% cases with a best case of 57 and 39% means. The remaining 9.4% of cases, non-concatenated technique provides the best reduction of 37 with 1.4% means, whilst achieving 100% test mapping in both cases.

The test pattern generator produces test vectors that are applied to the tested circuit during pseudo-random testing of combinational circuits. The nature of the generator thus directly influences the fault coverage achieved. In this paper we discuss the influence of the type of pseudo-random pattern generator on stuck-at fault coverage. Linear feedback shift registers (LFSRs) are mostly used as test pattern generators, and the generating polynomial is primitive to ensure the maximum period. We have shown that it is not necessary to use primitive polynomials, and moreover that their using is even undesirable in most cases. This fact is documented by statistical graphs. The necessity of the proper choice of a generating polynomial and an LFSR seed is shown here, by designing a mixed-mode BIST for the ISCAS benchmarks.An alternative to LFSRs are cellular automata (CA). We study the effectiveness of CA when used as pseudo-random pattern generators. The observations are documented by statistical results.

We present a novel approach for built-in self test (BIST) for VLSI. Many conventional BIST schemes use signatures generated by a linear feedback shift register (LFSR) or a multiple input signature register (MISR) for determining whether the device under test is faulty or fault free. In the approach presented, fault detection is made based on the number of different states the LFSR visits. This number is called the cycle length. It is also shown that such an approach results in the probability of aliasing of 2/sup -(2m-1+m/), where m denotes the number of registers in the LFSR, compared to 2/sup -m/ achieved by conventional signature analyzers. We also present the complexity of the additional hardware required to implement the scheme.

Test cost is increasingly becoming a major component of a product's design cost in scaled technologies. Exponential increase in test data volumes for sub-45 designs, especially for testing delay faults has led to large increase in ATE cost and test application time. In order to reduce external test cost, Logic BIST has been explored as a possible alternative to manufacturing test [1-5]. However, this paper shows that a large number of faults in BIST logic of large IWLS'05 and ITC'99 benchmark processors remain undetected after BIST run (42% of stuck-at and 34% of transition faults on average) and thus, BIST logic needs to be tested properly. This paper proposes a hierarchical BIST methodology `HBIST' which uses different BIST techniques to obtain complete stuck-at and transition fault coverage of CUT and then introduces additional levels of BIST logic to test for faults in the BIST logic at the preceding levels. A design methodology is proposed to optimize the number of additional levels of BIST required while keeping the BIST area and power overhead, and the addition of extra faults in BIST logic minimal. Experiments on large benchmarks show an average of 95.9% CUT stuck-at fault coverage (ATPG coverage of 96.4%) and 93.5% CUT transition fault coverage (ATPG coverage of 95.3%) is obtained using HBIST. Also, up to 99.2% (average 93.2%) reduction in external ATE test cost (including cost needed to test additional BIST levels) is obtained using two levels of BIST at 7% average area overhead (compared to scan overhead of 38.2%) and 18% increase in test power.

Linear feedback shift registers (LFSRs) are essential components of communications systems such as pseudo random bit sequence (PRBS) generators, convolutional encoders, scramblers and randomizers [1, 2]. Fig.1 (left) shows a LFSR scheme in which the XOR gate is operated among two tapped bits i and i+k within the shift register. The result bit is fed to the shift register at the last position (n) and the sequence in the register is 1-bit shifted as well. The experimental setup for demonstrating an all-optical LFSR is shown in Fig.1 (middle). The main components of the scheme are an optical buffer [3], a bit selecting circuit, and a XOR gate. The data vector (A) is generated by modulating the continuous wave (CW) λ s with a 10Gbps non-return-to-zero (NRZ) electrical pattern whose period is T P =33.3168µs. Only 5 bits are used as the initial sequence for the shift register. The travelling time of the packet in the buffer is T L =1.85 µs, meaning that up to 18 round trips can be accommodated by the pattern's period T P but one of those should be preserved for erasing the buffer before it is fetched a new sequence. The initial sequence enters the buffer as well as propagates directly to the bit selecting circuit. Every round trip, a new sequence as a replica of the previous one plus the feedback bit comes out. At the last round trip, a pump signal inserted into the buffer through the circulator will strongly reduce the gain of the semiconductor optical amplifier (SOA). Both the circulating packet and the accumulating in-band amplified spontaneous emission (ASE) noise will be suppressed. The buffer is now completely cleaned for a new cycle. The first and the last bits of the 1-bit shifted sequence are selected for the XOR operation. Referring to Fig.1 (left), i=1 and k=4, n=5. With this setup, the bit selecting circuit requires 2 clock signals (C) for tap the proper bits from the incoming sequence. The sampling process is done by exploiting four-wave-mixing (FWM) in a 250m-long highly nonlinear fiber (HNLF). Since at every round trip the sequence must be 1-bit shifted, the sampling clocks must be accordingly delayed for 1 bit, resulting the clock period of T C =T L +T B where T B =100ps is the bit time. The outputs of the bit selecting circuit are fed as pump signals to port a and d of a SOA Mach Zehnder interferometer (MZI). They are synchronized with a clock at λ s used as the probe signal (F) at port b. The output of the XOR gate is then fed back into the buffer. The feedback bit should be precisely allocated at the end of the packet circulating inside the buffer, meaning that the feedback time should be T F =T L +T B +T seq in which T seq is the original sequence duration and equal to 500ps in our setup. Fig.1 (right) depicts the results at the 10th round trip for two different input initial sequences (10001) and (10011) taken at point (B). The equalization between bits in the sequence and the quality of the pulses is strongly limited by the accumulating ASE noise inside the buffer, the long fiber-based structure and the bit's polarization. The fiber-based setup also causes misalignment between the clocks, spoils the essential synchronism and degrades the performance of the FWM and the XOR operation. One possible solution for solving all of these problems and hence improving the performance is the integration approach. The bit selection could be implemented exploiting nonlinear effects into an SOA or a periodic-poled lithium niobate (PPLN) instead of using a long HLNF. Moreover the extinction ratio of the pulses at the SOA-MZI XOR output (<13.5dB) could be improved, e.g. with a saturable absorber at its output, thus increasing the number of allowed round trips into the shift register and reducing the noise on the final bit sequence.

The conventional test-per-scan built-in self-test (BIST) scheme needs a number of shift cycles followed by one capture cycle. Fault effects received by the scan flip-flops are shifted out while shifting in the next test vector, like scan testing. Unlike deterministic testing, it is unnecessary to apply a complete test vector to the scan chains. A new scan-based BIST scheme is proposed by properly controlling the scan enable signals of the scan chains. Different weighted values are assigned to the scan enable signals of scan flip-flops in separate scan chains. Capture cycles can be inserted at any clock cycle if necessary. A new testability estimation procedure according to the proposed testing scheme is presented. A greedy procedure is proposed to select a weight for each scan chain. Experimental results show that the proposed method can improve test effectiveness of scan-based BIST greatly and most circuits can obtain complete fault coverage or very close to complete fault coverage.

To obtain satisfactory fault coverage for testing a logic circuit, linear feedback shift registers (LFSRs) have been used to generate not only the pseudorandom, but also the deterministic patterns in the scan-based built-in self-test environment. However, like other scan-based methods, the LFSR based pattern generation schemes take a long test application time to feed deterministic patterns from the LFSR into a scan chain. In this paper we derive a general relationship between the bits in the scan chain and the states of the LFSR and show that any bit to be generated by an LFSR in any future clock cycle can be pre-generated by a linear function of the current LFSR state. With this relationship, we can divide a scan chain into multiple sub-chains and use one LFSR-based multiple sequence generator to simultaneously generate all the subsequences required by the sub-chains, hence can greatly reduce the test application time for deterministic patterns. Moreover, due to the scan time reduction, test power wasted during the scan operation can also be significantly reduced.

Random number generators represent basic cryptographic primitives. They are widely used in modern security schemes including security protocols, computer security and password sources. In some algorithms (e.g. DSA) or protocols (e.g. zero-knowledge), random numbers are intrinsic to the computation [3]. In all these applications, strength of security depends greatly on the quality of randomness of the source. Pseudo random number generators (PRNGs) play an important role in cryptographic applications, as the security of these systems depends on the assumption that future values in the random sequence can be unpredictable. A linear feedback shift register (LFSR), in effect, implements a binary polynomial generator. These generators find common use for PRNGs. However, the random sequence generated by LFSR can not guarantee the unpredictability in secure system. We have used genetic algorithm to improve LFSR and proposed a novel random number generator with complex architecture and longer period.