LFSR generation for high test coverage and low hardware overhead

A low-overhead scheme for achieving complete (100%) fault coverage during built-in self test of circuits with scan is presented. It does not require modifying the function logic and does not degrade system performance (beyond using scan). Deterministic test cubes that detect the random-pattern-resistant (r.p.r.) faults are embedded in a pseudorandom sequence of bits generated by a linear feedback shift register (LFSR). This is accomplished by altering the pseudorandom sequence by adding logic at the LFSR's serial output to fix certain bits. A procedure for synthesizing the bit-fixing logic for embedding the test cubes is described. Experimental results indicate that complete fault coverage can be obtained with low hardware overhead. Further reduction in overhead is possible by using a special correlating automatic test pattern generation procedure that is described for finding test cubes for the r.p.r. faults in a way that maximizes bitwise correlation.

The most important step in the final testing of fabricated ASICs or the functional testing of ASIC and FPGA designs is the generation of a complete test set that is able to find the possible errors in the design. Automatic Test Pattern Generation (ATPG) is often done by fault simulation which is very time-consuming. Speed-ups in this process can be achieved by emulating the design on an FPGA and using the actual speed of the hardware implementation to run proposed tests. However, faults then have to be actually built in into the design, which induces area overhead as (part of) the design has to be duplicated to introduce both a faulty and a correct design. The area overhead can be mitigated by run-time reconfiguring the design, at the expense of large reconfiguration time overheads. In this paper, we leverage the parameterised reconfiguration of FPGAs to create an efficient Automatic Test Pattern Generator with very low overhead in both area and time. Experimental results demonstrate the practicality of the new technique as, compared to conventional tools, we obtain speedups of up to 3 orders of magnitude, 8X area reduction, and no increase in critical path delay.

Testing for delay and CMOS stuck-open faults requires two pattern tests and test sets are usually large. Built-in self-test (BIST) schemes are attractive for such comprehensive testing. The BIST test pattern generators (TPGs) for such testing should be designed to ensure high pattern-pair coverage. In this paper, necessary and sufficient conditions to ensure complete/maximal pattern-pair coverage for linear feedback shift register (LFSR) and cellular automata (CA) have been derived. The theory developed here identifies all LFSR/CA TPGs which maximize pattern-pair coverage under any given TPG size constraints. It is shown that LFSRs with primitive feedback polynomials with large number of terms are better for two-pattern testing. Also, CA are shown to be better TPGs than LFSRs for two-pattern testing. Results derived in this paper provide practical algorithms for the design of optimal TPGs for two-pattern testing. Experiments on some benchmark circuits indicate the TPGs designed using the procedures outlined in this paper provide much higher delay fault coverage than other TPGs. >

Many Built-in Self Test (BIST) pattern generators use Linear Feedback Shift Registers (LFSR) to generate test sequences. In this paper, we address the generation of deterministic pairs of patterns for delay faults testing with LFSRs. A new synthesis procedure for a n-size LFSR is given and guarantees that a deterministic set of n precomputed test pairs is embedded in the maximal length pseudo-random test sequence of the LFSR. Sufficient and necessary conditions for the synthesis of this pseudo-deterministic LFSR are provided and show that at-speed delay faults testing becomes a reality without any additional cost for the LFSR. Moreover, since the theoretical properties of LFSRs are preserved, our method could be beneficially used in conjunction with any other technique proposed so far.

This paper presents a novel test point insertion method for pseudo-random built -in self-test (BIST) to reduce the area overhead. R ecently, a new test point insertion method for BIST was proposed which tries to use functional flip -flops to drive control test points instead of adding extra dedicated flip - flops for driving the control points. Replacement rule used in the previous work has limitations preventing some dedicated flip-flops from being replaced by functional flip -flops. This paper proposes a logic cone analysis based test point insertion approach to overcome the limitations. Logic cone analysis is performed to find candida te functional flop -flops for replacing dedicated flip -flops. Experimental results indicate that the proposed method reduces test point area overhead significantly with minimal loss of testability by replacing the dedicated flip - flops. application to the inputs of the circuit -under-test (CUT). The output response analyzer compacts the output response of the CUT into a signature. T his provides a variety of benefits including the ability to apply a large number of test patterns in a short time (i.e., shorter test time) , at-speed testing, minimal automatic test equipment (ATE) storage requirements, test application in the field over t he lifetime of the part, and a reusable test solution for embedded cores. In particular, BIST is crucial for applications such as aerospace, defense, automotive, computer, etc., for the reliability of the entire system. The most economical logic BIST te chniques are based on pseudo-random pattern testing. On -chip input pattern generator constructed from a linear feedback shift register (LFSR) is most commonly used to generate pseudo -random patterns with its compact structure. And on -chip output response analyzer compacts the output responses into a signature and this allows significant compaction of test data. Pseudo-random pattern testing also can achieve high coverage of non-modeled faults which are not explicitly targeted during deterministic test ge neration. However, a major challenge is the presence of random -pattern-resistant (r.p.r.) faults which have low detection probabilities and hence may limit the fault coverage that can be achieved with pseudo -random patterns. There have been many research efforts to overcome the fault coverage limitation by r.p.r faults. Mainly two directions are given to enhance the fault coverage. One is to modify the pattern generator in order to generate patterns that detect hard faults. Various methods have been pr oposed such as weighted pattern generation ( 2), (4)-(8), pattern mapping ( 9)- (11), bit-fixing (12), bit-flipping (13), and LFSR reseeding (14)-(19).

A fixing-shifting encoding (FSE) method is proposed to reduce test cost of IP cores. The FSE method reduces test cost by supporting multiple-mode loading test data, i.e., parallel loading, left-direction, and right-direction serial loading for each test slice data. Furthermore, the FSE that utilizes only two test channels can support a large number of internal scan chains and achieve further reduction in test cost by combining with scan chain clustering method. As a non-intrusive and automatic test pattern generation (ATPG) independent solution, the approach is applicable to IP core testing because it requires neither redesign of the core under test (CUT) nor running any additional ATPG for the encoding procedure. In addition, the decoder has low hardware overhead, and its design is independent of the CUT. Experimental results for some large ISCAS 89 benchmarks and an industry ASIC design have proven the efficiency of the proposed approach

Excessive power dissipation caused by large amount of switching activities has been a major issue in scan-based testing. For large designs, the excessive switching activities during launch cycle can cause severe power droop, which cannot be recovered before capture cycle, rendering the at-speed scan testing more susceptible to the power droop. In this paper, we present a methodology to avoid power droop during scan capture without compromising at-speed test coverage. It is based on the use of a low area overhead hardware controller to control the clock gates. The methodology is ATPG (Automatic Test Pattern Generation)-independent, hence pattern generation time is not affected and pattern manipulation is not required. The effectiveness of this technique is demonstrated on several industrial designs.

Algebraic feedback shift registers (AFSRs) [] are pseudo-random sequence generators that generalize linear feedback shift registers (LFSRs) and feedback with carry shift registers (FCSRs). With a general setting, AFSRs can result in sequences over an arbitrary finite field. It is well known that the sequences generated by LFSRs can be synthesized by either the Berlekamp-Massey algorithm or the extended Euclidean algorithm. There are three approaches to solving the synthesis problem for FCSRs, one based on the Euclidean algorithm [], one based on the theory of approximation lattices [] and Xu’s algorithm which is also used for some AFSRs []. Xu’s algorithm, an analog of the Berlekamp-Massey algorithm, was proposed by Xu and Klapper to solve the AFSR synthesis problem. In this paper we describe an approximation algorithm that solves the AFSR synthesis problem based on low-dimensional lattice basis reduction []. It works for AFSRs over quadratic integer rings \(\mathbb {Z}[\sqrt{D}]\) with quadratic time complexity. Given the first \(2\varphi _\pi (\mathbf {a})+c\) elements of a sequence \(\mathbf {a}\), it finds the smallest AFSR that generates \(\mathbf {a}\), where \(\varphi _\pi (\mathbf {a})\) is the \(\pi \)-adic complexity of \(\mathbf {a}\) and \(c\) is a constant.

This paper presents a new scheme of Linear-Feedback Shift-Register (LFSR) reseeding technique based on Berlekamp-Massey Algorithm (BMA). It is proposed an LFSR-based TPG which its feedback polynomial is programmable by a BMA-synthesized LFSR that, in its turn, generates specific patterns to change the LFSR-based TPG's feedback polynomial. Using the proposed method, high fault coverage is achieved with a small number of test patterns. Experimental results have been shown the effectively of the proposed method.

The test pattern generator produces test vectors that are applied to the tested circuit during pseudo-random testing of combinational circuits. The nature of the generator thus directly influences the fault coverage achieved. In this paper we discuss the influence of the type of pseudo-random pattern generator on stuck-at fault coverage. Linear feedback shift registers (LFSRs) are mostly used as test pattern generators, and the generating polynomial is primitive to ensure the maximum period. We have shown that it is not necessary to use primitive polynomials, and moreover that their using is even undesirable in most cases. This fact is documented by statistical graphs. The necessity of the proper choice of a generating polynomial and an LFSR seed is shown here, by designing a mixed-mode BIST for the ISCAS benchmarks.An alternative to LFSRs are cellular automata (CA). We study the effectiveness of CA when used as pseudo-random pattern generators. The observations are documented by statistical results.

To obtain satisfactory fault coverage for testing a logic circuit, linear feedback shift registers (LFSRs) have been used to generate not only the pseudorandom, but also the deterministic patterns in the scan-based built-in self-test environment. However, like other scan-based methods, the LFSR based pattern generation schemes take a long test application time to feed deterministic patterns from the LFSR into a scan chain. In this paper we derive a general relationship between the bits in the scan chain and the states of the LFSR and show that any bit to be generated by an LFSR in any future clock cycle can be pre-generated by a linear function of the current LFSR state. With this relationship, we can divide a scan chain into multiple sub-chains and use one LFSR-based multiple sequence generator to simultaneously generate all the subsequences required by the sub-chains, hence can greatly reduce the test application time for deterministic patterns. Moreover, due to the scan time reduction, test power wasted during the scan operation can also be significantly reduced.

During testing, the power dissipation is more than normal working. Among many reasons, one reason is due to a lot of transitions occur between bits of test patterns generated. The work advised here has a low power pattern generator for a built-in-self-test (BIST) design. The proposed design is a low power, improved version of a conventional linear feedback shift register (LFSR). The proposed designed named half-start-half-stop pattern generator (2HS-PG) is comprised of conventional LFSR, redesigned with add-on circuitry which brings down the total number of switching between the bits, results in low switching power during testing. Implementation of both conventional LFSR and 2HS-PG design are done in Cadence Genus tool, using 90 nm standard cell technology library and simulation is done in Xilinx ISE tool. Simulation result and analysis shows that more than 30% dynamic power reduction, when patterns are generated using proposed pattern generator.KeywordsBISTLFSRBit-swapping lFSR (BS-LFSR)Pseudo random pattern generator (PRPG)Low power pattern generator

The testing of System on Chip (SoC) components in Very-Large-Scale Integrated Circuits (VLSI) presents significant challenges due to excessive power dissipation and data volume. The inherent complexity of VLSI circuits, which integrate numerous transistors on a single silicon substrate, increases fault likelihood, leading to large data volumes and longer test times. The conventional scan chain-based testing in Design-for-Testability (DFT), result in high switching activity and power consumption, especially during shift operations. Addressing low power dissipation during testing is essential for chip durability, performance, cost, and reliability. Otherwise, the chip may foresee power surge, voltage drops, hotspots, thermal stress, false timing failures and mismatches due to the reason that test power is always double than the Functional power. Thus, in this paper, a new architecture based on Linear-Feedback Shift-Register (LFSRs) driven architecture that is analogous to that of the traditional scan is proposed, to help diminish transition count in turn decreasing power usage in the testmode. The architecture employs Power gating and Automatic test pattern generation (ATPG) filling methods in the contribution of ensuring the design is in a low power state that provides a high level of test coverage at the lowest switching activity. The experimentation is tested on ISCAS89 benchmarking circuits, and on hyper convoluted industrial designs with Cadence Genus and Modus tools. Scalability between small benchmark circuits and large industrial designs is confirmed by performance analysis of a wide range of circuit complexities. Experimental data demonstrates that LFSR-based method showed a significant 1.34X decrease in the toggling activity, as well as impressive 4-10K decreasing pattern and an overall acceleration of the runtime of approximately 1-1.5 hours over the scan-based designs. Test coverage is enhanced 2.97-3.76 with the case of the static test, 6.03-7.51 with the case of the delay test and 0.41-0.59 with the case of scan tests. Test power recorded a decline of about 40-47 on industrial design exhibiting its substantial findings on intricate designs.

This work proposes automatic test pattern generation (ATPG) for Null Convention Logic (NCL). NCL is a robust asynchronous paradigm that introduces new challenges to test and testability algorithms due to the lack of a clock signal and the presence of a large number of state holding elements. The main features of this work are clockless, self-timed ATPG for all single stuck-at faults in NCL circuits, including those of gate internal feedback (GIF). The detection of faults on GIF is performed with no added test hardware. To the extent of our knowledge, this is the first work which has addressed clockless, self-timed ATPG with coverage for faults on GIF of NCL gates and with no area overhead. The proposed test generation algorithms are evaluated for several real-size NCL circuits with average 96.2% fault coverage.

In this paper we describe an optimized BIST scheme based on reseeding of multiple polynomial Linear Feedback Shift Registers (LFSRs). The same LFSR that is used to generate pseudo-random patterns, is loaded with seeds from which it produces vectors that cover the testcubes of difficult to test faults. The scheme is compatible with scandesign and achieves full coverage as it is based on random patterns combined with a deterministic test set. A method for processing the test s et to allow for efficient encoding by the .scheme is described. Algorithms for Calculating LFSR seeds from the test set and for the selection and ordering of polynomials are described. Experimental results are provided for ISCAS-89 benchmark circuits to demonstrate the effectiveness of the scheme. The scheme allows an excellent trade-off between test data storage and test application time (number of test patterns) with a very small hardware overhead. We show the trade-off between test data storage and number of test patterns under the scheme.