BMA-based reseeding technique

When using built-in self-test (BIST) for testing VLSI circuits the circuit response to an input test sequence, which may consist of thousands to millions of bits, is compacted into a signature which consists of only tens of bits. Usually a linear feedback shift register (LFSR) is used for response compaction via polynomial division. The compacting function is a many-to-one function and as a result some erroneous responses may be mapped to the same signature as the good response. This is known as aliasing. In this paper we deal with the selection of a feedback polynomial for the compacting LFSR, such that an erroneous response resulting from any modeled fault is mapped to a signature that is different from that for the good response. Such LFSRs are called zero-aliasing LFSRs. Only zero-aliasing LFSRs with primitive or irreducible feedback polynomials are considered due to their suitability for BIST test pattern generation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Safety-critical technology rests on optimised and effective testing techniques for every embedded system involved in the equipment. Pattern generator (PG) such as linear feedback shift register (LFSR) is used for fault detection and useful for reliability and online test. This study presents an analysis of the LFSR, using a known automatic test PG (ATPG) test set. Two techniques are undertaken to target difficult-to-detect faults with their respective trade-off analysis. This is achieved using Berlekamp-Massey (BM) algorithm with optimisations to reduce area overhead. The first technique (concatenated) combines all test sets generating a single polynomial that covers complete ATPG set (baseline-C). Improvements are found in Algorithm 1 reducing polynomial size through Xs assignment. The second technique uses non-concatenated test sets and provides a group of LFSRs using BM without including any optimisation (baseline-N). This algorithm is further optimised by selecting full mapping and independent polynomial expressions. Results are generated using 32 benchmarks and 65 nm technology. The concatenated technique provides reductions on area overhead for 90.6% cases with a best case of 57 and 39% means. The remaining 9.4% of cases, non-concatenated technique provides the best reduction of 37 with 1.4% means, whilst achieving 100% test mapping in both cases.

Assuming a stuck-at type fault, the authors discuss current testing for CMOS logic circuits where the random patterns generated by a linear feedback shift register (LFSR) are applied, and a dynamic power supply current is monitored. The LFSR is modified such that there exists a feedback from the outputs of a circuit under test to the LSFR. This modification is intended for amplifying the effect of a fault near a primary output on the dynamic current. In order to distinguish the dynamic current of a faulty circuit from the one of a fault-free circuit, two methods are discussed. One is the method where the waveform of the dynamic current is recognized using a neural network, and the other is the method where the mean dynamic current is calculated. Simulation results show that a high fault coverage can be obtained using a small number of test vectors. >

Algebraic feedback shift registers (AFSRs) [] are pseudo-random sequence generators that generalize linear feedback shift registers (LFSRs) and feedback with carry shift registers (FCSRs). With a general setting, AFSRs can result in sequences over an arbitrary finite field. It is well known that the sequences generated by LFSRs can be synthesized by either the Berlekamp-Massey algorithm or the extended Euclidean algorithm. There are three approaches to solving the synthesis problem for FCSRs, one based on the Euclidean algorithm [], one based on the theory of approximation lattices [] and Xu’s algorithm which is also used for some AFSRs []. Xu’s algorithm, an analog of the Berlekamp-Massey algorithm, was proposed by Xu and Klapper to solve the AFSR synthesis problem. In this paper we describe an approximation algorithm that solves the AFSR synthesis problem based on low-dimensional lattice basis reduction []. It works for AFSRs over quadratic integer rings \(\mathbb {Z}[\sqrt{D}]\) with quadratic time complexity. Given the first \(2\varphi _\pi (\mathbf {a})+c\) elements of a sequence \(\mathbf {a}\), it finds the smallest AFSR that generates \(\mathbf {a}\), where \(\varphi _\pi (\mathbf {a})\) is the \(\pi \)-adic complexity of \(\mathbf {a}\) and \(c\) is a constant.

Testing for delay and CMOS stuck-open faults requires two pattern tests and test sets are usually large. Built-in self-test (BIST) schemes are attractive for such comprehensive testing. The BIST test pattern generators (TPGs) for such testing should be designed to ensure high pattern-pair coverage. In this paper, necessary and sufficient conditions to ensure complete/maximal pattern-pair coverage for linear feedback shift register (LFSR) and cellular automata (CA) have been derived. The theory developed here identifies all LFSR/CA TPGs which maximize pattern-pair coverage under any given TPG size constraints. It is shown that LFSRs with primitive feedback polynomials with large number of terms are better for two-pattern testing. Also, CA are shown to be better TPGs than LFSRs for two-pattern testing. Results derived in this paper provide practical algorithms for the design of optimal TPGs for two-pattern testing. Experiments on some benchmark circuits indicate the TPGs designed using the procedures outlined in this paper provide much higher delay fault coverage than other TPGs. >

The author has proposed an improvement of the Berlekamp–Massey method when used for searching periodicities in bitstreams with errors. The essence of the improvement is another splitting of а bitstream into blocks, using a consistent bit shift before every parameter processing, and making decisions about the register’s length and feedback polynomial based on proposed mathematical formulas. Keywords: linear feedback shift register, register length, feedback polynomial, bitstream, Berlekamp–Massey method.

Although conventional global navigation satellite systems (GNSS) receivers were originally designed for single signals, studies on multi-signal receiver design have recently been actively conducted to achieve high accuracy, precision, and reliability. However, in order for a multi-signal receiver to support various codes, the receiver should support the generation of individual codes. Therefore, the resulting problem of increased complexity must be solved. This paper proposes a hardware structure for an area-efficient linear feedback shift register (LFSR)-based multi-frequency universal code generator. Whereas the existing universal code generators were configured so that feedback polynomials, output registers, and initial values can be selected by placing read-only memories (ROMs), multiplexers (MUXs), and exclusive ORs (XORs) by register bit, in the case of the proposed universal code generator; the circuit was implemented by applying the hardwiring technique to those register bits that have fixed values. According to the results of field programmable gate array (FPGA) implementation, the proposed LFSR-based universal code generator can improve look up table (LUT) by up to 37% and register by up to 78% when compared to conventional code generators, and LUT by up to 36% when compared to the previous universal code generator. Therefore, the proposed universal code generator is a good candidate for implementing multi-frequency receivers to achieve high precision and high reliability.

This paper presents a novel test point insertion method for pseudo-random built -in self-test (BIST) to reduce the area overhead. R ecently, a new test point insertion method for BIST was proposed which tries to use functional flip -flops to drive control test points instead of adding extra dedicated flip - flops for driving the control points. Replacement rule used in the previous work has limitations preventing some dedicated flip-flops from being replaced by functional flip -flops. This paper proposes a logic cone analysis based test point insertion approach to overcome the limitations. Logic cone analysis is performed to find candida te functional flop -flops for replacing dedicated flip -flops. Experimental results indicate that the proposed method reduces test point area overhead significantly with minimal loss of testability by replacing the dedicated flip - flops. application to the inputs of the circuit -under-test (CUT). The output response analyzer compacts the output response of the CUT into a signature. T his provides a variety of benefits including the ability to apply a large number of test patterns in a short time (i.e., shorter test time) , at-speed testing, minimal automatic test equipment (ATE) storage requirements, test application in the field over t he lifetime of the part, and a reusable test solution for embedded cores. In particular, BIST is crucial for applications such as aerospace, defense, automotive, computer, etc., for the reliability of the entire system. The most economical logic BIST te chniques are based on pseudo-random pattern testing. On -chip input pattern generator constructed from a linear feedback shift register (LFSR) is most commonly used to generate pseudo -random patterns with its compact structure. And on -chip output response analyzer compacts the output responses into a signature and this allows significant compaction of test data. Pseudo-random pattern testing also can achieve high coverage of non-modeled faults which are not explicitly targeted during deterministic test ge neration. However, a major challenge is the presence of random -pattern-resistant (r.p.r.) faults which have low detection probabilities and hence may limit the fault coverage that can be achieved with pseudo -random patterns. There have been many research efforts to overcome the fault coverage limitation by r.p.r faults. Mainly two directions are given to enhance the fault coverage. One is to modify the pattern generator in order to generate patterns that detect hard faults. Various methods have been pr oposed such as weighted pattern generation ( 2), (4)-(8), pattern mapping ( 9)- (11), bit-fixing (12), bit-flipping (13), and LFSR reseeding (14)-(19).

Random number generator (RNG) is a fundamental element in modern cryptography. If the quality of the outputs generated by RNGs is not as well as expected, the cryptographic applications which use the random number service are vulnerable to security threats. In reality, the entropy source of RNGs could be impressible by the changes of environmental factors, resulting in defects in the generated data, such as poor statistical properties. Thus, RNG is generally designed with a preset post-processing module to improve the quality of the output sequences. Linear feedback shift register (LFSR) is one of the frequently used methods for post-processing thanks to the characteristic of simplicity and no reduction in output throughput. However, we point out that even if the statistical properties of the outputs of the entropy source are extremely poor, the sequences processed by LFSR can still pass the statistical test. This undoubtedly increases the security risks in the usage of RNGs. In this work, we propose a distinguisher for the RNGs with LFSR post-processing for the first time. The distinguisher can be used to detect the RNGs with LFSR post processing, and we theoretically prove the sequences before processing can be recovered. On this basis, we design a new statistical test via combining the distinguisher with the Frequency Test in the NIST test suite. The experimental results show that if the sequence is biased before being processed by LFSR, our proposed method can detect it, but the NIST SP 800-22 Test Suite cannot.KeywordsRandom number generatorLFSRPost-processingDistinguisherRandomness test

In this paper we describe an optimized BIST scheme based on reseeding of multiple polynomial Linear Feedback Shift Registers (LFSRs). The same LFSR that is used to generate pseudo-random patterns, is loaded with seeds from which it produces vectors that cover the testcubes of difficult to test faults. The scheme is compatible with scandesign and achieves full coverage as it is based on random patterns combined with a deterministic test set. A method for processing the test s et to allow for efficient encoding by the .scheme is described. Algorithms for Calculating LFSR seeds from the test set and for the selection and ordering of polynomials are described. Experimental results are provided for ISCAS-89 benchmark circuits to demonstrate the effectiveness of the scheme. The scheme allows an excellent trade-off between test data storage and test application time (number of test patterns) with a very small hardware overhead. We show the trade-off between test data storage and number of test patterns under the scheme.

Many Built-in Self Test (BIST) pattern generators use Linear Feedback Shift Registers (LFSR) to generate test sequences. In this paper, we address the generation of deterministic pairs of patterns for delay faults testing with LFSRs. A new synthesis procedure for a n-size LFSR is given and guarantees that a deterministic set of n precomputed test pairs is embedded in the maximal length pseudo-random test sequence of the LFSR. Sufficient and necessary conditions for the synthesis of this pseudo-deterministic LFSR are provided and show that at-speed delay faults testing becomes a reality without any additional cost for the LFSR. Moreover, since the theoretical properties of LFSRs are preserved, our method could be beneficially used in conjunction with any other technique proposed so far.

To obtain satisfactory fault coverage for testing a logic circuit, linear feedback shift registers (LFSRs) have been used to generate not only the pseudorandom, but also the deterministic patterns in the scan-based built-in self-test environment. However, like other scan-based methods, the LFSR based pattern generation schemes take a long test application time to feed deterministic patterns from the LFSR into a scan chain. In this paper we derive a general relationship between the bits in the scan chain and the states of the LFSR and show that any bit to be generated by an LFSR in any future clock cycle can be pre-generated by a linear function of the current LFSR state. With this relationship, we can divide a scan chain into multiple sub-chains and use one LFSR-based multiple sequence generator to simultaneously generate all the subsequences required by the sub-chains, hence can greatly reduce the test application time for deterministic patterns. Moreover, due to the scan time reduction, test power wasted during the scan operation can also be significantly reduced.

Due to the increasing use of portable computing and wireless communications systems, energy consumption is of major concern in today's VLSI circuits. With that in mind we present an energy conscious weighted random pattern testing technique for Built-In-Self-Test (BIST) applications. Energy consumption during BIST operation can be minimized while achieving high fault coverage. Simple measures of observability and controllability of circuit nodes are proposed based on primary input signal probability (probability that a signal is logic ONE). Such measures help determine the testability of a circuit. We developed a tool, POWERTEST, which uses a genetic algorithm based search to determine optimal weight sets (signal probabilities or input signal distribution) at primary inputs to minimize energy dissipations. The inputs conforming to the primary input weight set can be generated using cellular automata or LFSR (Linear Feedback Shift Register). We observed that a single input distribution (or weights) may not be sufficient for some random-pattern resistant circuits, while multiple distributions consume larger area. As a trade-off, two distributions have been used in our analysis. Results on ISCAS benchmark circuits show that energy reduction of up to 97.82% can be achieved (compared to equi-probable random-pattern testing with identical fault coverage) while achieving high fault coverage.

This paper presents a smoothing technique for the output sequence of linear feedback shift registers (LFSR) to reduce power consumption in test-per-scan built-in self-test (BIST) applications. The proposed smoother is implemented by adding one multiplexer between the LFSR and scan-chain input of a single scan-chain. The size of the multiplexer is determined the desired smoothing degree. When the smoothed sequence of the LFSR is used to feed the test patterns in test-per-scan BIST, it reduces the number of transitions that occur at scan-chain input during scan shift operations by 25% to 50% depending on the smoothing degree, and hence reduces switching activity in the circuit-under-test (CUT) during test application. The proposed technique can be extended to multiple scan-chains BIST, also to test-per-clock applications. Various properties of the proposed technique and the methodology of the design are presented in this paper. Experimental results for the ISCAS'89 benchmark circuits show that the proposed design can reduce the switching activity up to 55% with a negligible effect on the fault coverage and test application time.

A low-overhead scheme for achieving complete (100%) fault coverage during built-in self test of circuits with scan is presented. It does not require modifying the function logic and does not degrade system performance (beyond using scan). Deterministic test cubes that detect the random-pattern-resistant (r.p.r.) faults are embedded in a pseudorandom sequence of bits generated by a linear feedback shift register (LFSR). This is accomplished by altering the pseudorandom sequence by adding logic at the LFSR's serial output to fix certain bits. A procedure for synthesizing the bit-fixing logic for embedding the test cubes is described. Experimental results indicate that complete fault coverage can be obtained with low hardware overhead. Further reduction in overhead is possible by using a special correlating automatic test pattern generation procedure that is described for finding test cubes for the r.p.r. faults in a way that maximizes bitwise correlation.