Zero-aliasing for modeled faults

Testing for delay and CMOS stuck-open faults requires two pattern tests and test sets are usually large. Built-in self-test (BIST) schemes are attractive for such comprehensive testing. The BIST test pattern generators (TPGs) for such testing should be designed to ensure high pattern-pair coverage. In this paper, necessary and sufficient conditions to ensure complete/maximal pattern-pair coverage for linear feedback shift register (LFSR) and cellular automata (CA) have been derived. The theory developed here identifies all LFSR/CA TPGs which maximize pattern-pair coverage under any given TPG size constraints. It is shown that LFSRs with primitive feedback polynomials with large number of terms are better for two-pattern testing. Also, CA are shown to be better TPGs than LFSRs for two-pattern testing. Results derived in this paper provide practical algorithms for the design of optimal TPGs for two-pattern testing. Experiments on some benchmark circuits indicate the TPGs designed using the procedures outlined in this paper provide much higher delay fault coverage than other TPGs. >

Many Built-in Self Test (BIST) pattern generators use Linear Feedback Shift Registers (LFSR) to generate test sequences. In this paper, we address the generation of deterministic pairs of patterns for delay faults testing with LFSRs. A new synthesis procedure for a n-size LFSR is given and guarantees that a deterministic set of n precomputed test pairs is embedded in the maximal length pseudo-random test sequence of the LFSR. Sufficient and necessary conditions for the synthesis of this pseudo-deterministic LFSR are provided and show that at-speed delay faults testing becomes a reality without any additional cost for the LFSR. Moreover, since the theoretical properties of LFSRs are preserved, our method could be beneficially used in conjunction with any other technique proposed so far.

Linear Feedback Shift Register (LFSRs) based pseudo-random number generators (PRNGs) are used in test pattern generators (TPGs). Because FPGAs are reprogrammable, you can implement designs of LFSR on FPGA and simulate different lengths. It is important to test and validate the simulated results and synthesis results. The primitive polynomial determines the total number of pseudo-random output states of LFSRs. If the polynomial used is a primitive, the output random state is up to 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> - 1 state. This paper presented the designed, developed, and implemented 4, 8, 16, and 32 bit reversible LFSRs in FPGAs by performing, analyzing, and investigating random behavior using the Verilog HDL code. The analysis is performed to find the design speed requirements in FPGA when the number of constant inputs, the number of garbage outputs, the number of reversible logic gates, and the increased number of bits. In this paper, shows a comparative study of 4, 8, 16, and 32 bit reversible LFSRs on FPGAs to understand their performance. According to the results, the proposed reversible LFSR design using the Pareek gate approach reduces power by 10% when compared to the irreversible approach. As a result, the proposed design is used to develop Built-In-Self-Test (BIST) module.

This paper presents a smoothing technique for the output sequence of linear feedback shift registers (LFSR) to reduce power consumption in test-per-scan built-in self-test (BIST) applications. The proposed smoother is implemented by adding one multiplexer between the LFSR and scan-chain input of a single scan-chain. The size of the multiplexer is determined the desired smoothing degree. When the smoothed sequence of the LFSR is used to feed the test patterns in test-per-scan BIST, it reduces the number of transitions that occur at scan-chain input during scan shift operations by 25% to 50% depending on the smoothing degree, and hence reduces switching activity in the circuit-under-test (CUT) during test application. The proposed technique can be extended to multiple scan-chains BIST, also to test-per-clock applications. Various properties of the proposed technique and the methodology of the design are presented in this paper. Experimental results for the ISCAS'89 benchmark circuits show that the proposed design can reduce the switching activity up to 55% with a negligible effect on the fault coverage and test application time.

When using Built-In Self Test (BIST) for testing VLSI circuits, a major concern is the generation of proper test patterns that detect the faults of interest. Usually a linear feedback shift register (LFSR) is used to generate test patterns. We first analyze the probability that an arbitrary pseudo-random test sequence of short length detects all faults. The term short is relative to the probability of detecting the fault having the fewest test patterns. We then show how to guide the search for an initial state (seed) for a LFSR with a given primitive feedback polynomial so that all the faults of interest are detected by a minimum length test sequence. Our algorithm is based on finding the location of test patterns in the sequence generated by this LPSR. This is accomplished using, the theory of discrete logarithms. We then select the shortest subsequence that includes test patterns for all the faults of interest, hence resulting in 100% fault coverage. >

We present a novel approach for built-in self test (BIST) for VLSI. Many conventional BIST schemes use signatures generated by a linear feedback shift register (LFSR) or a multiple input signature register (MISR) for determining whether the device under test is faulty or fault free. In the approach presented, fault detection is made based on the number of different states the LFSR visits. This number is called the cycle length. It is also shown that such an approach results in the probability of aliasing of 2/sup -(2m-1+m/), where m denotes the number of registers in the LFSR, compared to 2/sup -m/ achieved by conventional signature analyzers. We also present the complexity of the additional hardware required to implement the scheme.

This paper presents a novel test point insertion method for pseudo-random built -in self-test (BIST) to reduce the area overhead. R ecently, a new test point insertion method for BIST was proposed which tries to use functional flip -flops to drive control test points instead of adding extra dedicated flip - flops for driving the control points. Replacement rule used in the previous work has limitations preventing some dedicated flip-flops from being replaced by functional flip -flops. This paper proposes a logic cone analysis based test point insertion approach to overcome the limitations. Logic cone analysis is performed to find candida te functional flop -flops for replacing dedicated flip -flops. Experimental results indicate that the proposed method reduces test point area overhead significantly with minimal loss of testability by replacing the dedicated flip - flops. application to the inputs of the circuit -under-test (CUT). The output response analyzer compacts the output response of the CUT into a signature. T his provides a variety of benefits including the ability to apply a large number of test patterns in a short time (i.e., shorter test time) , at-speed testing, minimal automatic test equipment (ATE) storage requirements, test application in the field over t he lifetime of the part, and a reusable test solution for embedded cores. In particular, BIST is crucial for applications such as aerospace, defense, automotive, computer, etc., for the reliability of the entire system. The most economical logic BIST te chniques are based on pseudo-random pattern testing. On -chip input pattern generator constructed from a linear feedback shift register (LFSR) is most commonly used to generate pseudo -random patterns with its compact structure. And on -chip output response analyzer compacts the output responses into a signature and this allows significant compaction of test data. Pseudo-random pattern testing also can achieve high coverage of non-modeled faults which are not explicitly targeted during deterministic test ge neration. However, a major challenge is the presence of random -pattern-resistant (r.p.r.) faults which have low detection probabilities and hence may limit the fault coverage that can be achieved with pseudo -random patterns. There have been many research efforts to overcome the fault coverage limitation by r.p.r faults. Mainly two directions are given to enhance the fault coverage. One is to modify the pattern generator in order to generate patterns that detect hard faults. Various methods have been pr oposed such as weighted pattern generation ( 2), (4)-(8), pattern mapping ( 9)- (11), bit-fixing (12), bit-flipping (13), and LFSR reseeding (14)-(19).

This paper proposes a low power efficient Built in Self Test (BIST) with Test Pattern Generation (TPG) technique, which reduces power dissipation during testing. In general, the correlations between the consecutive test patterns are higher during normal mode than during testing mode. The proposed approach uses the concept of reducing the transitions in the test patterns generated by conventional Linear Feedback Shift Register (LFSR) . The transitions are reduced by increasing the correlation between the successive bits in the test pattern, which is done with the help of modified LFSR. This approach eliminates the need for an external tester. The simulation result shows that the power dissipated during testing is reduced in modified LFSR than in conventional LFSR.

The test pattern generator produces test vectors that are applied to the tested circuit during pseudo-random testing of combinational circuits. The nature of the generator thus directly influences the fault coverage achieved. In this paper we discuss the influence of the type of pseudo-random pattern generator on stuck-at fault coverage. Linear feedback shift registers (LFSRs) are mostly used as test pattern generators, and the generating polynomial is primitive to ensure the maximum period. We have shown that it is not necessary to use primitive polynomials, and moreover that their using is even undesirable in most cases. This fact is documented by statistical graphs. The necessity of the proper choice of a generating polynomial and an LFSR seed is shown here, by designing a mixed-mode BIST for the ISCAS benchmarks.An alternative to LFSRs are cellular automata (CA). We study the effectiveness of CA when used as pseudo-random pattern generators. The observations are documented by statistical results.

It is shown how to construct a general linear hybrid cellular automaton (CA) such that it has a maximum length cycle, and how the aliasing properties of such automata compare with linear feedback shift registers (LFSRs) when used as signature analyzers. The construction is accomplished by formally demonstrating the isomorphism which binds this kind of CA to the LFSRs. Consequently, these CAs can be analyzed as linear machines. Linear algebraic techniques are then applied appropriately for the transformations, and a useful search algorithm is developed which, given an irreducible characteristic polynomial, finds a corresponding linear hybrid automaton. Such CAs are tabulated for all irreducible and primitive polynomials up to degree 16, plus a selection of others of higher degree. The behavior of a linear hybrid CA and that of its corresponding LFSR are similar-that is, they have the same cycle structure and only relabel the states. The aliasing properties, when they are used as signature analyzers, remain unchanged.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The objective involves in construction of a Logical Built in Self Test using adaptive Multiple Input Signature Register designs that is mainly used for testing of the Integrated Circuits. One of the major issues is that, the complications in integrated circuit testing have been increased due to the emerging trends in the field of Very Large Scale Integration. This problem could be solved by increasing the usage of test equipment named Logical Built in Self Test shortly called as LBIST which works much well than any other test equipments. The logical BIST also has the advantage of performing a test that is in-built to the chip by means of an extra element that is present interior to the design. Test patterns for the operation are generated always by an inbuilt testing circuit as mentioned earlier. The output responses are determined with the help of a Multiple Input Signature Register, which is the most widely as the design is completely opposite to that of a Linear Feedback Shift Register design. The testing methodology is always invoked by a MISR by means of compressing multiple sequences of input bits as a single package named as signature of the design. The fault performance during a chip testing can be improved by means of a reconstructable Linear Feedback Shift Register which functions both to generate test patterns as well as to compress the responses required for logical Built in Self Testing. The QUCS simulator and SPICE tool is used to perform compilation of fast Multiple Input Signature Register design. Four structural representations namely Basic, Combined, Programmable and Advanced MISR are implemented and simulated using QUCS simulator and SPICE tool in 22nm technology. The output waveforms of the adaptive designs are obtained for different temperature variations ranging from 27°C to 107°C.

In this paper, a 4-bit Linear Feedback Shift Register (LFSR) is implemented based on a well-designed architecture combining using Pass-Transistor (PT) and Clock Complementary Metal Oxide Semiconductor (C2MOS) logic techniques. The D-flip flop registers and the XOR gates are the main parts of the propose LFSR. Number of transistors along with the speed of LFSR were positively enhanced since the exploited logic design techniques tends to blend the flavor of NMOS and PMOS devices. The PSpice and Field Programmable Gate Array (FPGA) based on Hardware Description Language (HDL) are the two different LFSR implementation environments. It has been observed that LFSR performance was effectively improved in terms of size and speed. Therefore, paper’s main aim refers to decreasing in number of transistors as well as speeding up LFSR circuit. A minimum clock time of 5ns was recorded under clearly correct LFSR output patterns. The LFSR circuit Based CMOS techniques can reduce the exploited transistors up to 43% of the conventional C2MOS logic. Besides, the number of transistors being reduced reflects the achieved circuit’s size reduction. It was concluded that paying attention to the design of the main LFSR circuit parts contributes mainly in the enhancement of the whole circuit performance.

To obtain satisfactory fault coverage for testing a logic circuit, linear feedback shift registers (LFSRs) have been used to generate not only the pseudorandom, but also the deterministic patterns in the scan-based built-in self-test environment. However, like other scan-based methods, the LFSR based pattern generation schemes take a long test application time to feed deterministic patterns from the LFSR into a scan chain. In this paper we derive a general relationship between the bits in the scan chain and the states of the LFSR and show that any bit to be generated by an LFSR in any future clock cycle can be pre-generated by a linear function of the current LFSR state. With this relationship, we can divide a scan chain into multiple sub-chains and use one LFSR-based multiple sequence generator to simultaneously generate all the subsequences required by the sub-chains, hence can greatly reduce the test application time for deterministic patterns. Moreover, due to the scan time reduction, test power wasted during the scan operation can also be significantly reduced.

The technique of Test Sequence Generation (TSG) plays a key role in Built-In Self-Test (BIST) architecture implementation. Major problem with any test sequence generator is to produce long, unpredictable key sequences which can be applied to Circuit Under Test (CUT) in order to detect the faults efficiently. Digital Systems/Circuits are tested by inducing appropriate stimuli and checking the responses generated. Generation of such stimuli together with calculation of their anticipated responses is called Test Sequence Generation or Test Pattern Generation. Due to certain limitations of Automatic Test Equipment (ATE), there exist methods where the main functions of the external tester have been moved onto the chip, Such DFT practice is generally known as BIST. With the progression of test technology, various techniques have been developed for IC testing. This paper presents three techniques: Cellular Automata (CA), Linear Feedback Shift Register (LFSR), and Single Bit Change Sequence Generator (SBCSG), used for test pattern generation and test response analysis in a typical BIST circuit. All the three TPGs are analyzed with respect to the parameters like Power, Time and Area to demonstrate their shortfalls and suitability for intended application.

Linear feedback shift register (LFSR) is an important part of sequence cipher. In this paper, we introduce a kind of reconfigurable LFSR design. According to need, it can be configured to be a random LFSR to run over GF (2), GF (2^8) ,GF (2^16)or GF (2^32) in a certain length range. The prototype of the reconfigurable LFSR has been implemented in Altera's EP2S60F1020C5 FPGA and its highest run clock is 100MHZ. It is proved by experiment that the reconfigurable LFSR design uses few hardware resources and its performance is stable.