Three-dimensional integrated circuits design

Over the past two decades, 3D techniques combined with heterogeneous integration, combining different functions and materials, have emerged as a key enabler for overcoming the physical and scaling limits of traditional 2D integration. These approaches are now expanding across multiple domains, including CMOS, memories, photonics, imagers, and RF systems, with the aim of delivering next-generation integrated systems for advanced computing (AI), analog/RF, and imaging applications. In this presentation, we will explore the fundamental techniques, recent advancements, and some challenges associated with achieving integration. Special emphasis will be placed on the role of hybrid bonding and sequential 3D integration schemes, as well as their implications for energy efficiency, device performance, and system-level innovations.3D integration has transitioned from a niche research area to a cornerstone technology in microelectronics, driven by its potential to address high density interconnect and traditional 2D scaling bottlenecks for several applications and enable heterogeneous integration at unprecedented scales. At the heart of this technological evolution are advanced schemes such as wafer thinning, Through-Silicon Vias (TSVs), hybrid bonding, and sequential 3D integration techniques. These techniques have been pivotal in shrinking the interconnect length, reducing latency, and enhancing data bandwidth in computing systems. In parallel, developments in wafer-to-wafer, die-to-wafer, and chiplet integration are enabling the seamless merging of diverse materials enabling functionalities such as logic, memory, photonics, and RF. Compact form factors are achieved enabling to boost performances of the most demanding applications such as Artificial Intelligence or Tb/s transceiver applications [1].Recent studies highlight significant progress in hybrid bonding technology, which achieves high-density interconnects at the submicron scale, thereby optimizing power delivery and thermal management in stacked devices [2]. Meanwhile, sequential 3D integration [3][4] where layers of transistors are fabricated sequentially on the same substrate, is emerging as a game-changing paradigm. It promises ultra-high-density integration with minimal parasitics, creating new opportunities for energy-efficient and high-performance systems. Several applications are foreseen including C-FETS, memories and imagers [5] .Photonic interconnects will enter in next generation 3D IC integration, addressing challenges in data bandwidth, power consumption and signal integrity and enabling photonic interposers for next generation of components for data centers and communication systems [7]. Similarly, RF [8] and analog domains [9] benefit from 3D stacking by improving front-end module integration with specific materials (III-V, HR, ...), leading to enhanced performance and higher frequencies.Despite these achievements, significant challenges remain. Thermal dissipation is a critical bottleneck [10] , particularly in densely 3D stacked architectures where hotspots can severely impact reliability and performance. Moreover, the mechanical stresses induced during bonding and processing can affect device yield and long-term stability. Our recent work in advanced thermal management and stress engineering underscores the need for interdisciplinary approaches to address these challenges. Solutions such as microfluidic cooling, novel materials for thermal interface layers and specific bonding technologies are being actively explored. Furthermore, while heterogeneous integration is currently feasible at the wafer scale—such as wafer-to-wafer hybrid bonding, which is already in mass production—expanding application fields will require advancements in die-to-wafer integration techniques.Looking ahead, the convergence of 3D integration with emerging paradigms such as neuromorphic computing, quantum technologies, multispectral and smart imagers, and advanced packaging promises to redefine system design at all levels. The synergy between 3D technologies and heterogeneous integration of advanced materials, such as 2D semiconductors, III-V, ferroelectric or oxide semiconductor [11] materials, further expands the horizon for innovation.In conclusion, 3D integration has proven to be a transformative force in microelectronics, offering pathways to overcome traditional limitations and unlock new performance dimensions. Intensive researches worldwide continues contribute to push the boundaries of what is possible, paving the way for smarter, more efficient, and highly integrated systems.

New semiconductor chip technologies and technologies for 3D integration require information’s of packaging and interface defects in 3 dimensions, that means the lateral dimension of the defect and the location inside the device or package must be defined. In this paper, new methodical approaches for non destructive failure analysis on 3D integrated TSV samples are introduced. The concepts combine improved scanning acoustic microscopy (SAM) imaging hardware with unique software solutions for defect identification and quantitative analysis of mechanical properties using scanning acoustic investigations. In case of MEMS 3D integration, e.g. based on direct bonding, related interface defects must be investigated by SAM. With respect to 3D integration applications, the potential of recent SAM improvements applying specifically adapted hardware and custom-made signal processing algorithms will be discussed. Examples of SAM-based failure detection techniques for the application in 3D integration are demonstrated. New technologies are shown to improve the through put of fully wafer scanning using scanning acoustic microscopy. To improve the defect resolution, a new transducer design was developed to increase defect resolution and signal to noise for interface characterisation.

Three-dimensional (3D) integration is adopted in the semiconductor industry to overcome the slowdown of Moore's Law. The 3D integration is beneficial in terms of interconnection bandwidth, wire delay, power efficiency, and area. However, the on-chip temperature of 3D stacked CPUs is known as much higher than that of conventional 2D CPUs due to the higher power density and lower heat dissipation capability. High on-chip temperature leads to performance degradation of 3D stacked CPUs due to following reasons: 1) High on-chip temperature leads to frequent Dynamic Thermal Management (DTM) invocations, which limits practical CPU voltage and clock frequency. 2) The power limits are used to proactively deal with the thermal problems from high on-chip temperature by adjusting the CPU clock frequency. In this paper, we explore the thermal characteristics of the first off-the-shelf through-silicon-via (TSV) based 3D stacked CPU (Intel Lakefield). In our evaluation, 3D CPU w/ the forced air cooling w/o PL1 shows 21.7% and 6% better single thread performance, on average, compared to 3D CPU w/ PL1 and 3D CPU w/o PL1, respectively. Although the 3D stacked CPU was launched to the market, we identify that the thermal problems of the 3D stacked CPU have not been fully resolved. To tackle the thermal problems of 3D stacked CPUs in the future, researchers are required to consider more innovative integration technologies, optimized DTM techniques, and advanced cooling solutions.

As Moore's law approaches its physical limits, 3D integrated circuit (3D IC) technology has emerged as a crucial way to increase chip integration density. Due to their small size, high carrier mobility, and low power consumption, carbon nanotube field‐effect transistors (CNTFETs) offer a promising way to overcome the limitations imposed by Moore's law. The evolution of ICs and 3D integration technologies for the post‐Moore era, such as chiplets and multilayer stacking are reviewed, and the potential applications and value of CNTFETs in 3D optoelectronics, memory, and monolithic 3D ICs are explored. The prospects of novel device structures like FinFETs and gate‐all‐around FETs are also discussed. CNT 3D ICs have tremendous potential for these applications, but challenges remain in material fabrication, device performance, and 3D structure design. Researchers are actively exploring solutions such as optimizing fabrication processes, developing new materials, and innovative logic design methodologies. Notably, the integration of CNTFETs with chiplet technology promises more efficient and flexible chip design and manufacturing, catering to the future demand for high‐performance, low‐power, and high‐density ICs.

Three dimensional (3D) integration offers numerous electrical advantages like shorter interconnection distances between different dies in the stack, reduced signal delay, reduced interconnect power and design flexibilities. The main enabler of 3D integration is through-silicon-vias (TSVs) and stacking of multiple dies. Irrespective of these advantages, thermal management in 3D stacks poses significant challenges for the implementation of 3D integrated circuits. Even though extensive research work has been done in understanding the thermal management in two dimensional (2D) planar circuits for the past several decades, 3D integration offers a new set of challenges in terms of thermal management, which makes it difficult to readily apply the thermal management strategies available for 2D planar circuits. Over the past decade, some work has been done in thermal analysis and management of 3D stacks but still, knowledge is scattered and a comprehensive understanding is lacking. This research work focuses on bringing together the limited work on thermal analysis and thermal management in 3D vertically integrated circuits available in the literature. A compilation and analysis of the results from investigations on thermal management in 3D stacks is presented in this review with special emphasis on experimental studies conducted on different thermal management strategies. Furthermore, 3D integration technologies, thermal management challenges, and advanced 2D thermal management solutions are discussed.

3D integration consists of 3D integrated circuit (IC) packaging, 3D Si integration, and 3D IC integration. They are different and in general the through-silicon via (TSV) separates 3D IC packaging from 3D Si/IC integrations since the latter two use TSV but 3D IC packaging does not. 3D Si integration and 3D IC integration are different. 3D IC integration stacks up the thin chips with TSV and microbump, while 3D Si integration stacks up thin wafers with TSV alone (i.e., bumpless). TSV is the heart of 3D Si/IC integrations and is the focus of this investigation. Also, the state-of-the-art, challenge, and trend of 3D integration will be presented and examined. Furthermore, supply chain readiness for high volume manufacturing (HVM) of TSVs is discussed.

3D Packaging Technologies and Applications, Latest Challenges and Supply Chain ActivitiesSemiconductor industry, for more than four decades, has rigorously followed Moore's Law in scaling down the CMOS technologies. Although several new materials and processes are being developed to address the challenges of future technology nodes, in the coming years they will be limited with respect to functionalities that future devices will require. As a consequence a clear trend of moving from CMOS to package and system architecture can be observed. Three-dimensional (3D) technology using the well-known Through Silicon Via (TSV) interconnect is one the emerging options, considered today the most advanced technology, that could enable various heterogeneous integration. 3D Integration is not limited to the CMOS scaling in itself, it is rather based on bringing more functionalities by stacking different type of devices (Logic, Memory, Analog, MEMS, Passive components) while reducing the form factor of the packaging. This functional diversification is also known as More-than-Moore. In addition, considering Known Good Die approach, each component of the 3D package could have a different manufacturer using different wafer sizes and node technology, thus bringing more complexity but also more opportunities and responsibilities to the supply chain. There are several business models identified, either using vertical integration or collaborative approach, if a dominant one will emerge or several tactics will co-exist, it is still remains a key question that will have to be answered. The supply chain interaction and key players will be addressed in this presentation, including current and future standardization needs. This is today a key for the manufacturing of advanced 3D devices. 3D integration is considered today a new paradigm for the semiconductor industry, since it will drive evolution for packages for the coming decades. Due to several advantages that TSV technology can bring, several platforms have started. 3D WLCSP, 2.5D interposers & 3DIC are the main platforms that will be studied in this paper. Market forecasts in terms of wafer starts, market revenue, segments and end-products as well as supply chain activities and major player interactions will be presented. The industry has enthusiastically been waiting for mass production of 3D ICs. Although some small level of production has already been reported, the adoption rate in high volume manufacturing (HVM) is still low due to unresolved challenges that the industry still needs to address. Process technology is not fully mature, there are still many challenges in bonding and de-bonding, testing as well as thermal management that have to be overcome. Furthermore, design tools have to be fully released to enable proper 3D integration design. Looking at the time to market it is foreseen that device such as the Hybrid Memory Cube, combining high-speed logic with multiple stacks of TSV bonded memories, will come into high volume production in 2014. This will definitely change the world of the memory market and will significantly speed up the adoption of 3D technologies. Technology roadmaps for 3D integration will also be included in the manuscript and reviewed during the presentation.

Monolithic inter-layer vias (MIVs) used in 3D integration technology are much smaller than through-silicon vias (TSVs) used in TSV-based 3D integration. Thus, monolithic 3D integration provides shorter wire length, better performance, and lower power consumption than TSV-based 3D integration. Multi-tier monolithic 3D integration stacks more than two silicon layers, thereby increasing the device density, which reduces the wire length and power consumption and improves performance further than two-tier monolithic 3D integration. Since the size of an MIV is comparable to that of a local via, the wire lengths of multi-tier gate-level monolithic 3D IC layouts are expected to be close to the ideal wire length reduction ratio, for example, 29, 42, and 50 percent for two-, three-, and four-tier designs, respectively. However, it is still unknown whether it would be possible to achieve the ideal wire length reduction ratios by multi-tier gate-level monolithic 3D integration. In this paper, we propose an efficient routing methodology to design multi-tier monolithic 3D ICs. Using the design methodology, we design two- to eight-tier gate-level monolithic 3D IC layouts and thoroughly investigate the wire length characteristics of the layouts. The simulation results show that the proposed routing methodology reduces the wire length by 12 to 53 percent compared to the 2D designs. In addition, the proposed routing methodology builds multi-tier monolithic 3D IC layouts more efficiently than a state-of-the-art methodology with comparable routed wire length.

“There's Plenty of Room at the Bottom” is the title of Richard Feynman's lecture on December 29 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sup> , 1959 to the American Physical Society at California Institute of Technology (Caltech) and is generally considered to be the very first speech about nanotechnology. Some important milestones of nanotechnology will be briefly mentioned and the emphasis is placed on the applications and outlooks of nanotechnology in electronics. “Computing Machines in the Future” is the title of the Nishina Memorial Lecture at Gakushuin University in Tokyo given by the 1965 Nobel Physics Laureate, Richard Feynman on August 9 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sup> , 1985. During the lecture, Feynman not only told us to go for 3D integration, but also taught us how to do it! In this study, 3D integration will be the focus and the emphasis is placed on 3D IC integration and their recent advances and new trends. 3D Si integration will be briefly discussed.

Semiconductor industry, for more than four decades, has rigorously followed Moore's Law in scaling down the CMOS technologies. Although several new materials and processes are being developed to address the challenges of future technology nodes, in the coming years they will be limited with respect to functionalities that future devices will require. As a consequence a clear trend of moving from CMOS to package and system architecture can be observed. Three-dimensional (3D) technology using the well-known Through Silicon Via (TSV) interconnect is one the emerging option, considered today the most advanced technology, that could enable various heterogeneous integration. Indeed such technology is not limited to the CMOS scaling in itself, it is rather based on bringing more functionalities by stacking different type of devices (Logic, Memory, Analog, MEMS, Passive component...) while reducing the form factor of the packaging. This functional diversification is also known as More-than-Moore. In addition, considering Known Good Die approach, each component of the 3D package could have a different manufacturer using different wafer sizes and node technology, thus bringing more complexity but also more opportunities and responsibilities to the supply chain. There are several business models identified, either using vertical integration or collaborative approach, if a dominant one will emerge or several tactics will co-exist, it is still remains a key question that need to be answered. The supply chain interaction and key players will be addressed in this presentation, including current and future standardization needs. This is today a key for the manufacturing of advanced 3D devices. 3D integration is considered today a new paradigm for the semiconductor industry, since it will drive evolution for packages for the coming decades. Due to several advantages that TSV technology can bring, several platforms have started. 3D WLCSP, 2.5D interposers &amp; 3DIC are the main platforms that will be studied in this paper. Market forecasts in terms of wafer starts, market revenue, segments and end-products as well as supply chain activities and major player interactions will be presented. The industry has enthusiastically been waiting for mass production of 3D ICs. Although some small level of production has already been reported, the adoption rate in high volume manufacturing (HVM) is still low due to unresolved challenges that the industry still needs to address. Process technology is not fully mature, there are still many challenges in bonding and de-bonding, testing as well as thermal management that have to be overcome. Furthermore, design tools have to be fully released to enable proper 3D integration design. Looking at the time to market it is foreseen that device such as the Hybrid Memory Cube, combining high-speed logic with a multiple stacks of TSV bonded memories, will come into high volume production in 2014. This will definitely change the world of the memory market and will significantly speed up the adoption of 3D technologies. Technology roadmaps for 3D integration will also be included in the manuscript and reviewed during the presentation.

Three-dimensional (3D) integration of electronic chips has been advocated by both industry and academia for many years. It is acknowledged as one of the most promising approaches to meet ever-increasing demands on performance, functionality, and power consumption. Furthermore, 3D integration has been shown to be most effective and efficient once large-scale integration is targeted for. However, a multitude of challenges has thus far obstructed the mainstream transition from “classical 2D chips” to such large-scale 3D chips. In this paper, we survey all popular 3D integration options available and advocate that using an interposer as system-level integration backbone would be the most practical for large-scale industrial applications and design reuse. We review major design (automation) challenges and related promising solutions for interposer-based 3D chips in particular, among the other 3D options. Thereby we outline (i) the need for a unified workflow, especially once full-custom design is considered, (ii) the current design-automation solutions and future prospects for both classical (digital) and advanced (heterogeneous) interposer stacks, (iii) the state-of-art and open challenges for testing of 3D chips, and (iv) the challenges of securing hardware in general and the prospects for large-scale and trustworthy 3D chips in particular.

Heterogeneous manycore architectures are the key to efficiently execute compute- and data-intensive applications. Through-silicon-via (TSV)-based 3D manycore system is a promising solution in this direction as it enables the integration of disparate computing cores on a single system. Recent industry trends show the viability of 3D integration in real products (e.g., Intel Lakefield SoC Architecture, the AMD Radeon R9 Fury X graphics card, and Xilinx Virtex-7 2000T/H580T, etc.). However, the achievable performance of conventional TSV-based 3D systems is ultimately bottlenecked by the horizontal wires (wires in each planar die). Moreover, current TSV 3D architectures suffer from thermal limitations. Hence, TSV-based architectures do not realize the full potential of 3D integration. Monolithic 3D (M3D) integration, a breakthrough technology to achieve “More Moore and More Than Moore,” opens up the possibility of designing cores and associated network routers using multiple layers by utilizing monolithic inter-tier vias (MIVs) and hence, reducing the effective wire length. Compared to TSV-based 3D integrated circuits (ICs), M3D offers the “true” benefits of vertical dimension for system integration: the size of an MIV used in M3D is over 100 × smaller than a TSV. This dramatic reduction in via size and the resulting increase in density opens up numerous opportunities for design optimizations in 3D manycore systems: designers can use up to millions of MIVs for ultra-fine-grained 3D optimization, where individual cores and routers can be spread across multiple tiers for extreme power and performance optimization. In this work, we demonstrate how M3D-enabled vertical core and uncore elements offer significant performance and thermal improvements in manycore heterogeneous architectures compared to its TSV-based counterpart. To overcome the difficult optimization challenges due to the large design space and complex interactions among the heterogeneous components (CPU, GPU, Last Level Cache, etc.) in a M3D-based manycore chip, we leverage novel design-space exploration algorithms to trade off different objectives. The proposed M3D-enabled heterogeneous architecture, called HeM3D , outperforms its state-of-the-art TSV-equivalent counterpart by up to 18.3% in execution time while being up to 19°C cooler.

3D ICs are assumed to suffer from stronger thermal issues when compared to equivalent implementations in traditional single-die integration technologies. Based on this assumption, heat dissipation is frequently pointed as one of the remaining challenges in the promising 3D integration technology. This work brings an overview of the thermal impact of the 3D integration technology, providing means to investigate causes and alternative solution for the existing thermal issues in 3D ICs. A complete chip-package-board system is used to evaluate the thermal performance of a memory-on-logic 3D circuit. Thermal simulations and silicon measurements from two fabricated versions of a SoC instrumented with integrated heaters and thermal sensors are compared to reveal the temperature profile changes resulting from 3D integration. This work also provides a comprehensive discussion of the four main aspects differentiating heat dissipation in 3D ICs: chip footprint, die thickness, inter-die interface and TSVs. This study demonstrates, for instance, that non-thinned stacked dies may act as heat spreaders and help to alleviate hotspot issues while TSVs are in fact not effective for thermal mitigation. Lastly, this work proposes the use of graphite-based heat spreaders as an alternative to compensate the poor heat dissipation properties exhibited in 3D ICs. Simulation results show a temperature reduction of up to 45μC and suggest this is a potential cost-effective method for thermal management. The discussion presented in this work aims to understand the thermal impact of technology parameters inherent in 3D integration and supports system architects and designers to take early design decisions and prevent thermal issues.

To meet the needs of the continual scaling of wiring structures, 3D IC integration with through-silicon-vias has become the most important direction to go for further miniaturization. Compared to the conventional packaging, 3D integration based on the TSV technology has several inherent advantages, such as small size, high density and short interconnect path. Consequently, TSV technology has attracted wide spread interest in the circuits and devices, packaging and testing communities in the world. As the heart and key technology for 3D integration, TSV structures should be sufficiently reliable to guarantee the performance of the packaged devices. Among all the concerned reliability problems, thermo-mechanical interfacial reliability is crucial one which should deserve more attention. In this paper, modeling and simulation has been carried out to examine the impact of the thermal stress on the interfacial reliability of the TSV structures. Firstly, distribution of the thermal stresses and strains of the structure and the interface has been calculated by a thermo-mechanical FEA model. To obtain more appropriate results, the copper filled in the vias was considered to be elastic-plastic. The mechanical elastic property and the coefficients of thermal expansion (CTE) of copper and silicon were considered to be temperature dependent. Subsequently, a damage model was built up to simulate the initiation and propagation of the interfacial crack. Cohesive elements with “traction-separation” response were used in the model. Furthermore, energy release rate associated with interfacial crack growth was calculated and J-integral method for calculation of energy release rate was introduced to investigate the crack growth stability of TSV structures with preexisting cracks. Cases with cracks at different locations and various crack lengths have been simulated. Results indicate that thermal stress may concentrate on the interface with different materials. The stress concentration locations were the potential positions where the crack may be most likely initiated. And the simulation results of the damage model show that the interface crack growth may be unstable and cracks may initiate and propagate as the temperature difference is up to 325°C. And the interface may fail to work rapidly once it is damaged. For the preexisting cracks in the interface, they may propagate if the crack length is long enough. The estimated critical length of notch crack is about 2µm, and 4µm for buried cracks when a temperature difference 255 °C is applied on the structure. The energy release rate increases with the crack length. The results further show that the strain energy release rate for notch cracks is higher than the buried ones with the same crack length so that the notch cracks should deserve more attention during the manufacture processes.

All computing platforms, from mobile to supercomputers, are becoming more and more heterogeneous and massively parallel. While they can provide higher power efficiency and computation throughput, effective and confident use of these systems always requires knowledge about low-level programming. The average time necessary to develop and optimize a design on heterogeneous platforms is higher and higher compared to typical homogeneous systems. Dataflow models of computation (MoC) are quickly becoming the common practice in heterogeneous systems development. In domains such as signal processing and multimedia communication, dataflow MoCs have become accepted as standard. However, the shift from a sequential and architecture-specific MoC to a dataflow MoC still uncovers several programming and development challenges. The Cal Actor Language (CAL) is a recently-specified dataflow and actor-based language capable of concisely expressing complex and general purpose parallel applications. However, design tools supporting this language are generally not adequate to fully exploit its features and expressiveness power. In fact, they generally restrict its MoC in order to reduce the design space exploration (DSE) effort. The objective of this thesis is to provide a DSE methodology where all the features of CAL and dynamic dataflow MoCs can be exploited in a more general and effective manner. This dissertation illustrates a novel profiling, analysis and performance estimation methodology for the DSE of dynamic dataflow programs. The main research contributions of this thesis are: the formalization of a graph-based representation of the program execution called an execution trace graph (ETG); the formalization of a systematic methodology for profiling generic dynamic dataflow programs through their code interpretation; the formalization of a complete DSE methodology for dynamic dataflow programs in order to efficiently identify close-to-optimal design points according to various and tailored performance merit functions. In particular, the following design space optimization problems for dynamic dataflow programs are addressed: the analysis of the hotspots and the algorithmic bottlenecks of a parallel program; the bounding and optimization of the buffer size configuration for complex designs; the dynamic power dissipation minimization of programs implemented in multi-clock domain architecture. Furthermore, theoretical concepts like the design space critical path and the potential speedup of a dataflow application have been defined and revisited, respectively. The thesis also presents a DSE framework developed in order to demonstrate the effectiveness of this design methodology.