Failure Analysis Using Scanning Acoustic Microscopy for Diagnostics of Electronic Devices and 3D System Integration Technologies

Three dimensional (3D) integration offers numerous electrical advantages like shorter interconnection distances between different dies in the stack, reduced signal delay, reduced interconnect power and design flexibilities. The main enabler of 3D integration is through-silicon-vias (TSVs) and stacking of multiple dies. Irrespective of these advantages, thermal management in 3D stacks poses significant challenges for the implementation of 3D integrated circuits. Even though extensive research work has been done in understanding the thermal management in two dimensional (2D) planar circuits for the past several decades, 3D integration offers a new set of challenges in terms of thermal management, which makes it difficult to readily apply the thermal management strategies available for 2D planar circuits. Over the past decade, some work has been done in thermal analysis and management of 3D stacks but still, knowledge is scattered and a comprehensive understanding is lacking. This research work focuses on bringing together the limited work on thermal analysis and thermal management in 3D vertically integrated circuits available in the literature. A compilation and analysis of the results from investigations on thermal management in 3D stacks is presented in this review with special emphasis on experimental studies conducted on different thermal management strategies. Furthermore, 3D integration technologies, thermal management challenges, and advanced 2D thermal management solutions are discussed.

To meet the needs of the continual scaling of wiring structures, 3D IC integration with through-silicon-vias has become the most important direction to go for further miniaturization. Compared to the conventional packaging, 3D integration based on the TSV technology has several inherent advantages, such as small size, high density and short interconnect path. Consequently, TSV technology has attracted wide spread interest in the circuits and devices, packaging and testing communities in the world. As the heart and key technology for 3D integration, TSV structures should be sufficiently reliable to guarantee the performance of the packaged devices. Among all the concerned reliability problems, thermo-mechanical interfacial reliability is crucial one which should deserve more attention. In this paper, modeling and simulation has been carried out to examine the impact of the thermal stress on the interfacial reliability of the TSV structures. Firstly, distribution of the thermal stresses and strains of the structure and the interface has been calculated by a thermo-mechanical FEA model. To obtain more appropriate results, the copper filled in the vias was considered to be elastic-plastic. The mechanical elastic property and the coefficients of thermal expansion (CTE) of copper and silicon were considered to be temperature dependent. Subsequently, a damage model was built up to simulate the initiation and propagation of the interfacial crack. Cohesive elements with “traction-separation” response were used in the model. Furthermore, energy release rate associated with interfacial crack growth was calculated and J-integral method for calculation of energy release rate was introduced to investigate the crack growth stability of TSV structures with preexisting cracks. Cases with cracks at different locations and various crack lengths have been simulated. Results indicate that thermal stress may concentrate on the interface with different materials. The stress concentration locations were the potential positions where the crack may be most likely initiated. And the simulation results of the damage model show that the interface crack growth may be unstable and cracks may initiate and propagate as the temperature difference is up to 325°C. And the interface may fail to work rapidly once it is damaged. For the preexisting cracks in the interface, they may propagate if the crack length is long enough. The estimated critical length of notch crack is about 2µm, and 4µm for buried cracks when a temperature difference 255 °C is applied on the structure. The energy release rate increases with the crack length. The results further show that the strain energy release rate for notch cracks is higher than the buried ones with the same crack length so that the notch cracks should deserve more attention during the manufacture processes.

3D ICs are assumed to suffer from stronger thermal issues when compared to equivalent implementations in traditional single-die integration technologies. Based on this assumption, heat dissipation is frequently pointed as one of the remaining challenges in the promising 3D integration technology. This work brings an overview of the thermal impact of the 3D integration technology, providing means to investigate causes and alternative solution for the existing thermal issues in 3D ICs. A complete chip-package-board system is used to evaluate the thermal performance of a memory-on-logic 3D circuit. Thermal simulations and silicon measurements from two fabricated versions of a SoC instrumented with integrated heaters and thermal sensors are compared to reveal the temperature profile changes resulting from 3D integration. This work also provides a comprehensive discussion of the four main aspects differentiating heat dissipation in 3D ICs: chip footprint, die thickness, inter-die interface and TSVs. This study demonstrates, for instance, that non-thinned stacked dies may act as heat spreaders and help to alleviate hotspot issues while TSVs are in fact not effective for thermal mitigation. Lastly, this work proposes the use of graphite-based heat spreaders as an alternative to compensate the poor heat dissipation properties exhibited in 3D ICs. Simulation results show a temperature reduction of up to 45μC and suggest this is a potential cost-effective method for thermal management. The discussion presented in this work aims to understand the thermal impact of technology parameters inherent in 3D integration and supports system architects and designers to take early design decisions and prevent thermal issues.

Monolithic inter-layer vias (MIVs) used in 3D integration technology are much smaller than through-silicon vias (TSVs) used in TSV-based 3D integration. Thus, monolithic 3D integration provides shorter wire length, better performance, and lower power consumption than TSV-based 3D integration. Multi-tier monolithic 3D integration stacks more than two silicon layers, thereby increasing the device density, which reduces the wire length and power consumption and improves performance further than two-tier monolithic 3D integration. Since the size of an MIV is comparable to that of a local via, the wire lengths of multi-tier gate-level monolithic 3D IC layouts are expected to be close to the ideal wire length reduction ratio, for example, 29, 42, and 50 percent for two-, three-, and four-tier designs, respectively. However, it is still unknown whether it would be possible to achieve the ideal wire length reduction ratios by multi-tier gate-level monolithic 3D integration. In this paper, we propose an efficient routing methodology to design multi-tier monolithic 3D ICs. Using the design methodology, we design two- to eight-tier gate-level monolithic 3D IC layouts and thoroughly investigate the wire length characteristics of the layouts. The simulation results show that the proposed routing methodology reduces the wire length by 12 to 53 percent compared to the 2D designs. In addition, the proposed routing methodology builds multi-tier monolithic 3D IC layouts more efficiently than a state-of-the-art methodology with comparable routed wire length.

Today 3D integration based on through silicon vias (TSV) is a well-accepted approach to overcome the performance bottleneck and simultaneously shrink the form factor. According to the ITRS road map [1] there is a variety of reasons for application of 3D integration, such as miniaturization, improved circuit performance, lower power consumption and heterogeneous integration. World-wide, several full 3D process flows have been demonstrated. However, there is a strong demand for considering the behaviour and reliability of 3D-integrated systems [2]. Explicitly, the impact of 3D processes on the system, e.g. thermo-mechanical stresses, has to be evaluated before the implementation to production lines. A test chip for reliability evaluation of 3D TSV technologies was designed and fabricated by Fraunhofer EMFT. The 3D-integrated reliability test chip is a 3-level-stack with TSVs through a middle (2nd) device layer to connect structures on the bottom (1st) level with the top (3rd) level device. The layout is modular, so you can test basic assembly processing with the combination of level 1 with level 2 only and the influence of additional processing when adding level 3. For reliability testing, temperature cycling following the JEDEC standard was performed from −55 C ° to +150 °C (at a soak time of 5 minutes). Additionally, analysis was done by cross sectioning and reversed engineering. The 3D-integrated test chips were fabricated by application of Fraunhofer EMFT's TSV SLID technology. The applied 3D TSV process is based on intermetallic compound (IMC) bonding and TSV formation before stacking [3]. Reliability issues related to thermo-mechanical stress caused by the 3D integration process have to be considered. Failures of 3D integrated systems caused by TSV formation and the permanent bonding process were analysed by a novel high rate milling Focussed Ion Beam equipment. Figure 1 schematically shows the application of the novel FIB analysis technique for the areas of interest (IMC bond, TSV cross sections). Compared to classical FIB systems, the new equipment allows to remove material significantly faster while maintaining good resolution at low beam currents, important for the subsequent analysis. Cross sections of the 3-layer stack are shown in Figure 2. The merits of the novel plasma FIB and the resulting failure analysis will be discussed in detail.

The effects of delamination at the mold component/die interface during reliability testing are investigated using scanning acoustic microscopy (SAM), and electrical and physical analyses. The SAM results are correlated with electrical end point (EEP) tests and destructive physical analysis. The spread of delamination during temperature cycling of units is examined. It is demonstrated that scanning acoustic microscopy provides a significant improvement over cross sectioning for the inspection of critical defects in IC packages. The impact of this result on a test method for package reliability evaluation based on inspection for package cracks is discussed. >

3D IC is just one of a host of 3D integration schemes that exploit the z-direction Philip Garrou, Christopher Bower, Peter Ramm: Handbook of 3D Integration. Peter Ramm, Fraunhofer EMFT, defines heterogenous 3D integration as 3D for 3D Integration and Interposer Technologies”, Handbook of 3D Integration, Vol. Desktop 3D printing giant MakerBot has published a handbook designed to to support the integration of 3D printing in the classroom though challenges.

Traditional failure analysis (FA) methods face growing challenges due to the increasing miniaturization and complexity of modern semiconductor devices. In particular, the detection of cracks in the extreme low K layers of flip-chips, utilized in advanced packaging architectures at the back end of line (BEOL), is challenging. To improve detectability of these defects, we propose an AI-based image enhancement workflow, specifically tailored to improve scanning acoustic microscopy (SAM) images. By applying a Deep CNN with Skip Connections and Network in Network (DCSCN) model to lowresolution C-scan SAM images, we are able to improve perceptual quality of images. The approach boosts resolution dependent analysis like AI-based object detection and classification as well as decreases significantly SAM scanning time. Our work demonstrates that AI-based image enhancement can significantly improve FA workflows, offering a robust and efficient solution for modern semiconductor analysis.

The next generation of small form factor (SFF) microsystem technologies can only keep up with increased functionality and performance demands by using the third dimension. 3D integration technologies can be grouped into following distinct technology approaches: (i) 3D-monolithic IC integration, (ii) 3D stacking of IC-dies, wafers and packages, and (iii) 3D integrated packaging. This paper provides an overview on the various 3D integration and enabling technologies as well as the associated challenges that exist for SFF wireless system implementation with optimum cost and performance.

3D integration is a key solution to the predicted performance problems of future ICs as well as it offers extreme miniaturization and cost-effective fabrication of so-called more than Moore products as e.g. MEMS/IC systems. Through silicon via (TSV) technologies enable high interconnect performance at relatively high fabrication cost compared to 3D packaging. In general it is not only one 3D integration technology suitable for the fabrication of the large variety of 3D integrated systems. Moreover, even one single product may need several different technologies for a cost-effective fabrication. Wireless sensor systems (e.g. e-CUBES <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">reg</sup> ) an excellent example for the need of a suitable mixture. Consisting of MEMS, ICs, memories, antennas and power modules they can only be fabricated in a cost-efficient way by application of specific optimized 3D technologies for the integration of the different sub-modules. The technology choice for an e-CUBES demonstrator is described.

In a first time confined to labs and then R&amp;D centers, 3D integration technologies have now gained maturity and are now penetrating the industrial world. More and more, R&amp;D centers are approached to back the industrial developments with associated constraints of swift product development, prototyping, and short time-to- market. To face this paradigm, Léti has developed a specific two-step approach in the field of 3D integration, including both a very advanced R&amp;D part focused on the most promising technologies and integration flows, and the industrial validation of the most mature process flows already assessed at the laboratory scale or on specific industrial themes. This talk aims to detail the two aspects of this dual approach:-In the first part, we will give an overview of the innovative R&amp;D performed on the still nascent and most promising integration flows, as well as the associated technological means.-in the second part, we will present the prototyping activities that Léti is now offering. Based on a limited number of mature and already validated process steps (bonding and thinning, TSV, bumping, stacking) this generic integration scheme allows industrial customers to assess on their own wafers the benefits of an innovative 3D integration.

We proposed 3D heterogeneous opto-electronic integration technology for system-on-silicon (SOS). In order to realize 3D opto-electronic integrated system-on-silicon (SOS), we developed novel heterogeneous integration technology of LSI, MEMS and optoelectronic devices by implementing 3D heterogeneous opto-electronic multi-chip module composed with LSI, passives, MEMS and optoelectronic devices. The electrical interposer mounted with amplitude shift keying (ASK) LSI, LC filter and pressure-sensing MEMS chips and the optical interposer embedded with vertical-cavity surface-emitting laser (VCSEL) and photodiode (PD) chips are precisely bonded to form 3D opto-electronic multi-chip module. Opto-electronic devices are electrically connected via through-silicon vias (TSVs) which were formed into the interposers. Micro-fluidic channels are formed into the interposer by wafer direct bonding technique. 3D heterogeneous opto-electronic multi-chip module is successfully implemented for the first time.

Three-dimensional (3D) integration is adopted in the semiconductor industry to overcome the slowdown of Moore's Law. The 3D integration is beneficial in terms of interconnection bandwidth, wire delay, power efficiency, and area. However, the on-chip temperature of 3D stacked CPUs is known as much higher than that of conventional 2D CPUs due to the higher power density and lower heat dissipation capability. High on-chip temperature leads to performance degradation of 3D stacked CPUs due to following reasons: 1) High on-chip temperature leads to frequent Dynamic Thermal Management (DTM) invocations, which limits practical CPU voltage and clock frequency. 2) The power limits are used to proactively deal with the thermal problems from high on-chip temperature by adjusting the CPU clock frequency. In this paper, we explore the thermal characteristics of the first off-the-shelf through-silicon-via (TSV) based 3D stacked CPU (Intel Lakefield). In our evaluation, 3D CPU w/ the forced air cooling w/o PL1 shows 21.7% and 6% better single thread performance, on average, compared to 3D CPU w/ PL1 and 3D CPU w/o PL1, respectively. Although the 3D stacked CPU was launched to the market, we identify that the thermal problems of the 3D stacked CPU have not been fully resolved. To tackle the thermal problems of 3D stacked CPUs in the future, researchers are required to consider more innovative integration technologies, optimized DTM techniques, and advanced cooling solutions.

Scanning acoustic microscopy (SAM) of Haversian bone at high frequency clearly shows differences in the brightness (gray) levels of individual osteons, which were observed to correspond to the differences in reflection coefficients measured with the SAM technique: the darker the bony regions on the SAM micrographs, the lower the SAM reflection coefficient values, and vice versa. We studied the correlation between differences in brightness and the related reflection coefficients of osteons on undecalcified transverse sections of goat tibial diaphysis using a 400-MHz burst mode lens on the Olympus UH3 SAM. Results showed that there was a strong linear correlation between brightness intensities and the corresponding reflection coefficients, with a correlation coefficient r = 0.99 ( P << 0.001) using gray level 210 as cutoff. This result suggested that the image brightness intensity of osteonic bone could be measured retrospectively to provide information on the stiffness of the corresponding bone matrix.

Scanning acoustic microcopy (SAM) method with inverted inspection direction has been successfully develop and evaluate the quality of flip chip underfill and interconnect bonds in manufacturing of microelectronic components. Acoustic microscopes utilize high frequency ultrasound transmitting through the silicon chip backside in one scan to access and examine the internal structures in optically opaque materials. These non-destructive methods relatively enable the defect localization which leads microstructural examinations involving destructive analysis sample preparation. For the justification of accuracy of SAM method analysis, a destructive cross-sectioned and mechanical lapping physical analysis were performed for preparing the samples and examine by optical microscope and Scanning Electron Microscope (SEM) for defect verification. Cases studies have been demonstrated that the capabilities of conventional SAM inspection and advantages over other analysis method.