FPGA Implementation of Discrete Fourier Transform Core Using NEDA

Nonlinear digital filters play an important role in digital signal processing applications. In this brief, a novel architecture is proposed for the hardware implementation of fixed and runtime variable window length one-dimensional median filters. In the proposed architecture, the maximum working clock frequency is almost independent of the median filter window length, whereas the hardware complexity is proportional to the number of samples in the window. This feature enables the construction of filters with relatively large window lengths with negligible reduction in the maximum clock frequency, whereas in previous architectures, the maximum clock frequency significantly drops as the window length is increased. The benchmark results show the efficiency of the proposed architecture in comparison with state-of-the-art techniques.

The design of both area-efficient and reliable VLSI arrays for computation of the complex N-point discrete Fourier transform (DFT) is considered. C.D. Thompson's VLSI model of computation (1979) is used to quantify the area required by wiring and the achievable period. Four architectures using the fast two-dimensional (2-D) algorithm for the DFT that achieve the maximum throughput per chip area are presented. The first two use N-element 2-D meshes requiring N+2N/sup 3/2/ multiplications and 1+2 square root N periods per DFT. The first uses in place data I/O and can be made systolic with Goertzel's algorithm. The second is systolic with row parallel I/O. The third and fourth architectures both use pipelined DFT blocks of length square root N connected by a pipelined matrix transposer. The third uses systolic 2-D meshes for the short DFTs with period square root N. The fourth uses pipelined butterfly networks implementing standard FFT algorithms for the short DFTs, but only N(1+log/sub 2/ N) multiplications per DFT, thus preserving maximum throughput per unit area. The technique of algorithm-based fault-tolerance applies directly to all four architectures with only fractional redundant overhead. >

The advent of Dark Silicon as result of the limit on Dennard scaling forced modern processor designs to reduce the chip area that can work on maximum clock frequency. This effect reduced the free gains from Moore's law. This work introduces a less conservative dark silicon estimate based on chip components power density and technological process, so that designers could explore architectural resources to mitigate it. We implemented our dark silicon estimation tool on top of MultiExplorer and evaluated on a set of Intel Pentium and AMD K8/10 multicore processors built on transistor technologies from 90nm down to 32nm. Our contributions are twofold: (1) Our experiments have shown dark silicon estimates up to 8.26% of the chip area compared to a baseline 90nm real processor, we also evaluated clock frequency behavior based on Dennard scaling and obtained up to 15.65% dark silicon on chip area. (2) We designed and showed that a dark silicon aware Design Space Exploration (DSE) strategy can minimize chip dark area while increasing performance at design time. Our results on DSE found dark silicon free multicore platforms while providing 3.6 speedup.

We demonstrate the functioning of a high-throughput, gate-level-pipelined floating-point adder and multiplier over 50 GHz. The gate-level-pipelined floating-point adder and multiplier requires dedicated circuit blocks to wait until other circuit blocks complete calculations because of the dependence between their sign, exponent, and significand parts. We revealed that the resultant delay difference of the waiting circuit blocks hinders high-frequency operation if the predesigned circuit blocks with the fixed clock distribution are connected in a simple manner. We showed that clock distribution needs to synchronize with every pipeline stage regardless of the circuit blocks to minimize the delay difference between the circuit blocks for circuits containing the waiting circuit blocks (e.g., the floating-point adder and multiplier). We designed a 5-bit floating-point adder and multiplier to demonstrate the effectiveness of the clock distribution experimentally. The test chips were fabricated using AIST 10-kA/cm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\boldsymbol{^{2}}$</tex-math></inline-formula> Advanced Process 2. We verified the high-speed operation at over 50 GHz in the floating-point adder and multiplier. The maximum clock frequency and throughput of the floating-point adder were 56 GHz and 56 GFLOPS, respectively. The corresponding values for the floating-point multiplier were 63 GHz and 63 GFLOPS, respectively.

The need for wireless communication has driven the communication systems to high performance. However, the main bottleneck that affects the communication capability is the Fast Fourier Transform (FFT), which is the core of most modulators. This study presents an on-chip implementation of pipeline digit-slicing multiplier-less butterfly for FFT structure. The approach is taken, in order to reduce computation complexity in the butterfly, digit-slicing multiplier-less single constant technique was utilized in the critical path of Radix-2 Decimation In Time (DIT) FFT structure. The proposed design focused on the trade-off between the speed and active silicon area for the chip implementation. The new architecture was investigated and simulated with MATLAB software. The Verilog HDL code in Xilinx ISE environment was derived to describe the FFT Butterfly functionality and was downloaded to Virtex II FPGA board. Consequently, the Virtex-II FG456 Proto board was used to implement and test the design on the real hardware. As a result, from the findings, the synthesis report indicates the maximum clock frequency of 549.75 MHz with the total equivalent gate count of 31,159 is a marked and significant improvement over Radix 2 FFT butterfly. In comparison with the conventional butterfly architecture, the design that can only run at a maximum clock frequency of 198.987 MHz and the conventional multiplier can only run at a maximum clock frequency of 220.160 MHz, the proposed system exhibits better results. The resulting maximum clock frequency increases by about 276.28% for the FFT butterfly and about 277.06% for the multiplier. It can be concluded that on-chip implementation of pipeline digit-slicing multiplier-less butterfly for FFT structure is an enabler in solving problems that affect communications capability in FFT and possesses huge potentials for future related works and research areas.

In this paper a novel coded multi-dimensional spreading technique using the Discrete Fourier Transform (DFT) is introduced. It exploits the DFT characteristic of spreading one symbol in one domain to all the symbols in the corresponding transform domain. Frequency domain channel estimation is performed at the receiver. The performance of a coded twodimensional (2D) DFT spreading communication system is investigated and simulation results are presented, using first a 2D DFT time-frequency system and then a 2D DFT space-frequency system. The proposed 2D DFT system shows good immunity to narrowband interference and impulse noise and exhibits a significant performance improvement when compared with a coded conventional OFDM system of equivalent size.

Discrete Fourier transforms (DFTs) over finite fields have widespread applications in various communication and storage systems. Hence reducing the computational complexities of DFTs is of great significance. Recently proposed cyclo-tomic fast Fourier transforms (CFFTs) are promising due to their low multiplicative complexities. Unfortunately, they have very high additive complexities. Techniques such as common subexpression elimination (CSE) can be used to reduce the additive complexities of CFFTs, but their effectiveness for long DFTs is limited by their complexities. In this paper, we propose prime factor cyclotomic Fourier transforms (PFCFTs), which use CFFTs as sub-DFTs via the prime factor algorithm. When the length has co-prime factors, the short lengths of the sub-DFTs allow us to use CSE to significantly reduce their additive complexities. In comparison to previously proposed fast Fourier transforms, our PFCFTs achieve reduced overall complexities when the lengths of DFTs are at least 255, and the improvement significantly increases as the length grows. This approach enables us to propose the first efficient DFTs with very long length (e.g., 4095-point) in the literature. Finally, our PFCFTs are also advantageous for hardware implementation due to their regular structure.

In this work we present some improvements on hardware operators dedicated to the computation of power operations with fixed integer exponent (x 3 ,x 4 ...) in unsigned radix-2 fixed-point or integer representations. The proposed method reduces the number of partial products using simplifications based on new identities and transformations. These simplifications are performed both at the logical and the arithmetic levels. The proposed method has been implemented in a VHDL generator that produces synthesizable descriptions of optimized operators. The results of our method have been demonstrated on FPGA circuits.

This paper is on the use and performance of M-path polyphase Infinite Impulse Response (IIR) filters for channelisation, conventionally where Finite Impulse Response (FIR) filters are preferred. This paper specifically focuses on the Discrete Fourier Transform (DFT) modulated filter banks, which are known to be an efficient choice for channelisation in communication systems. In this paper, the low-pass prototype filter for the DFT filter bank has been implemented using an M-path polyphase IIR filter and we show that the spikes present at the stopband can be avoided by making use of the guardbands between narrowband channels. It will be shown that the channelisation performance will not be affected when polyphase IIR filters are employed instead of their counterparts derived from FIR prototype filters. Detailed complexity and performance analysis of the proposed use will be given in this article.

We propose an empirical compressed learning approach based on generalized approximate message passing (GAMP) for deterministic sensing matrix with low spark. The spark of a matrix is defined as the minimum number of correlated columns. In contrast to previous works, GAMP with independent and non-identically distributed Gaussian prior for the sparse signal to be estimated is used to avoid the over-fitting problem in the original GAMP. Specifically, we consider the discrete Fourier transform (DFT) sub-matrix as part of the sensing matrix which is common used in communication systems. Then we consider using the proposed approach to the estimation and mitigation of impulsive noise in orthogonal frequency division multiplexing (OFDM) systems utilizing null tones. Numerical results show that the performance of the proposed method is close to sparse Bayesian learning (SBL) for low spark DFT matrices and about 1dB performance gain in symbol error rate (SER) is observed over existing GAMP based approaches for Gaussian mixture interferences and more than 5dB gain at symbol error rate (SER) of 0.01 for stable-alpha-symmetric interference. The complexity is only O(Nlog2N), where N is the size of the signal to be estimated.

A model describing the maximum clock frequency (FMAX) distribution of a microprocessor is derived and compared with wafer sort data for a recent 0.25-/spl mu/m microprocessor. The model agrees closely with measured data in mean, variance, and shape. Results demonstrate that within-die fluctuations primarily impact the FMAX mean and die-to-die fluctuations determine the majority of the FMAX variance. Employing rigorously derived device and circuit models, the impact of die-to-die and within-die parameter fluctuations on future FMAX distributions is forecast for the 180, 130, 100, 70, and 50-nm technology generations. Model predictions reveal that systematic within-die fluctuations impose the largest performance degradation resulting from parameter fluctuations. Assuming a 3/spl sigma/ channel length deviation of 20%, projections for the 50-nm technology generation indicate that essentially a generation of performance gain can be lost due to systematic within-die fluctuations. Key insights from this work elucidate the recommendations that manufacturing process controls be targeted specifically toward sources of systematic within-die fluctuations, and the development of new circuit design methodologies be aimed at suppressing the effect of within-die parameter fluctuations.

An essential element of HF communications systems is the excision of narrowband interference. The interference in the received signal is excised by first performing a discrete Fourier transform (DFT), then identifying and removing narrowband interferers in the frequency domain, and finally transforming the remaining signal back into the time domain via inverse DFT. In the present work the statistical F-test for variance equality was used to determine the stationarity of wideband HF noise and interference after excision. The most obvious result of this test is the systematic failure of the F-test near the DFT boundaries. This failure is due to short but large amplitude glitches present in the signal after excision, and occur at the beginning and end of the DFT interval. It is shown that the glitches are an artifact of the excision operation and are related to Gibb's phenomenon. It is concluded that system designs will have to take account of this observation. >

In the LTE uplink, Single Carrier Frequency Division Multiple Access (SC-FDMA) is adopted as its multiple access scheme. The Channel Estimation (CE) is one of the key technologies in mobile communication system. According to the latest LTE criterion, the pilot-aided CE algorithms of SC-FDMA are researched in this paper. Our research mainly discusses Least-Square (LS), the traditional LS based on Discrete Fourier transform (DFT) and the improved LS based on DFT. Finally, theoretical analysis and simulation result show that: The improved LS based on DFT has more superior estimation performance than the traditional LS based on DFT while it increases the computational complexity in the low SNR.

Orthogonal frequency division multiplexing (OFDM) is adopted in most wireless communication systems, and the performance of OFDM is affected by impulse noise (IN). Better channel estimation (CE) performance is required to detect the channel information on the receiving side. The OFDM system is considered with the number of subcarriers carrying the data and pilot symbols. In the OFDM modulator, the symbols of the frequency domain are transformed into the signals of the time domain using inverse discrete Fourier transformation (IDFT). Effective impulsive noise mitigation is crucial for improving the effectiveness of OFDM communication systems, and it improves the signal-to-noise ratio (SNR) at the receiver. A cyclic prefix is then appended before transmission through the channel. In the receiver noise, the effect of IN is mitigated jointly with CE using the Bayesian matching pursuit (BMP) and Moth-flame algorithm (MFA). In this approach, the IN and channel information is considered as a sparse vector. Here, the data symbols used are considered an unknown parameter. The approach incorporating all subcarriers has a lower mean square error (MSE) of IN estimate for impulsive noise reduction. The MFA algorithm is used to optimize the sensor matrix in BMP. The sparsity of the channel and the impulse response are observed in the time domain to represent the channel and IN together. It exactly recovers the sparse signal for finding the convex objectives of the sparse minimizer, and the sparse solution is obtained with fixed point updates. The proposed BMP algorithm improves the CE by explicitly considering the existence of IN. The BMP is a greedy algorithm that selects the most correlated residuals at each column. Under mutual incoherence, it recovers the signal with a higher probability. The simulated outcomes proved that the proposed CE and noise mitigation model achieved better performance based on the bit error rate (BER), throughput and MSE.

SummaryThe implementation of the Orthogonal Frequency Division Multiplexing (OFDM) can be achieved using Inverse Discrete Cosine Transform (IDCT), and DCT instead of Inverse Discrete Fourier Transform (IDFT), and DFT. The Carrier Frequency Offset (CFO) is the main issue of the OFDM system. One of the tools to mitigate the CFO effect and improve the Bit‐Error‐Rate (BER) performance is the equalization procedure. Also, the 1‐Dimension (1‐D), and 2‐Dimension (2‐D) burst errors can be mitigated using a chaotic interleaver in the OFDM system. This consequently improves the BER performance. In this paper, we propose a Joint Low‐Complexity Regularized Linear Zero Forcing (JLCRLZF) equalizer for the OFDM system based on DCT in addition to a chaotic interleaving scheme. The proposed equalizer depends on the concept of the banded‐matrix approximation, and jointly performs the equalization and CFO compensation processes. Simulation results ensure the importance of the proposed JLCRLZF equalizer compared to other algorithms.