Carrier Mobility Extraction Methodology in Junctionless and Inversion-Mode FETs

This paper presents a unified compact model for a junctionless (JL) multiple-gate (MG) FET operating in the subthreshold region. A unified center potential model for double-gate, triple-gate, and quadruple-gate (QG) JL FETs is obtained using a quasi-3D scaling equation. The source/drain (S/D) extension regions are also modeled depending on the S/D extension length. The subthreshold current and subthreshold characteristics such as the subthreshold slope, threshold voltage, and drain-induced barrier lowering are analytically modeled for JL MG FETs. Comparison of the proposed models with numerical simulation results obtained using Sentaurus TCAD showed good accuracy, even for a very-short-channel QG device with a channel length of 10 nm. The proposed compact model can be used for low power circuit applications of JL MG FETs.

Impact ionization induced dynamic floating body effect in junctionless transistors

본 연구에서는 다중게이트 구조인 나노 와이어 n-채널 무접합(junctionless)와 반전모드(inversion mode) 다중게이트 MOSFET(Multiple-Gate MOSFET : MuGFET)의 PBTI에 의한 소자 특성 저하를 비교 분석하였다. PBTI에 의해서 무접합 및 반전모드 소자의 문턱전압이 증가하는 것으로 관측되었으며 무접합 소자의 문턱전압 변화가 반전모드 소자보다 작음을 알 수 있었다. 그러나 소자특성 저하 비율은 반전모드 소자가 무접합 소자보다 큰 것으로 관측되었다. 특성저하 활성화 에너지는 반전모드 소자가 무접합 소자보다 큰 것을 알 수 있었다. PBTI에 의한 소자 특성 저하가 무접합 소자보다 반전모드 소자가 더 심한 것을 분석하기 위하여 3차원 소자 시뮬레이션을 수행하였다. 같은 게이트 전압에서 전자의 농도는 같으나 수직방향의 전계는 반전모드 소자가 무접합 소자보다 큰 것을 알 수 있었다. In this paper, a comparative analysis of PBTI induced device degradation in nanowire n-channel junctionless and inversion mode Multiple-Gate MOSFET(MuGFETs) has been performed. It has been observed that the threshold voltage is increased after PBTI stress and the threshold voltage variation of junctionless device is less significant than that of inversion mode device. However the degradation rate of junctionless device is less significant than that of inversion mode device. The activation energy of the device degradation is larger in inversion mode device than junctionless device. In order to analyze the more significant PBTI induced device degradation in inversion mode device than junctionless device, 3-dimensional device simulation has been performed. The electron concentration in inversion mode device is equal to the one in junctionless device but the electric field in inversion mode device is larger than junctionless device.

We propose a physics-based analytical model that accurately captures the effects of buffer traps on dc characteristics of gallium nitride (GaN)-based high-electron-mobility transistors (HEMTs). The model is then semi-analytically extended to additionally include the transient behavior. Analytical formulations for the shift in the threshold voltage <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${(}{V}_{\text {OFF}}{)}$ </tex-math></inline-formula> and two-dimensional electron gas (2-DEG) density due to the presence of buffer traps in the steady state are presented. In pulsed operation, technology computer-aided design (TCAD) simulations indicate that a time-dependent negative potential (NP) is developed under the gate, resulting in a modified <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {OFF}}$ </tex-math></inline-formula> and current collapse (CC). An expression for the modified <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {off}}$ </tex-math></inline-formula> helps capture the pulsed current–voltage characteristics. The model captures the dependence of bias, time, temperature, trap concentration, capture cross section area, and activation energy of traps on the steady-state and transient characteristics. The model is implemented in Verilog-A in an existing compact model framework using a diode and <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> sub-circuit and validated using measured data and TCAD simulations. The modeling results are in excellent agreement with the experimental data and TCAD simulations. Since the model is physics-based, it requires fewer number of parameters compared to that in the existing models.

The junctionless (JL) device concept for silicon-on-insulator MOSFETs was introduced by Colinge et al. in 2010 [1], demonstrating considerable gains in terms of process simplicity when compared to conventional inversion-mode MOSFETs. The objective of this work is to implement the JL device concept in an In0.53Ga0.47As channel, where the SiO2 insulator in [1] is replaced by a wider bandgap p-type In0.52Al0.48As barrier layer and to investigate the effect of low-temperature RF hydrogen plasma treatment on the main electrical parameters of such devices. The JL device architecture is particularly well suited to III-V channel materials. Firstly, the high doping concentration (Nd) present in the channel of a JL MOSFET is less problematic for In0.53Ga0.47As than it is for Si. Indeed, the bulk electron mobility in Si is ~100 cm2/V·s at Nd = 1×1019 cm-3, while in In0.53Ga0.47As the bulk mobility is ~4,000 cm2/V·s at a similar Nd level. Moreover, the JL architecture circumvents the difficulties associated with the implantation or regrowth techniques generally used to form the source/drain (S/D) regions of III-V inversion-mode MOSFETs. However in order to form a good Ohmic S/D contacts it is necessary to anneal the device at 350-400°C that could lead to diffusion of In atoms into the gate dielectric. In this work low-temperature RF plasma treatment (RFPT) [2] is proposed to improve S/D contacts and enhance the properties of JL MOSFETs. A structure consisting of a 32-nm-thick n- In0.53Ga0.47As (Nd = 2×1018 cm-3) on a 500-nm-thick p-In0.52Al0.48As (Na = 8×1015 cm-3) barrier was grown by metal organic vapour-phase epitaxy (MOVPE) on a p+-InP wafer (Fig. 1 (a)). In order to form a channel for the JL devices, the In0.53Ga0.47As layer was thinned using a 10% H2O2/10% HCl digital wet etching process to achieve channel thicknesses of 24, 20 and 16 nm. A gate enclosed device layout was employed to simplify the fabrication process flow (Fig. 1(b-e)). A surface passivation in 10% (NH4)2S for 30 min was performed before atomic layer deposition (ALD) of an 8.5-nm-thick Al2O3 gate oxide. A Pd gate was formed by e-beam evaporation and lift-off. The Al2O3 on the S/D contact areas was etched in dilute HF. The S/D contact formation was performed by e-beam evaporation of a Au/Ge/Au/Ni/Au stack and lift-off. The RFPT (13.6 MHz) was performed in forming gas (10%H2+90%N2) with additional heating of the sample holder (up to 200°C). Temperature of the samples at the RFPT did not exceed 250°C [2]. Well behaved Id-Vg characteristics measured on the 24-nm-thick In0.53Ga0.47As channel device are shown in Fig. 2. A threshold voltage (VT) of -0.55 V was extracted using the second-derivative method. Scaling the In0.53Ga0.47As channel thickness down to 16 nm improved the subthreshold swing (SS) but degraded the maximum Id and ION/IOFF due to the combined effect of S/D series resistance (RSD) and mobility degradation. As a result, the lowest SS value (115 mV/dec) was extracted on the 16-nm-thick In0.53Ga0.47As channel device and 190 mV/dec - on the 24-nm-thick In0.53Ga0.47As channel one, but the highest ION/IOFF value (1.5×105) was obtained on the 20-nm-thick In0.53Ga0.47As channel device and 2.0×104 - on the 24-nm-thick In0.53Ga0.47As channel one. The gate-to-channel Cgc-Vg characteristic featured a low frequency dispersion near the accumulation region, suggesting a low density of interface traps (Dit) in the upper part of the In0.53Ga0.47As bandgap. Moreover, the conductance analysis yielded low Dit values ranging from 1.5×1012 to 3.5×1012 cm-2×eV-1 from the conductance band edge to midgap, correspondingly. Measurements of RSD on circular transfer length method (CTLM) structures yielded the value of 12 kOhm on the 20-nm-thick In0.53Ga0.47As channel devices and contacts were strongly rectifying. RF plasma treatment with power 0.5 W/cm2 at 150°C resulted in Ohmic SD contact, a strong decrease of RSD down to 45 Ohm (Fig. 3) and increases the ION by two orders of magnitude (Fig. 2). Additionally, SS for the plasma treated devices decreases from 190 mV/dec to 150 mV/dec, and the threshold voltage shifts to positive values by 0.4 V (Fig.2). This is associated, correspondingly, with a decrease of Dit and negative charge in the gate dielectric. The conductance analysis yielded reduction of Dit at midgap down to 1.0×1012 cm-2×eV-1. [1] Colinge J.-P., Lee C.-W., Afzalian A., Akhavan N.D., Yan R., Ferain I., Razavi P., O'Neill B., Blake A., White M., Kelleher A.-M., McCarthy B., Murphy R. Nanowire Transistors Without Junctions. Nature Nanotechnology. Vol. 5, P. 225-229 (2010). [2] Nazarov A.N., Lysenko V.S., Nazarova T.M. Hydrogen Plasma Treatment of Silicon Thin-film Structures and Nanostructured Layers. Semiconductor Physics, Quantum Electronics & Optoelectronics. Vol. 11, P. 101-123 (2008). Figure 1

Study of parasitic oscillation of a multi-chip SiC MOSFET circuit based on a signal flow graph model by TCAD simulation

TFETs (Tunnel Field-Effects Transistors) are assumed to be ultra-low-power devices because they have steep subthreshold swing and a more favourable scaling characteristic. Their electrical characteristics, however, cannot be adequately simulated using extensive Technology Computer-Aided Design (TCAD) simulations, which are computationally intensive and time-consuming to analyze. In an attempt to overcome this bottleneck, a proposal for a machine learning (ML)-based surrogate modeling framework is provided where the prediction of the critical TFET properties of transfer curves, Ion, Ioff, threshold voltage (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$V_{\text{th}}$</tex>), and subthreshold swing (SS) is endeavored with the help of the Random Forest Regression (RFR) model. The data collected based on TCAD simulations and literature reports was processed, trained, and tested on various ML models such as the Artificial Neural Networks (ANN), Support Vector Regression (SVR) and RFR. The calculated R2 of the proposed RFR model was better than ANN and SVR, with a much smaller MSE (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{3. 2 1} \times \mathbf{1 0}^{-\mathbf{7}}$</tex>) and an RMSE (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{1. 7 9} \times \mathbf{1 0}^{-\mathbf{4}}$</tex>), showing that the model is robust and exhibits better generalization within the conditions of the devices used. Also, the ranking of intrinsic feature importance offered by RFR has a better interpretation rate and complies well with the previous findings on TCAD. These findings place RFR as a sound and efficient substitute for TFET modelling, with lower computational expense and intact physical stability, and thus add another facet and a practical approach to future device design optimization, assisted by a novel and powerful ML

Junction-less FETs are used as top-tier devices in a 3-D sequential integration. Due to the low thermal budget allowed in the 3-D integration, conventional inversion mode FETs show extremely poor BTI reliability. In contrast, a junction-less FET shows improved BTI reliability, which is attributed to the reduced oxide electric field of operation. We observe that the reliability of junction-less FETs can be further improved by increasing the channel doping and/or the channel thickness. Correspondingly, a tradeoff exists between performance (subthreshold slope, carrier mobility), reliability, and variability. This tradeoff is verified in both planar/FinFET structures and can serve as a device optimization matrix. Furthermore, we use the non-radiative multi-phonon (NMP) theory, as implemented in the imec/T.U. Vienna BTI simulation framework “Comphy,” to investigate the degradation kinetics and show that the stress/recovery traces measured in inversion mode and junction-less nFETs can be reproduced with the same set of oxide defect parameters. This observation confirms that the reliability improvement in junction-less devices is inherent to their specific operation mode and not related to the different fabrication flows compared to standard inversion mode devices. Based on the calibrated Comphy model, we perform BTI lifetime projections, exposing for junction-less devices a substantial deviation from the commonly used power-law voltage acceleration.

This work evaluates the potential impact of interface traps on the interface of oxide and semiconductor on a 2-D-based ion-sensitive field-effect transistor (ISFET) using a surface potential-based model and Technology Computer-Aided Design (TCAD) simulation calibrated for pH sensing applications. The electrolyte/oxide interface in the proposed 2-D ISFET model is modeled using the Guoy-Chapman–Stern technique and the site binding association model. The baseline field-effect transistor (FET) of the ISFET is modeled using Fermi-Dirac statistics to obtain surface potential, which is further used to derive a compact drain current expression. The proposed ISFET model development is carried out by accounting for the interface trap effect. The voltage and current sensitivity of ISFET with and without interface traps are calculated to demonstrate the impact of interface traps in 2-D material-based pH sensors. It is observed that voltage sensitivity remains close to the Nernst limit (59 mV/pH), and a decrease in current sensitivity from 34 to 2 nA/pH is observed, as the density of interface traps is varied from 0 to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${5}\times {10} {^{{12}}}$ </tex-math></inline-formula>cm<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-}2 $ </tex-math></inline-formula>eV<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-}1 $ </tex-math></inline-formula>. Another sensitivity metric, the transconductance to drain current ratio, is analyzed for its variation with changes in the density of interface traps. The noise level of ISFET in the presence of interface traps is analyzed, and its influence on the minimum resolvable pH is demonstrated. The proposed model prediction closely matches the TCAD simulation data obtained from a calibrated TCAD simulation setup. The model is suitable for implementation in Verilog-A for ISFET-based circuit simulation, and the impact of interface traps on the response time of ISFET-based circuits is also demonstrated.

A functionally enhanced transistor is a potential candidate for further advancing electronics and Moore's law beyond the classical scaling. This chapter discusses these kinds of multifunctional transistors called reconfigurable field-effect transistor (RFET) and reconfigurable tunnel field-effect transistor (RTFET). The RFET works on the principle of Schottky barrier tunneling, and the RTFET works on the principle of band-to-band tunneling. Both devices can be configured as an n-type and p-type device based on the biasing. This chapter explains the working and performance comparison of RFET and RTFET in detail with the help of technology computer-aided design (TCAD) simulations. Further, the potential and current models of a single-gated RFET and double-gated RTFET are presented in this chapter. The presented analytical models are compared and verified with TCAD simulations. The potential in the channel regions of RFET and RTFET is modeled by solving a two-dimensional (2D) Poisson's equation. Because the working principle of both devices is different, two different formulas are utilized for modeling the current in the device. The current model for the RFET is developed by integrating Landauer's formula, whereas the current model for RTFET is obtained by integrating band-to-band generation rate over the tunneling volume. The procedure, technique, and assumptions followed to obtain the potential and current models of RFET and RTFET are detailed in this chapter.

The temperature effects of both gate-all-around polycrystalline silicon nanowire (GAA poly-Si NW) junctionless (JL) and inversion mode (IM) transistor devices at various temperatures (77–410 K) were investigated. The electrical characteristics of these devices, such as subthreshold swing (SS), threshold voltage (Vth), and drain-induced barrier lowering (DIBL), were also characterized and compared in this study. Moreover, JL devices with different doping concentrations at various temperatures were also discussed. Both Vth and Ion showed significant doping concentration dependences for JL devices with doping concentrations of 1 × 1019 and 5 × 1019 cm−3. However, the electrical characteristics of JL devices showed less thermal sensitivity when the doping concentration reached 1020 cm−3.

In this work, we revisit the requirement of higher channel doping (≥1019 cm−3) in junctionless (JL) double gate MOSFETs. It is demonstrated that moderately doped (1018 cm−3) ultra low power (ULP) JL transistors perform significantly better than heavily doped (1019 cm−3) devices. JL MOSFETs with moderate doping results in the spreading out of carriers across the entire silicon film instead of being localized at the center of the film. This improves gate controllability leading to higher on–off current ratio and lower intrinsic delay for ULP subthreshold logic applications. Additional benefits of using a channel doping concentration of 1018 cm−3 instead of conventional heavily doped design is the significant reduction in threshold voltage sensitivity values (by ∼70–90%) with respect to film thickness and gate oxide thickness. Further improvement in ULP performance metrics can be achieved by limiting the source/drain implantation away from the gate edge. This design, specifically for ULP, allows the requirement of gate workfunction to be reduced from p+-poly (∼ 5.1 eV) to near about midgap values (∼ 4.8 eV). On–off current ratio and intrinsic delay for optimized JL devices are compared for low standby power projections of the technological roadmap. A 6T-SRAM cell operating at 0.8 V with 25 nm JL devices exhibits a static noise margin of 151 mV with gate workfunction offset of 0.2 eV with respect to midgap value (4.72 eV). The results highlight new viewpoints for realizing improved low power JL transistors.

The detrimental lateral band-to-band tunneling (L-BTBT) governing the OFF-state performance of the junctionless (JL) FETs is more pronounced in emerging Nanotube (NT) transistor architectures. This restricts the scaling of NT JLFETs irrespective of their ultimate electrostatic gate control due to additional core gate. Therefore, in this paper, we propose a symmetric intrinsic pocketed Pi-NT JLFET which has narrow intrinsic pockets on both sides of the channel region leading to a diminished L-BTBT induced lateral parasitic BJT action in the emerging NT JLFETs. Using calibrated 3-D simulations, we demonstrate that the incorporation of an intrinsic pocket decreases the OFF-state current by around 2 orders of magnitude in the Pi-NT JLFET for a gate length of 20 nm, leading to a significant ON-state to OFF-state current ratio ( $I_{\text{ON}}/I_{\text{OFF}}$ ) of 108. Furthermore, we also show an improvement in the performance of the emerging NT junctionless accumulation mode (JAM) FETs which exhibits a degraded performance compared to NT JLFETs due to enhanced L-BTBT irrespective of their higher ON-state current. The inclusion of the intrinsic pockets in NT JAMFET (Pi-NT JAMFET) reduces the L-BTBT originated OFF-state by 3 orders of magnitude for a gate length of 20 nm leading to an impressive $I_{\text{ON}}/I_{\text{OFF}}$ ratio of 108. Moreover, the proposed Pi-NT JLFET and Pi-NT JAMFET exhibit an impressive $I_{\text{ON}}/I_{\text{OFF}}$ ratio of ~ 108 and 106, respectively, with more than 4 orders of remarkable reduction in the leakage current even when the gate length is scaled to 10 nm. Additionally, the proposed architectures exhibit lower sensitivity to the gate length modulation unlike their conventional counterpart. The Pi-NT transistors exhibit superior immunity against the short channel effects of threshold-voltage roll-off due to the reduced electrostatic source/channel-to-drain coupling. Furthermore, we show that incorporating gate engineering of the dual-material gate (DMG) further enhances the performance of the Pi-NT transistor. The DMG-Pi-NT transistors exhibit an enhanced $I_{\text{ON}}/I_{\text{OFF}}$ ratio ~ 1011 achievable with the proper tuning of the dual metal gate work functions. Thus, our proposed device architecture enhances the scalability of the NT JLFETs and NT JAMFETs for realizing them in the future technology nodes.

In order to analyze the performance of surrounding-gate Nanowire (SG-NW) junctionless (JL) FET under various temperatures, this paper introduces the incomplete ionization to modify the original model and presents a new precise model considering temperature effect. By solving surface potential based model, the electronic characteristics are compared with the results of the numerical simulation from three-dimensional device simulation software ISE TCAD.

In this study, we investigated the impact of random dopant fluctuation (RDF) on junctionless (JL) fin field-effect transistors (FinFETs) with ferroelectric (FE) negative capacitance (NC) effect. The RDF-induced variations were captured by using built-in Sano methodology in three-dimensional technology computer-aided design (TCAD) simulation. Compared to the regular JL-FinFETs, the variations in JL-FinFETs with NC effect (NCJL-FinFETs) was observed to be less via statistical Monte Carlo analysis, which further enhanced its performance as well. The evaluation and estimation of threshold voltage (V T ), ON-state current (I on ), OFF-state current (I off ), and subthreshold swing (SS) by different FE layer thicknesses indicated reduction in the standard deviations of V T (δV T ) and I on (δI on ) by 34.7% and 7.08%, respectively; the OFF-state current and its standard deviation shrank by approximately three orders of magnitude than the JL-FinFET counterpart. Although δSS was not monotonous, the SS was significantly improved to sub-60 mV/decade. To sum up, the regular JL-FinFETs containing the FE layer as NC effect not only improved the electrical performance, but also led to the resilience of the RDF-induced statistical variability.