Carrier Recovery Algorithms and Real-time DSP Implementation for Coherent Receivers

Carrier recovery is an important building block for modern coherent optical communication systems. This chapter first introduces the concept of carrier recovery and the challenges faced. Before diving into the detail of hardware‐efficient carrier recovery algorithms, the chapter gives a brief introduction to the Cramer‐Rao lower bound (CRLB), CRLB provides us with a more fundamental way to evaluate the effectiveness of various carrier recovery algorithms. Before proceeding to discuss various frequency offset estimation schemes, the chapter focuses on several hardware‐efficient phase estimation algorithms by assuming that the frequency offset has been largely compensated‐for before phase recovery. It describes in more detail three hardware‐efficient multistage phase recovery algorithms that have been demonstrated for high‐SE 100Gb/s and beyond transmission experiments. These are the multistage hybrid blind phase search (BPS)/maximum likelihood (ML) phase recovery algorithm, the hybrid phase‐locked loop (PLL)/ML algorithm, and the training‐assisted two‐stage BPS/ML algorithm.

We propose a polarity decision carrier recovery algorithm that is useful for carrier acquisition in high order-QAM (quadrature amplitude modulation). The PD (phase detector) output and its variance characteristics are mathematically derived and the simulation results are presented. We design a carrier recovery loop with this polarity decision PD and ATC (automatic transfer-mode controller), which is proposed to detect a proper time for mode change and to yield fine phase tracking error in the steady state. While the conventional DD (decision directed) algorithm can only acquire frequency offsets of less than /spl plusmn/10 kHz, the proposed carrier recovery algorithm can acquire up to /spl plusmn/200 kHz without AFC (automatic frequency control). We show the RMS (root mean square) phase error performance using the proposed carrier recovery PLL (phase locked loop).

A refined phase estimation based parallel carrier recovery algorithm for high speed wireless communication systems is proposed in this paper. This parallel algorithm is based on a serial DPLL (digital phase locked loop) carrier recovery feedback architecture and a novel refined phase estimation module. To archive high speed communication, parallelization of serial DPLL carrier recovery algorithm is presented; to guarantee high accuracy, a refined phase estimation design is proposed. A 32 parallel baseband simulation model of 16QAM modulation is performed on MATLAB platform to validate the proposed algorithm. Simulation results demonstrate that the performance loss of EVM (Error Vector Magnitude) introduced by the proposed algorithm is less than 0.3%, which is only half of the traditional coarse compensation algorithm.

This paper presents an all digital DS-CDMA upstream transmitter arid a head-end baseband receiver for upstream cable/HFC networks. The upstream transmitter supports frequency agility of the carrier, QPSK and QAM constellations up to 64QAM, variable symbol rates from 160kchip/s to 5.12Mchip/s increasing by power of two, and direct-digital up-conversion to achieve accurate amplitude and phase of modulation. The transmitter consists of pulse shaping filter, half-band filter, cascaded integrator-comb (CIC) filter, and inverse SINC filter. The all digital head-end baseband receiver supports programmable quadrature amplitude modulation up to 64QAM. Fast timing and carrier recovery algorithms are adopted for burst mode transmission. Code acquisition can be achieved within 2 symbols, and the carrier acquisition can be achieved within 31 symbols. All digital timing recovery is designed with /spl plusmn/200ppm symbol timing offset tolerance and the carrier recovery can compensate /spl plusmn/100ppm of carrier frequency offset.

Video has become an interactive medium of communication in everyday life. The sheer volume of video makes it extremely difficult to browse through and find the required data. Hence extraction of key frames from the video which represents the abstract of the entire video becomes necessary. The aim of the video shot detection is to find the position of the shot boundaries, so that key frames can be selected from each shot for subsequent processing such as video summarization, indexing etc. For most of the surveillance applications like video summery, face recognition etc., the hardware (real time) implementation of these algorithms becomes necessary. Here in this paper we present the architecture for simultaneous accessing of consecutive frames, which are then used for the implementation of various Video Shot Detection algorithms. We also present the real time implementation of three video shot detection algorithms using the above mentioned architecture on FPGA (Field Programmable Gate Arrays).

Vision-correcting near-eye displays are necessary concerning the large population with refractive errors. However, varifocal optics cannot effectively address astigmatism (AST) and high-order aberration (HOAs); freeform optics has little prescription flexibility. Thus, a computational solution is desired to correct AST and HOA with high prescription flexibility and no increase in volume and hardware complexity. In addition, the computational complexity should support real-time rendering. We propose that the light field display can achieve such computational vision correction by manipulating sampling rays so that rays forming a voxel are re-focused on the retina. The ray manipulation merely requires updating the elemental image array (EIA), being a fully computational solution. The correction is first calculated based on an eye's wavefront map and then refined by a simulator performing iterative optimization with a schematic eye model. Using examples of HOA and AST, we demonstrate that corrected EIAs make sampling rays distributed within ±1 arcmin on the retina. Correspondingly, the synthesized image is recovered to nearly as clear as normal vision. We also propose a new voxel-based EIA generation method considering the computational complexity. All voxel positions and the mapping between voxels and their homogeneous pixels are acquired in advance and stored as a lookup table, bringing about an ultra-fast rendering speed of 10 ms per frame with no cost in computing hardware and rendering accuracy. Finally, experimental verification is carried out by introducing the HOA and AST with customized lenses in front of a camera. As a result, significantly recovered images are reported.

The GHKSS nonlinear projective filtering method as a representative of nonlinear time series analysis, has been used as a “posterior filtering” noise reduction technique in a range of applications. Compared to Fourier and model-based techniques it has the advantage of reducing the noise with broadband spectra, without knowledge of the system model. The contamination of time series data with measurement noise may result in an apparent loss of intrinsic dynamical information of the nonlinear systems. A real-time implementation and working principle of the GHKSS algorithm is widely ignored due to its complexity and high computational cost. Here, we present a real-time implementation of this algorithm using a Field Programmable Gate Array (FPGA) and High-level synthesis (HLS) tools. The computational burden is reduced by running the false nearest neighbour (FNN) search and delay estimation part of the GHKSS, on a separate DSP slice using HLS tools. The effect of noise reduction on dynamic preservation using GHKSS was illustrated by estimating the correlation dimension and the maximal Lyapunov exponent of the 3-D Chay model in the chaotic regime. This research is important since the real-time implementation of the GHKSS algorithm will widen its application in nonlinear time series analysis.

Detecting the presence of primary users and ability to find white spaces in the spectrum are the key enablers of the opportunistic communication. This paper analyzes the trade-offs in cyclostationary-based spectrum sensing algorithm implementations in terms of performance, hardware complexity, and power consumption. The evaluation of the algorithm implementations is performed on field-programmable gate arrays. The analysis presented will provide the designer understanding of dependency between algorithm complexity and power consumption, which is inherently limiting factor of implementation feasibility for cognitive mobile devices.

This paper presents an experimental prototype based on a beam for educational purposes for students of university. The platform is conditioned easily by students for experiments different, opening many new possibilities for experiments in mechanics of material courses. The approach is to apply the theory of mechanic of materials using the prototype by a real-time implementation. This estimates and plots shear-force and bending moment diagrams for a beam with concentrated loads. The implemented algorithm allows to estimate maximum moment and deflection on a specific point. The platform is easy to interface with any computer giving new possibilities for practical assignments in courses of Mechanical, Mechatronics, Architecture and Civil engineering. Also, we present application examples with a beam with two supports and a Cantilever beam that validate the performance of the prototype with students during practices.

Massive multiple-input and multiple-output systems combined with hybrid beamforming technique is a key approach to achieve high data rate and extended cell coverage in the fifth generation (5G) cellular networks . Specifically, the precoding for analog/digital hybrid beamforming technique is absolutely essential for millimeter-wave (mm-wave) frequency based transmission for 5G, simply because the technique reduces hardware complexity and energy consumption for high-frequency design. In order to prove the aforementioned advantages, the present paper will investigate the energy efficiency (EE) and optimization of low complexity hybrid precoding (EELCHP) algorithm to enable the reduction of radio frequency (RF) chains within the base station (BS). The proposed solution will also incorporate high-resolution phase shifters (HRPS) specifically for downlink multi-user mm-wave system. The intelligence within the EELCHP algorithm for hybrid beamforming is based on the fully complex zero-forcing (ZF) precoding mechanism that allowed the maximization of energy efficiency by reducing the RF chains, without affecting the potentially increasing number of antennas. In addition, maximum EE is possible by eliminating the nonlinear concave fractional issue based on the Lagrange duality method. During the simulation process of the proposed method, we further realized that hardware complexity and power consumption can be reduced by allowing the RF chains to select only one beam per switch within the beamforming solution. Furthermore, with the implementation of EELCHP algorithm, more energy is saved due to low complexity system by reducing the required RF chain.

An efficient compression of hyperspectral images on-board satellites is mandatory in current and future space missions in order to save bandwidth and storage space. Reducing the data volume in space is a challenge that has been faced with a twofold approach: to propose new highly efficient compression algorithms; and to present technologies and strategies to execute the compression in the hardware available on-board. The Consultative Committee for Space Data Systems (CCSDS), a consortium of the major space agencies in the world, has recently issued the CCSDS 123 standard for multispectral and hyperspectral image (MHI) compression, with the aim of facilitating the inclusion of on-board compression on satellites by the space industry. In this paper, we present a low-complexity feld programmable gate arrays (FPGAs) implementation of this recent CCSDS 123 standard, which demonstrates its main features in terms of compression efficiency and suitability for an implementation on the available on-board technologies. A hardware architecture is conceived and designed with the aim of achieving low hardware occupancy and high performance on a space-qualified FPGA from the Microsemi RTAX family. The resulting FPGA implementation is therefore suitable for on-board compression. The effect of the several CCSDS-123 configuration parameters on the compression efficiency and hardware complexity is taken into consideration to provide flexibility in such a way that the implementation can be adapted to different application scenarios. Synthesis results show a very low occupancy of 34% and a maximum frequency of 43 MHz on a space-qualified RTAX1000S. The benefits of the proposed implementation are further evidenced by a demonstrator, which is implemented on a commercial prototyping board from Xilinx. Finally, a comparison with other FPGA implementations of on-board data compression algorithms is provided.

Computational evaluations are crucial in modern problem-solving when we surpass theoretical algorithms or bounds. These experiments frequently take much work, and the sheer amount of needed resources makes it impossible to execute them on a single personal computer or laptop. Cluster schedulers allow for automatizing these tasks and scale to many computers. But, when we evaluate implementations of combinatorial algorithms, we depend on stable runtime results. Common approaches either limit parallelism or suffer from unstable runtime measurements due to interference among jobs on modern hardware. The former is inefficient and not sustainable. The latter results in unreplicable experiments. In this work, we address this issue and offer an acceptable balance between efficiency, software, hardware complexity, reliability, and replicability. We investigate effects towards replicability stability and illustrate how to efficiently use widely employed cluster resources for parallel evaluations. Furthermore, we present solutions which mitigate issues that emerge from the concurrent execution of benchmark jobs. Our experimental evaluation shows that – despite parallel execution – our approach reduces the runtime instability on the majority of instances to one second.

A VLSI structure for path metric updating in the M algorithm is presented. The architecture is based on the combination of a modified Batcher's (1968) odd-even merging network and a bitonic selection procedure. A feature of the trellis structure allows to replace an existing solution based on two 2M-item sorting operations by three M-item sorting operations with an additional one-layer bitonic merge. These three sorting networks and the bitonic merging procedure permit a reduction of up to 50% in hardware complexity.

The growing demand for electricity, integration of renewable energy sources, and recent advances in power electronics have driven the development of HVDC systems. Multi-terminal HVDC (MTDC) grids, enabled by Voltage Source Converters (VSCs), provide increased operational flexibility, including the ability to reverse power flow and independently control both active and reactive power. However, fault propagation in DC grids occurs more rapidly, potentially leading to significant damage within milliseconds. Unlike AC systems, HVDC systems lack natural zero-crossing points, making fault isolation more complex. This paper presents the implementation of a wavelet-based protection algorithm to detect faults in a four-terminal VSC-HVDC grid, modelled in MATLAB and SIMULINK. The study considers several fault scenarios, including two internal DC pole-to-ground faults, an external DC fault in the load branch, and an external AC fault outside the protected area. The discrete wavelet transform, using Symlet decomposition, is applied to classify faults based on the wavelet entropy and sharp voltage and current signal variations. The algorithm processes the decomposition coefficients to differentiate between internal and external faults, triggering appropriate relay actions. Key factors influencing the algorithm’s performance include system complexity, fault location, and threshold settings. The suggested algorithm’s reliability and suitability are demonstrated by the real-time implementation. The results confirmed the precise fault detection, with fault currents aligning with the values in offline models. The internal faults exhibit more entropy than external faults. Results demonstrate the algorithm’s effectiveness in detecting faults rapidly and accurately. These outcomes confirm the algorithm’s suitability for a real-time environment.

This paper presents a real-time implementation of the QCELP speech coder which has been chosen as digital cellular standard in North America and Korea. A real-time implementation of QCELP algorithm can be realized using 16-bit fixed point digital signal processor. The principle of QCELP algorithm and real-time implementation on fixed point DSP chip are addressed. The paper also discusses the finite word-length effects and considers the methods to reduce the effects through fixed point C simulation. In addition to speech service in CDMA Mobile System, the implementation of data service(be1ow 4.8kbps) by speech coder bypass operation is presented.