CausalTuner: Will Causality Help High-Dimensional EDA Tool Parameter Tuning

The rapid increase in the complexity of Very Large-Scale Integration (VLSI) systems, along with continuous semiconductor scaling, has made conventional design and automation techniques increasingly time-consuming and resource-intensive. AI-driven VLSI design and automation have emerged as a powerful paradigm that applies machine learning, deep learning, and data-driven optimization to improve the efficiency, accuracy, and scalability of Electronic Design Automation (EDA) tools. By learning from large volumes of design data, AI techniques enable intelligent decision-making across key stages of the VLSI design flow, including architecture exploration, logic synthesis, placement and routing, timing analysis, power optimization, and verification. This chapter provides an overview of AI-based methodologies used in modern VLSI automation, emphasizing predictive modeling and reinforcement learning for faster design cycles and improved performance, power, and area (PPA) metrics. It also discusses challenges such as data quality, model interpretability, and tool integration, highlighting AI’s critical role in next-generation VLSI systems.

In modern IC design, circuit designers often need to manually operate and move data among different EDA (Electronic Design Automation) tools. If these tools were installed in separate computers, due to the license and system requirements, the design flow will be frequently interrupted, to handle the dreary data movement work, and the design efficiency will thus be reduced. To alleviate the above problem, a seamless and efficient design flow would be a must. The aim of this paper is to propose a service-oriented integrated EDA environment that can improve the smoothness of the design flow and consequently increase the overall design productivity. In our approach, a multi-agent framework based on JADE platform is used to manage distributed EDA tools, which are encapsulated as agent services. Mobile agents are allowed to autonomously and concurrently migrate among computers to access services for IC designers. To facilitate that, a scripting language is designed for mobile agents to allocate tasks, cooperate with each other, and select appropriate services. To demonstrate the feasibility of our method, an Integrated Circuit Design Cycle Assistant System (ICDCAS) for simplifying the manual operations in IC design cycles is developed by combining two EDA tools: ModelSim and Xilinx ISE. The implemented system proves to have the features of time saving and being free of mistakes incurred by manually operating and configuring the sophisticated EDA tools.

This paper concentrates on the development of system-on-chip for the decryption algorithm in the advanced encryption standard (AES). This method includes the transformation of cipher text into plain text and consists of 4 sub-tasks based on the resolution. In this work, the 128-bit resolution is utilized to perform 10 rounds of transformation with the round key added at every round generated by the key expansion algorithm. Though there are many cryptography algorithms, the AES is simple, secure, faster in operation, and easy to develop compared to the others. The system-on-chip (SOC) design for the decryption of the AES depends on the synthesizable hardware description language (HDL) code development for all 10 rounds of processes with the key expansion algorithm. The lookup tables (LUTs) are used for the inverse S-box in the HDL code. The proposed SOC is designed using the Cadence electronic design automation (EDA) tools by making use of the synthesized HDL code for the proposed methods and analyzed for the very large-scale integration (VLSI) parameters.

Provision of free, downloadable industry-standard reconfigurable hardware EDA tools is a growing and welcome trend. Low cost, ever-more-complex FPGA-based embedded system development platforms with host interface control are becoming more readily available. This paper describes a series of structured VHDL workshop modules which use the Xilinx ISE Webpack/ModelsimXE electronic design automation (EDA) tools and Digilent Spartan-3 hardware development system. The described course implements an extendable embedded system, which performs a selection of image and audio processing applications, controlled by a host graphical user interface (GUI). A formal structured design, documentation and test methodology is incorporated throughout the course. Enhancements to EDA tool VHDL and diagram creation wizard support are proposed to aid VHDL capture automation and design visualisation. Improved student understanding and achievement level in VHDL programming, digital embedded system design techniques and FPGA implementation has resulted

Recent developments in EDA tools for power electronics modules have led to simultaneous analysis and optimization of package features with regard to electro-thermal and thermo-mechanical aspects. In this work, two of these EDA tools, PowerSynth and ParaPower, are linked together with a software application programming interface (API) to rapidly explore a combined electro-thermo-mechanical design space and present the user with co-optimized solutions and tradeoffs in a fraction of the time consumed using traditional analysis methods. An overview of this co-design process and its advantages over that of the traditional, iterative approach is presented along with an explanation of the methods used by the respective tools for analysis. Finally, additional considerations and constraints are introduced that ensure manufacturing feasibility and reliable operation at high voltages. A case study in co-design using these tools has been proposed for the final paper.

Advanced electronic design automation (EDA) tools, with their simulation, modeling, design rule checking, and optical proximity correction capabilities, have facilitated the improvement of first pass wafer yields. While the data produced by these tools may have been processed for optimal wafer manufacturing, it is possible for the same data to be far from ideal for photomask manufacturing, particularly at lithography and inspection stages, resulting in production delays and increased costs. The same EDA tools used to produce the data can be used to detect potential problems for photomask manufacturing in the data. A production implementation of automated photomask manufacturing rule checking (MRC) is presented and discussed for various photomask lithography and inspection lines. This paper will focus on identifying data which may cause production delays at the mask inspection stage. It will be shown how photomask MRC can be used to discover data related problems prior to inspection, separating jobs which are likely to have problems at inspection from those which are not. Photomask MRC can also be used to identify geometries requiring adjustment of inspection parameters for optimal inspection, and to assist with any special handling or change of routing requirements. With this foreknowledge, steps can be taken to avoid production delays that increase manufacturing costs. Finally, the data flow implemented for MRC can be used as a platform for other photomask data preparation tasks.

Digital Electronic Design Automation (EDA) tools have seen a remarkable improvement over the last decade. In addition to providing good documentation, their ability to simulate a design provides immense convenience in optimizing a design and in examining what-if scenarios which would otherwise be very time-consuming, expensive, and even impossible using hardware. This paper begins with an overview of EDA tools and related issues. Next, it discusses the implementation of an EDA laboratory established with funding from the National Science Foundation. Details of four experiments and an evaluation of the EDA tools used in the undergraduate curriculum have been presented.

Scaling complementary metal oxide semiconductor (CMOS) devices has been a method used very successfully over the last four decades to improve the performance and the functionality of very large scale integrated (VLSI) designs. Still, scaling is heading towards several fundamental limits as the feature size is being decreased towards 10 nm and less. One of the challenges associated with scaling is the expected increase of static and dynamic parameter fluctuations and variations, as well as intrinsic and extrinsic noises, with significant effects on reliability. Therefore, there is a clear, growing need for electronic design automation (EDA) tools that can predict the reliability of future massive nano-scaled designs with very high accuracy. Such tools are essential to help VLSI designers optimize the conflicting tradeoffs between area-power-delay and reliability requirements. In this paper, we introduce an EDA tool that quickly and accurately estimates the reliability of any CMOS gate. The tool improves the accuracy of the reliability calculation at the gate level by taking into consideration the gate's topology, the reliability of the individual devices, the applied input vector, as well as the noise margins. It can also be used to estimate the effect on different types of faults and defects, and to estimate the effects of enhancing the reliability of individual devices on the gate's overall reliability.

Power flow calculation is fundamental for a wide variety of power system applications. The computation accuracy and efficiency of power flow calculation is critical for downstream large-scale power system real time applications. Using very large-scale integrated (VLSI) circuit to model power system will keep power system characteristics with less assumptions and higher fidelity. And power system VLSI circuit model has a great potential for high fidelity real time transient simulation. As a preliminary exploration, this paper uses Electronic Design Automation (EDA) tool to model power system as an integrated circuit and calculate the power flow using the integrated circuit simulator. The power flow calculation accuracy and efficiency of the proposed approach are verified and demonstrated by case study on the IEEE standard systems and real large-scale power systems.

The incorporation of electronic design automation (EDA) tools in engineering curricula will better prepare graduates to enter the modern engineering marketplace. The engineering courses appropriate for EDA introduction are discussed, as are the tools themselves and their sources. Issues of computing platform, operating system, and tool suites are presented. Internet accessible public domain documents are provided to aid engineering schools in setting up a comprehensive EDA curriculum.

The application of Machine Learning (ML) in Electronic Design Automation (EDA) for Very Large-Scale Integration (VLSI) design has garnered significant research attention. Despite the requirement for extensive datasets to build effective ML models, most studies are limited to smaller, internally generated datasets due to the lack of comprehensive public resources. In response, we introduce EDALearn, the first holistic, open-source benchmark suite specifically for ML tasks in EDA. This benchmark suite presents an end-to-end flow from synthesis to physical implementation, enriching data collection across various stages. It fosters reproducibility and promotes research into ML transferability across different technology nodes. Accommodating a wide range of VLSI design instances and sizes, our benchmark aptly represents the complexity of contemporary VLSI designs. Additionally, we provide an in-depth data analysis, enabling users to fully comprehend the attributes and distribution of our data, which is essential for creating efficient ML models. Our contributions aim to encourage further advances in the ML-EDA domain.

As the semiconductor industry moves into the next generation sub-nanometer design the quality of the electronic design automation (EDA) tools becomes more critical. With shrinking market windows and increasing time to market constraints the designers need reliable and robust EDA software tools to ensure that the design is manufacturable with an acceptable yield. This paper develops a balanced scorecard for implementing systemic quality in an EDA organization.

Over the course of 60 years, since the invention of the integrated circuit (IC), exponential improvements in cost, performance and power consumption were observed. Such advances have been strongly linked with the continuous reduction of the dimensions in manufactured ICs, but this trend has shown decreasing benefits as fundamental limits are reached. Notice that such tiny devices have increased variability, which generates unpredictable variations in the behavior of the manufactured devices. These uncertainties are typically addressed by defining margins on the clock period, estimated during the design phase. However, the overly conservative margins produce significant degradations in performance. Additionally, the evolution that enabled circuits with increasingly higher density of components, also resulted in an extremely complex IC design. At every step, electronic design automation (EDA) tools are challenged to handle this increasing complexity, requiring more powerful techniques to comply with the specification constraints within an affordable runtime. This thesis investigates alternatives in order to improve power, performance, area, and cost, using established IC manufacturing technologies. Advances in EDA are proposed in three distinct topics: area minimization using Boolean methods, area and delay reduction for designs based on fieldprogrammable gate array (FPGA), and an alternative clocking scheme to reduce timing margins. The first contribution consists of a technology-independent method for area minimization of combinational logic. Local optimization is applied on and-inverter graphs (AIGs), performing multi-output Boolean decomposition using two-literal divisors, targeting node count reduction. The second contribution regards two methods targeting technology mapping of FPGAs. On one hand, a functional decomposition approach, which uses the support size as cost function, exploring the inherent characteristics of FPGAs. On the other hand, an approach for recursive remapping, which reduces the structural bias of the subject graph, uses the mapping results as cost function, and obtains significant reductions in area and delay. The third contribution evaluates the dynamic variability mitigation and simplification of power delivery networks (PDNs) using an adaptive clocking scheme based on ring oscillator clocks (ROCs). The impact of the PDN parameters and ROC location is investigated, showing potential improvements in performance, leakage power and cost. A lo largo de los 60 años desde la invención del circuito integrado (CI), se han producido mejoras exponenciales en su coste, rendimiento y consumo de energía. Ese progreso esta fuertemente vinculado a la reducción continua de las dimensiones de fabricación de los circuitos integrados, pero esta tendencia ha ido mostrando menos beneficios a medida que se alcanzan límites fundamentales. Estos dispositivos minúsculos tienen una mayor variabilidad, lo que genera variaciones impredecibles en el comportamiento de los dispositivos fabricados. Estas incertidumbres generalmente se abordan mediante la definición de márgenes en el período de reloj, estimado durante la fase de diseño. Sin embargo, márgenes excesivamente conservadores producen degradaciones significativas en el rendimiento. Además, la evolución que permitió crear circuitos con una densidad de componentes cada vez mayor, también incrementado la complejidad de los CI. En cada paso del proceso de diseño, las herramientas de automatización de diseño electrónico (EDA) se enfrentan al desafío de manejar esta complejidad creciente, lo que requiere técnicas más potentes para cumplir con las restricciones impuestas por las especificaciónes dentro de un tiempo de ejecución asequible. Esta tesis investiga alternativas para mejorar el consumo de energía, el rendimiento, el área y el coste, utilizando las tecnologías de fabricación de CI ya establecidas. Los avances en EDA se proponen en tres temas distintos: minimización de área usando métodos booleanos, reducción de retardo y área para diseños basados en matrices de puertas programables (FPGA), y un esquema de reloj alternativo para reducir los márgenes de tiempo excesivamente conservadores. La primera contribución consiste en un método independiente de tecnología para minimizar el área de la lógica combinacional. Se aplica optimización local en grafos de AND-inversor, utilizando una descomposición Booleana de múltiples salidas con divisores de dos literales, con el objetivo de reducir la cantidad de nodos. La segunda contribución propone dos métodos para el mapeo tecnológico de los FPGA. Por un lado, un método de descomposición funcional, que utiliza el tamaño del soporte como función de coste, explorando las características inherentes de los FPGA. Por otro lado, un método de mapeo recursivo, que reduce la distorsión estructural del grafo sujeto, utiliza los resultados del mapeo como función de coste y obtiene reducciones significativas en área y retardo. La tercera contribución evalúa la mitigación de la variabilidad dinámica y la simplificación de la red de suministro de energía (PDN) utilizando un esquema de reloj adaptativo basado en un oscilador en anillo (ROC). Se investiga el impacto de los parámetros de la PDN y la ubicación del ROC, mostrando mejoras potenciales en el rendimiento, consumo estático y coste.

With Moore's law in effect, as the complexity of digital electronic circuits increases, the amount of time spent by the electronic design automation (EDA) tools to design such circuits also increases. It brings us to the point, where we need to improve the performance of EDA algorithms to fulfil the present and the future requirements of the EDA industry. Out of many algorithms used by these tools, Breadth First Traversal (BFT) is one of the most commonly used algorithms to traverse the gates of electronic circuits. In this paper, we present a new simple, fast and parallelizable BFT algorithm for sparse graphs, named H-BFT. We show that the CPU implementation of H-BFT is about 75× faster than the CPU implementation of the state of the art, the Sparse Matrix-Vector Product (SMVP) based BFT. Further, with the new features introduced by NVIDIA in their GPUs, we have accelerated both the state of the art SMVP based BFT implementation and our new H-BFT implementation. The best speedups we achieved via these accelerations are 180× and 25× for the SMVP-BFT and H-BFT respectively.

This paper presents a hardware-accelerated Advanced Encryption Standard (AES) implementation featuring an 11-stage pipelined architecture and an optimized subkey generation scheme for enhanced performance. This design is implemented in Verilog and verified through waveform analysis. Operating at a maximum clock frequency of 100 MHz, our implementation achieves significant efficiency. The final design occupies an area of 1.44 mm2 and consists of 32,424 standard cells, with a power consumption of 32 mW at the typical corner. Furthermore, the entire design flow, from synthesis to layout (GDSII), is achieved using OpenLane, an open-source Electronic Design Automation (EDA) tool. This democratization of hardware design empowers a wider range of participants, particularly students and researchers, to efficiently implement their designs and gain hands-on experience without the constraints of expensive commercial tools. This fosters innovation and accelerates progress by allowing a broader community to contribute to technological advancements. Index Terms—OpenLane, Open-source , EDA, Pipelined AES, RTL to GDSII