Chapter 4 - DSP ASIP Design Flow

The author describes the new CPU benchmark suites from the Standard Performance Evaluation Corporation (SPEC). The author describes the reasons for the release, and analyzes and compares new suites with the SPEC Release 1 benchmark suite. The new benchmark CPU suites are CINT2.0 (integer) and CFP2.0 (floating-point). CINT2.0 and CFP2.0 replace the SPEC Release 1 benchmark suite. The new suites provide a wider 'SPECtrum' of performance characterization by adding new application benchmarks. >

Modern High Performance Computing (HPC) sys-tems are built with innovative system architectures and novel programming models to further push the speed limit of computing. The increased complexity poses challenges for performance portability and performance evaluation. The Standard Perfor-mance Evaluation Corporation (SPEC) has a long history of producing industry-standard benchmarks for modern computer systems. SPEC's newly released SPEChpc 2021 benchmark suites, developed by the High Performance Group, are a bold attempt to provide a fair and objective benchmarking tool designed for state-of-the-art HPC systems. With the support of multiple host and accelerator programming models, the suites are portable across both homogeneous and heterogeneous architectures. Different workloads are developed to fit system sizes ranging from a few compute nodes to a few hundred compute nodes. In this work we present our first experiences in performance benchmarking the new SPEChpc2021 suites and evaluate their portability and basic performance characteristics on various popular and emerging HPC architectures, including x86 CPU, NVIDIA GPU, and AMD GPU. This study provides a first-hand experience of executing the SPEChpc 2021 suites at scale on production HPC systems, discusses real-world use cases, and serves as an initial guideline for using the benchmark suites.

Years of planning went into the preparation of ICPE 2020 in Edmonton. There was great excitement in bringing ICPE back to North America after a while and great anticipation for productive interactions between the participants of ICPE and members of the various SPEC working groups. But, alas, the only certain thing about life is its uncertainty. The arrival of the COVID-19 pandemic led to the cancelation of the face-to-face conference in Edmonton. ICPE proceeded with the publication of these proceedings and with the availability of video presentations and slides linked to the conference program in the website. The great program for ICPE 2020 was made possible thanks to the many authors that submitted contributions to the advancement of performance modeling and engineering and many other related topics. We were anticipating great interest in the strong line of keynote speakers. The Canadian-based line up is a coincidence but it would have been a great way to celebrate the contributions from Canadian universities in this area. Gail Murphy from the University of British Columbia planned to share her experiences in increasing the productivity of software development. Sebastian Fishmeister from the University of Waterloo would talk about what they learned from mining traces from the design of embedded software systems. Ahmed Hassan from Queens University intended talk about assessing and testing large-scale software systems. There is much work that goes into putting together a complex program such as ICPE. Besides the contributing authors and presenters, many volunteering hours were dedicated by chairs, programcommittee members, local organizers, local volunteers, steering-committee members and many others. On behalf of the ICPE community we thank you all for your effort and dedication. We thank for the generous sponsorship from the Standard Performance Evaluation Corporation (SPEC). Even though ICPE could not go ahead as planned because of the 2020 pandemic, we hope that the availability of video presentations and the publication of these proceedings will lead to productive online interactions between researchers.

This paper presents a new 32-b reduced instruction set computer/digital signal processor (RISC/DSP) architecture which can be used as a general purpose microprocessor and in parallel as a 16-/32-b fixed-point DSP. This has been achieved by using RISC design principles for the implementation of DSP functionality. A DSP unit operates in parallel to an arithmetic logic unit (ALU)/barrelshifter on the same register set. This architecture provides the fast loop processing, high data throughput, and deterministic program flow absolutely necessary in DSP applications. Besides offering a basis for general purpose and DSP processing, the RISC philosophy offers a higher degree of flexibility for the implementation of DSP algorithms and achieves higher clock frequencies compared to conventional DSP architectures. The integrated DSP unit provides instruction set support for highly specialized DSP algorithms. Subword processing optimized for DSP algorithms has been implemented to provide maximum performance for 16-b data types. While creating a unified base for both application areas, we also minimized transistor count and we reduced complexity by using a short instruction pipeline. A parallelism concept based on a varying number of instruction latency cycles made superscalar instruction execution superfluous.

Applying a methodology to develop user eXperience heuristics

Breakthrough streaming applications such as virtual reality, augmented reality, autonomous vehicles, and multimedia demand for high-performance and power-efficient computing. In response to this ever-increasing demand, manufactures look beyond the parallelism available in Chip Multi-Processors (CMPs), and more toward application-specific designs. In this regard, ACCelerator (ACC)-based heterogeneous CMPs (ACMs) have emerged as a promising platform. An ACMP combines application-specific HW ACCelerators (ACCs) with General Purpose Processor(s) (GPP) onto a single chip. ACCs are customized to provide high-performance and power-efficient computing for specific compute-intensive functions and GPP(s) runs the remaining functions and controls the whole system. In ACMP platforms, ACCs achieve performance and power benefits at the expense of reduced flexibility and generality for running different workloads. Therefore, manufactures must utilize several ACCs to target a diverse set of workloads within a given application domain.

Popular public key algorithms such as RSA and Diffie-Hellman key exchange, and more advanced cryptographic schemes such as Paillier’s and Damgard-Jurik’s algorithms (with applications in private information retrieval), require efficient modular multiplication with large integers of size at least 1024 bits. Montgomery multiplication algorithm has proven successful for modular multiplication of large integers. While general purpose multi-core processors have become the mainstream on desktop as well as portable computers, utilization of their computing resources have been largely overlooked when it comes to performing computationally intensive cryptographic operations. In this work, we propose a new parallel Montgomery multiplication algorithm which exhibits up to 39 % better performance than the known best serial Montgomery multiplication variant for the bit-lengths of 2048 or larger. Furthermore, for bit-lengths of 4096 or larger, the proposed algorithm exhibits better performance by utilizing multiple cores available. It achieves speedups of up to 81 %, 3.37 times and 4.87 times for the used general-purpose microprocessors with 2, 4 and 6 cores, respectively. To our knowledge, this is the first work that shows with actual implementation results that Montgomery multiplication can be practically and scalably parallelized on general-purpose multi-core processors.

In the last years, the large availability of information and knowledge models formalized by ontologies has demanded effective and efficient methodologies for reusing and integrating such models in global conceptualizations of a specific knowledge or application domain. The ability to effectively and efficiently perform knowledge reuse is a crucial factor in the development of ontologies, which are a potential solution to the problem of information standardization and a viaticum towards the realization of knowledge-based digital ecosystem. In this paper, an approach to ontology reuse based on heterogeneous matching techniques will be presented; in particular, we will show how the process of ontology building will be improved and simplified, by automating the selection and the reuse of existing data models to support the creation of digital ecosystems. The proposed approach has been applied to the food domain, specifically to food production.

Most fully automatic segmentation approaches target a single anatomical structure in a specific combination of image modalities and are often difficult to extend to other modalities and protocols or segmentation tasks. More recently, deep learning-based approaches promise to be readily adaptable to new applications as long as a suitable training set is available, although most deep learning architectures are still tuned towards a specific application and data domain. In this paper, we propose a novel fully convolutional neural network architecture for image segmentation and show that the same architecture with the same learning parameters can be used to train models for 20 different organs on two different protocols, while still achieving segmentation accuracy that is on par with the state-of-the-art. In addition, the architecture was designed to minimize the amount of GPU memory required for processing large images, which facilitates the application to full-resolution whole-body CT scans. We have evaluated our method on the publicly available data set of the VISCERAL multi-organ segmentation challenge and compared the performance of our method with those of the challenge and two recently proposed deep learning-based approaches. We achieved the highest Dice similarity coefficients for 17 out of 20 organs for the contrast enhanced CT scans and for 10 out of 20 organs for the uncontrasted CT scans in a cross-comparison between our method and participating methods.

Streaming languages were originally aimed at streaming architectures, but recent work has shown the stream programming model to be useful in exploiting parallelism on general purpose processors. Current research in mapping stream code onto GPPs deals with load balancing and generating threads based on hardware features. We look into improving problems associated with stream data locality and stream data parallelism on GPPs. We suggest that automatically generating vectorized code for these streaming operations is a potential solution. We use the Brook stream language as our syntax base and augment it to generate vector intrinsics targeting the x86 architecture. This compiler uses both existing and new strategies to transform high-level streaming kernel code into vector instructions without requiring additional annotations. We compare our system's results to existing mapping strategies aimed at using stream code on GPPs. When evaluating performance, we see a wide range of speedups from a few percent to over 2x and discuss the level of effectiveness of using vector code over scalar equivalents in specific application domains.

Many mobile knowledge management (KM) systems have been described in the literature having unique and interesting features, each being inserted into a specific application domain. This fragmentation in the application domain makes it difficult to compare and define a set of core features of mobile KM systems. Analysing and comparing features and strategies of several systems from different application domains makes it possible to identify the core features that form a mobile KM system. Consequently, we may use these core features to define the evaluation and comparison framework of mobile KM systems, regardless of its application domain. The purpose of this work is to define these core features and discuss their importance, through the analysis of six mobile KM systems, highlighting the positive and the negative aspects of the KM processes. The contributions of this work are the framework and the list of core features of mobile KM systems.

Nowadays, a variety of Big Data architectures are emerging to organize the Big Data life cycle. While some of these architectures are proposed for general usage, many of them are proposed in a specific application domain such as smart cities, transportation, healthcare, and agriculture. There is, however, a lack of understanding of how and why Big Data architectures vary in different domains and how the Big Data architecture strategy in one domain may possibly advance other domains. Therefore, this paper surveys and compares the Big Data architectures in different application domains. It also chooses a representative architecture of each researched application domain to indicate which Big Data architecture from a given domain the researchers and practitioners may possibly start from. Next, a pairwise cross-domain comparison among the Big Data architectures is presented to outline the similarities and differences between the domain-specific architectures. Finally, the paper provides a set of practical guidelines for Big Data researchers and practitioners to build and improve Big Data architectures based on the knowledge gathered in this study.

Semantic mediation of observation datasets through Sensor Observation Services

Many mobile knowledge management (KM) systems have been described in the literature having unique and interesting features, each being inserted into a specific application domain. This fragmentation in the application domain makes it difficult to compare and define a set of core features of mobile KM systems. Analysing and comparing features and strategies of several systems from different application domains makes it possible to identify the core features that form a mobile KM system. Consequently, we may use these core features to define the evaluation and comparison framework of mobile KM systems, regardless of its application domain. The purpose of this work is to define these core features and discuss their importance, through the analysis of six mobile KM systems, highlighting the positive and the negative aspects of the KM processes. The contributions of this work are the framework and the list of core features of mobile KM systems.

Chapter 9 - Fuzzy Methods