A 32-b RISC/DSP microprocessor with reduced complexity

Recently the border between DSP processors and general-purpose processors has been diminishing as general-purpose processors have obtained DSP features to support various multimedia applications. This chapter provides a view to general-purpose DSP processors by considering the characteristics of DSP algorithms and identifying important features in a processor architecture for efficient DSP algorithm implementations. Fixed-point and floating-point data paths are discussed. Memory architectures are considered from parallel access point of view and address computations are shortly discussed.

Multipliers play a important role in current signal processing chips like DSP and general purpose processors and applications. In such high performance systems addition and multiplication operations are fundamental and most used arithmetic operations. Some case study shows that more than 70% of DSP algorithms and in microprocessor operations perform addition and multiplication. Hence these operations dominate the execution time. To meet the processing speed demand, the design of multipliers and adders plays a vital role. Low power consumption has consumption has became a major issue in design of multiplier. To reduce the power consumption, the components used in the design must be drastically reduced and in parallel it should not degrade the other performance metric. In this paper we are proposing a new architecture to design multiplier using parallel prefix adders. The Parallel Prefix Adder (PPA) have fast carry generation network and hence they are the fastest types of adder that had been created and developed. Most common types of parallel prefix adder are Brent Kung and Kogge Stone adders. The performances of these two adders in terms of worst case delay and transistor count and power consumption studied and an analysis of the same is presented. Utilizing the same to design and implement the multiplier using PPA is performed in this paper.

This paper analyses the performance of the state-of-the-art media ISA (instruction set architecture) extensions in a general-purpose processor, when executing a video encoder based on an affine motion model. In addition to SIMD (single instruction multiple data) fixed-point instructions, these ISA extensions include SIMD floating-point instructions, special-purpose SIMD fixed-point instructions, and cacheability control instructions. In this study, eight time-consuming kernels of the video encoder were hand-optimized, using instructions in all four instruction categories of these media ISA extensions (the FLP version). These kernels were also hand-optimized using only SIMD fixed-point ISA extensions, without special-purpose instructions (the FXP version). For the FLP version, this study resulted in an average kernel-level speedup of 1.37X and an application-level speedup of 1.11X, compared to the FXP version, and an application-level speedup of 3.41X, compared to the C version.

The RISC-V instruction set has advanced and expanded significantly in recent years. It is an open instruction set architecture (ISA) based on the concept of Reduced Instruction Set Computing (RISC). This article uses Verilog to design a 5-stage pipeline CPU based on RISC-V architecture in Vivado 2022.2. The CPU can execute 38 instructions and optimises its arithmetic logic unit (ALU) by optimising adders, shifters, and multipliers. Next, write a testbench in the simulation software to verify the functionality of the CPU. RTL diagrams and reports are then generated to verify the design structure and evaluate resource allocation. Finally, the CPU successfully executes the instruction and obtains the correct operation result, and the occupation of LUT resources in the shifter part is reduced. This work serves as an important reference for system-on-chip (SoC) and computer design in general. It not only highlights the potential of the RISC-V architecture but also demonstrates the success of optimisation efforts. This paves the way for more powerful and efficient computing systems.

Popular public key algorithms such as RSA and Diffie-Hellman key exchange, and more advanced cryptographic schemes such as Paillier’s and Damgard-Jurik’s algorithms (with applications in private information retrieval), require efficient modular multiplication with large integers of size at least 1024 bits. Montgomery multiplication algorithm has proven successful for modular multiplication of large integers. While general purpose multi-core processors have become the mainstream on desktop as well as portable computers, utilization of their computing resources have been largely overlooked when it comes to performing computationally intensive cryptographic operations. In this work, we propose a new parallel Montgomery multiplication algorithm which exhibits up to 39 % better performance than the known best serial Montgomery multiplication variant for the bit-lengths of 2048 or larger. Furthermore, for bit-lengths of 4096 or larger, the proposed algorithm exhibits better performance by utilizing multiple cores available. It achieves speedups of up to 81 %, 3.37 times and 4.87 times for the used general-purpose microprocessors with 2, 4 and 6 cores, respectively. To our knowledge, this is the first work that shows with actual implementation results that Montgomery multiplication can be practically and scalably parallelized on general-purpose multi-core processors.

Reduced Instruction Set Computer (RISC) is a design which presents better performances, higher speed of operation and favors the smaller and simpler set of instructions. A 16 bit RISC processor designed in this paper is capable of executing more number of instructions with simple design, using the Verilog Hardware Description Language (HDL) and the design is simulated in the Xilinx ISE 14.7 design suite. The main achievement in this work is that the multiplier unit in Arithmetic and Logic Unit (ALU) and Multiplier and Accumulator (MAC) is implemented using Vedic Sutras. The main principle used in Vedic mathematics is to reduce the typical calculation of conventional mathematics to very simple one and hence reduce the overall computational complexity. In addition to these blocks, designed RISC Processor consists of other blocks like Control unit and data path, Register Bank, Program Counter and Memory. The proposed RISC processor is very simple and capable of executing 14 instructions. The achievement in this work is that 44% savings in power in case of MAC and that of 12% in case of ALU is achieved compared to conventional ALU and MAC respectively. Also the delay is reduced by 45% in case of MAC and that of 35% in case of ALU in comparison with conventional ALU and MAC correspondingly. These Vedic MAC and ALU are then integrated with other blocks in processor and 16-bit Vedic processor is developed. This reduces the delay by 34% and saves around 88% power compared to conventional processor. Hence the improvement in speed of operation, reduction in power utilization and less area utilization are the key features of designed RISC processor.

Chapter 4 - DSP ASIP Design Flow

Chapter 11 - The ARM Architecture

Synthetic Aperture Radar (SAR) signal pmcess- ing poses a signijicant challenge due to its very large compu- tation and data storage requirements. This paper compares various design approaches for parallel SAR processors capable ofprocessing high resolution satellite SAR data at a rate of 1/10 real-time. Sample designs are presented forpar- allel processors based on general purpose microprocessors, general purpose digital signal processors (DSP), and special purpose DSPs. In each case, the number of processing ele- ments required and the expected performance is predicted. A heterogeneous vector/scalar architecture composed of gen- eral and special purpose DSP devices is proposed that offers a good balance ofperformance andfixibility.

An oil/water, 3-D fully implicit Reservoir Simulator has been implemented on the ICL Distributed Array Processor (DAP), by a joint BNOC/ICL project team. The DAP is a single instruction, multiple data stream machine with 4096 processors in parallel. The major computational areas of code have been implemented on the DAP, leaving I/O and well calculations as serial code on the host 2976 machine. Matrix assembly is inherently parallel and can be implemented easily and efficiently on the DAP with compact code. Table look-up, though not obviously parallel, has been coded using a very efficient parallel algorithm. The Linear Solver, of Line Gauss-Seidel type, has been chosen for its efficiency on the DAP, with odd and even reduction used for solution of the resulting tri-diagonal equations. Further research will be undertaken to increase the robustness of this solver. The initial implementation has a 1-1 mapping of active grid blocks to processors, thus allowing up to 4096 active grid blocks. It is planned to extend to much larger models, and to 3 phase.

The RISC-V instruction set architecture (ISA) is gaining wide adoption in domains such as IoT, embedded systems, and academic research due to its open-source, modular, and flexible design. A CPU core that is both efficient and easily verified is a basic prerequisite for such applications. In this work, we present the design and implementation of a Verilog HDL-based 32-bit single-cycle RISC-V processor that supports the RV32I instruction set. The processor integrates an Arithmetic Logic Unit (ALU), Register File, Control Unit, and Memory into a structured and modular datapath. Simulation and functional verification were performed using Eda Playground, where the correctness of instruction execution was confirmed through waveform analysis. The result of ALU operations is governed by the opcode and operands, where arithmetic operations (e.g., addition) perform A+B, logical operations (e.g., AND) perform <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{A} \wedge \mathrm{B}$</tex>, and memory instructions handle load/store between registers and memory. Status flags such as zero, carry, negative, and overflow are updated accordingly. The proposed design demonstrates improved efficiency through optimized control logic and reduced critical path delay, ensuring faster instruction execution in single-cycle operation. This processor serves as a foundational model for future enhancements such as pipelined or low-power architectures aimed at increasing performance and energy efficiency. The proposed modular top-level architectural synthesis approach improves scalability, verification simplicity, and enables seamless extension toward pipelined RISC-V architectures.

Wireless baseband processing, which is characterized by high computational complexity and high data throughput, is regarded as the most challenging issue for software radio (SR) systems, especially for the General Purpose Processor (GPP)-based SR systems. To overcome this implementation difficulty in SR systems, the multicore architecture has been proposed as the GPP-based SR platform, for example, multicore Central Processing Unit (CPU), Graphic Processing Unit (GPU) and Cell processors. In this paper, the Cell processor is considered as the core component in the GPP-based SR platform, and the channel decoding modules for convolutional, Turbo and Low-density parity-check (LDPC) codes of WiMAX systems are investigated and efficiently implemented on Cell processor. With a single Synergistic Processor Element (SPE) running at 3.2GHz, the implemented channel decoders can throughput up to 30Mbps, 1.36Mbps and 1.71Mbps for the above three codes, respectively. Moreover, the decoding modules can be easily integrated to the SR system and can provide a highly integrated SR solution.

Summary form only given. In high level synthesis for real-time digital signal processing (DSP) architectures using heterogeneous functional units (FUs), an important problem is how to assign a proper fit type to each operation of a DSP application and generate a schedule in such a way that all requirements can be met and the total cost can be minimized. We propose a two-phase approach to solve this problem. In the first phase, we solve heterogeneous assignment problem, i.e., how to assign a proper FU type to a DSP application such that the total cost can be minimized while the timing constraint is satisfied. In the second phase, based on the assignments obtained from the first phase, we propose a minimum resource scheduling algorithm to generate a schedule and a feasible configuration that uses as little resource as possible. We prove heterogeneous assignment problem is NP-complete and propose several algorithms to solve it. The experiments show that algorithm DFG-assign-repeat is the best that gives a reduction of 25.7% on total cost compared with the previous work.

Software defined radio (SDR) is characterized by its flexibility and convenience of modification, because significant amounts of signal processing are handed over to the general-purpose processor (GPP), rather than being done in special-purpose hardware. In the long term, software-defined radios work well in low data transmission rate systems such as 2G/3G cellular systems and other wireless radio systems. With rapid development of GPP power, more complex algorithms and higher data rate wireless communication systems can be implemented with GPP processor and general purpose RF front end. In this paper we propose a LTE physical layer parallel system architecture based on multicore GPP to match up the high capacity requests of LTE air interface. Firstly, we analyzed the complexity of each LTE physical layer module and made a statistics of their processing time. And then we used Linux CPU affinity to allocate each LTE module to particular CPU core carefully based on the statistics. CPU utilization rate shows that using multi-core makes the system to have enough capacity. Our system can only match up 2M bandwidth when the LTE physical layer procedures are running on single CPU core, while it can match up 5M bandwidth when it's running on multi-core.

During design space exploration, alternative CPUs are evaluated for an envisaged SoC, thereby requiring fast CPU models and efficient code generation tools. Candidate CPUs may be general-purpose processors, DSPs, micro-controllers or ASIPs. The ASIP is a particularly challenging alternative: since instruction-set architecture (ISA) tailoring is allowed, an ASIP cannot rely on pre-existent code generation tools. Each target ISA requires a new tool chain. Therefore, an automatically retargetable tool chain is mandatory. This paper focuses on a couple of tools from such a chain: pre-processor and assembler. It proposes robust and efficient techniques allowing retargetability through automatic tool generation from a given target ISA, which is formally described by architecture description language (ADL) constructs. Tool robustness results from formal techniques based on context-free grammars. Tool efficiency evidence is provided by experiments targeting three CPUs: MIPS, PowerPC 405 and PIC 16F84.