Chapter 7 - Energy efficiency enhancement and linear amplifications: An envelope-tracking (ET) approach

This article presents a detailed design example of applying envelope tracking (ET) techniques on a highly monolithic silicon‐based radio‐frequency (RF) power amplifier (PA) to form a high‐efficiency and low‐cost ET‐PA system. An envelope‐tracked SiGe cascode PA with an integrated complementary metal–oxide–semiconductor (CMOS) envelope modulator for mobile WiMAX and 3GPP long‐term evolution (LTE) transmitters (TXs) is shown in this work. The entire ET‐based RF PA system delivers the linear output power of 22.3/24.3 dBm with the overall power‐added efficiency (PAE) of 33%/42% at 2.4 GHz for the WiMAX 64QAM and the 3GPP LTE 16QAM modulations, respectively. Additionally, it exhibits a highly efficient broadband characteristic for multiband applications. Compared with the conventional fixed‐supply cascode PA, our ET‐based cascode PA meets the WiMAX/LTE spectral mask and error vector magnitude (EVM) spec at close to itsP1dBcompression without the need for predistortion. The SiGe PA and the CMOS envelope modulator are both designed and fabricated in the TSMC 0.35‐μm SiGe bipolar CMOS (BiCMOS) process on the same die. This work represents an essential integration step toward achieving a fully monolithic ET‐based TX for wideband wireless applications.

This paper outlines an experimental demonstration of an envelope tracking (ET) technique applied to a kilowatt-level single-ended solid-state power amplifier (SSPA), aimed at enhancing the charging efficiency of superconducting radio frequency (SRF) cavities by reducing reflection power while maintaining a high degree of efficiency. The technique is particularly designed for the pulsed operation of the European Spallation Source (ESS) at a nominal frequency of 352 MHz, with a 5% duty cycle and a pulse width of 3.5 ms. The study introduces an optimal charging scheme using a solid-state-based amplifier to maintain high efficiency, allowing for power ramp-up while minimizing reflections from SRF cavities and optimizing SSPA efficiency. A fast envelope tracking power supply (ETPS) system is implemented for the approximately 300 ms charging time required by the SRF cavities at ESS. The ETPS system, demonstrated on a single module as a proof-of-concept with scalability potential to a 400 kW power station, indicates an overall average efficiency of 70% and a 24% energy saving over traditional vacuum-tube based amplifiers. This demonstrates the ET technique’s effectiveness at the kilowatt level for efficient SRF cavity charging with reduced reflection, offering significant efficiency and energy savings.

Envelope tracking (ET) prolongs the battery life by modulating the supply of a power amplifier (PA) according to the signal envelope. With this emerging technology, the PA efficiency is greatly improved, whereas the supply modulator (SM) itself needs to provide efficient and accurate envelope tracking for the overall performance of the SM-PA combined system (PA module). The ET technique, meanwhile, has seen limited use in high-power transmission due to the reduced SM efficiency for low output power originating from the linear stage in hybrid structures [1].

Power back-off performances of a new variant power-combining Class-E amplifier under different amplitude-modulation schemes such as continuous wave (CW), envelope elimination and restoration (EER), envelope tracking (ET) and outphasing are for the first time investigated in this study. Finite DC-feed inductances rather than massive RF chokes as used in the classic single-ended Class-E power amplifier (PA) resulted from the approximate yet effective frequency-domain circuit analysis provide the wherewithal to increase modulation bandwidth up to 80% higher than the classic single-ended Class-E PA. This increased modulation bandwidth is required for the linearity improvement in the EER/ET transmitters. The modified output load network of the power-combining Class-E amplifier adopting three-harmonic terminations technique relaxes the design specifications for the additional filtering block typically required at the output stage of the transmitter chain. Qualitative agreements between simulation and measurement results for all four schemes were achieved where the ET technique was proven superior to the other schemes. When the PA is used within the ET scheme, an increase of average drain efficiency of as high as 40% with respect to the CW excitation was obtained for a multi-carrier input signal with 12 dB peak-to-average power ratio.

We have investigated the efficiency and distortion behavior of an envelope tracking (ET) power amplifier (PA) according to the idle current. A two-stage PA is implemented using an InGaP/GaAs heterojunction bipolar transistor process and only the collector bias voltage of the power stage of the PA is modulated by a supply modulator. The gain of the power stage is decreased due to the saturated operation in the ET mode and the power burden of the drive stage is increased, lowering the overall efficiency of the ET PA. Through the idle current optimization of the power stage of the ET PA, the burden of the drive stage is reduced and the overall efficiency of the ET PA is enhanced. The intermodulation distortions (IMDs) of the ET PA change according to the idle current. The optimum linearity performance is achieved at the idle current where the magnitudes of IMD3 and IMD5 of the ET PA are low with a similar value. It is found that the optimal idle current for the high efficiency and linearity are identical. The optimized ET PA performs a power-added efficiency of 44.3% and an evolved universal terrestrial radio access adjacent channel leakage ratio of −35.2 dBc at an average power of 27 dBm and operating frequency of 1.85 GHz for a long term evolution signal having a peak-to-average power ratio of 7.5 dB, a bandwidth of 10 MHz, and a 16-quadrature amplitude modulation.

A common-drain power amplifier (PA) for envelope tracking systems is presented. In envelope tracking, the main PA operates mostly in compression and the power supply rejection ratio (PSRR) is not high. Furthermore, the output noise of the supply modulator can be mixed with the RF signal and generates out-of-band emissions. In this article, instead of using a common-source topology, the PSRR of the envelope tracking PA is inherently improved by utilizing a common-drain topology. A comprehensive analysis shows that the common-drain topology is less sensitive to the supply noise, as compared to the conventional common-source topology. The proposed common-drain PA is implemented using a discrete LDMOS PD20010-E RF transistor. Measurement results show that the PSRR of the proposed common-drain PA is improved by up to 7 dB as compared to that of the common-source PA. For a two-tone input with 10 MHz bandwidth at the center frequency of 700 MHz, the power added efficiency (PAE) and IM3 of the envelope tracking common-drain PA are 20% and − 28 dBc, respectively, at an average output power of 33.4 dBm. The amplifier also shows a 12.4 dB power gain. Moreover, by utilizing the envelope tracking, the PAE is improved by more than 5%.

This paper presents a SiGe envelope-tracking (ET) cascode power amplifier (PA) with an integrated CMOS envelope modulator for mobile WiMAX and 3GPP long-term evolution (LTE) transmitters (TXs). The entire ET-based RF PA system delivers the linear output power of 22.3/24.3 dBm with the overall power-added efficiency of 33%/42% at 2.4 GHz for the WiMAX 64 quadrature amplitude modulation (64QAM) and the 3GPP LTE 16 quadrature amplitude modulation, respectively. Additionally, it exhibits a highly efficient broadband characteristic for multiband applications. Compared to the conventional fixed-supply cascode PA, our ET-based cascode PA meets the WiMAX/LTE spectral mask and error vector magnitude spec at close to its P1dB compression without the need of predistortion. The SiGe PA and the CMOS envelope modulator are both designed and fabricated in the TSMC 0.35-μm SiGe BiCMOS process on the same die. This study represents an essential integration step toward achieving a fully monolithic large-signal ET-based TX for wideband wireless applications.

Envelope tracking (ET) is a key technology improving efficiency of RF power amplifiers (PAs) and battery lifetime in mobile handsets. It has been commercialized since 4G LTE era, and is also being employed in 5G NR handsets. A supply modulator (SM) is a circuit generating power supplies of RF PAs for ET and average power tracking (APT) operations. Currently, the maximum channel BW and supported ET BW of 5G NR handset is 100MHz [1]–[4]. In a short time, over 100MHz BW will be necessary to support intra-band contiguous carrier aggregation cases of n77C/n78C/n79C in 3GPP standard [5]. The required instantaneous maximum output power of SM is about 10W which is calculated by the following parameters: 26dBm output power by power class 2 (PC2), 2dB loss of RF front-end module (FEM) due to complex operating band combinations (EN-DC for non-standalone mode, NE-DC, 2CA/3CA), 6dB higher instantaneous power due to peak-to-average power ratio (PAPR) at 1 resource block (RB), 1dB margin, and poor PA efficiency of around 33% (worst example) due to high carrier frequency of 5GHz at n79 band. The poor PA efficiency can be relaxed by high voltage PA design beyond 5V. In [1], a supply modulator with boosted output larger than battery voltage $(V_{BAT})$ is proposed, and the designed PA with 30% higher voltage shows 10% higher efficiency and broader BW owing to low impedance transformation ratio from $50 \Omega$ and small parasitic output capacitance of power cell. The challenge is how to design a supply modulator for 5G NR that can achieve both wide ET BW and high output voltage/power capability, while satisfying high efficiency, low receiver-band noise, short transition time, and multi-mode/standard operation.

Preface. About the Authors. Acknowledgments. 1 Power Amplifier Fundamentals. 1.1 Introduction. 1.2 Definition of Power Amplifier Parameters. 1.3 Distortion Parameters. 1.4 Power Match Condition. 1.5 Class of Operation. 1.6 Overview of Semiconductors for PAs. 1.7 Devices for PA. 1.8 Appendix: Demonstration of Useful Relationships. 1.9 References. 2 Power Amplifier Design. 2.1 Introduction. 2.2 Design Flow. 2.3 Simplified Approaches. 2.4 The Tuned Load Amplifier. 2.5 Sample Design of a Tuned Load PA. 2.6 References. 3 Nonlinear Analysis for Power Amplifiers. 3.1 Introduction. 3.2 Linear vs. Nonlinear Circuits. 3.3 Time Domain Integration. 3.4 Example. 3.5 Solution by Series Expansion. 3.6 The Volterra Series. 3.7 The Fourier Series. 3.8 The Harmonic Balance. 3.9 Envelope Analysis. 3.10 Spectral Balance. 3.11 Large Signal Stability Issue. 3.12 References. 4 Load Pull. 4.1 Introduction. 4.2 Passive Source/Load Pull Measurement Systems. 4.3 Active Source/Load Pull Measurement Systems. 4.4 Measurement Test-sets. 4.5 Advanced Load Pull Measurements. 4.6 Source/Load Pull Characterization. 4.7 Determination of Optimum Load Condition. 4.8 Appendix: Construction of Simplified Load Pull Contours through Linear Simulations. 4.9 References. 5 High Efficiency PA Design Theory. 5.1 Introduction. 5.2 Power Balance in a PA. 5.3 Ideal Approaches. 5.4 High Frequency Harmonic Tuning Approaches. 5.5 High Frequency Third Harmonic Tuned (Class F). 5.6 High Frequency Second Harmonic Tuned. 5.7 High Frequency Second and Third Harmonic Tuned. 5.8 Design by Harmonic Tuning. 5.9 Final Remarks. 5.10 References. 6 Switched Amplifiers. 6.1 Introduction. 6.2 The Ideal Class E Amplifier. 6.3 Class E Behavioural Analysis. 6.4 Low Frequency Class E Amplifier Design. 6.5 Class E Amplifier Design with 50# Duty-cycle. 6.6 Examples of High Frequency Class E Amplifiers. 6.7 Class E vs. Harmonic Tuned. 6.8 Class E Final Remarks. 6.9 Appendix: Demonstration of Useful Relationships. 6.10 References. 7 High Frequency Class F Power Amplifiers. 7.1 Introduction. 7.2 Class F Description Based on Voltage Wave-shaping. 7.3 High Frequency Class F Amplifiers. 7.4 Bias Level Selection. 7.5 Class F Output Matching Network Design. 7.6 Class F Design Examples. 7.7 References. 8 High Frequency Harmonic Tuned Power Amplifiers. 8.1 Introduction. 8.2 Theory of Harmonic Tuned PA Design. 8.3 Input Device Nonlinear Phenomena: Theoretical Analysis. 8.4 Input Device Nonlinear Phenomena: Experimental Results. 8.5 Output Device Nonlinear Phenomena. 8.6 Design of a Second HT Power Amplifier. 8.7 Design of a Second and Third HT Power Amplifier. 8.8 Example of 2nd HT GaN PA. 8.9 Final Remarks. 8.10 References. 9 High Linearity in Efficient Power Amplifiers. 9.1 Introduction. 9.2 Systems Classification. 9.3 Linearity Issue. 9.4 Bias Point Influence on IMD. 9.5 Harmonic Loading Effects on IMD. 9.6 Appendix: Volterra Analysis Example. 9.7 References. 10 Power Combining. 10.1 Introduction. 10.2 Device Scaling Properties. 10.3 Power Budget. 10.4 Power Combiner Classification. 10.5 The T-junction Power Divider. 10.6 Wilkinson Combiner. 10.7 The Quadrature (90 ) Hybrid. 10.8 The 180 Hybrid (Ring Coupler or Rat-race). 10.9 Bus-bar Combiner. 10.10 Other Planar Combiners. 10.11 Corporate Combiners. 10.12 Resonating Planar Combiners. 10.13 Graceful Degradation. 10.14 Matching Properties of Combined PAs. 10.15 Unbalance Issue in Hybrid Combiners. 10.16 Appendix: Basic Properties of Three-port Networks. 10.17 References. 11 The Doherty Power Amplifier. 11.1 Introduction. 11.2 Doherty's Idea. 11.3 The Classical Doherty Configuration. 11.4 The 'AB-C' Doherty Amplifier Analysis. 11.5 Power Splitter Sizing. 11.6 Evaluation of the Gain in a Doherty Amplifier. 11.7 Design Example. 11.8 Advanced Solutions. 11.9 References. Index.

This paper presents a dual power-mode and multi-band power amplifier (PA) for handset applications that improves the efficiency in low-power regions. This PA operates in two modes through path control by a shunt switched capacitor. The proposed control method provides efficient mode control without any efficiency degrading and bandwidth (BW) limiting. The proposed PA, in conjunction with a boosted supply modulator for envelope tracking (ET) operation not only in the high-power mode, but also in the low-power mode, delivers good performance at all average output power levels. The linearity is improved by ET through a proper envelope-shaping method. For demonstrative purposes, the PA and supply modulator are implemented using an InGaP/GaAs heterojunction bipolar transistor and AIGaAs/InGaAs enhancement/depletion-mode pseudomorphic high electron-mobility transistor process and a 0.18- $\mu$ m CMOS process, respectively. The ET PA is tested across the range of 1.7–2.0 GHz using a long-term evolution signal with 16 quadrature amplitude modulation, a 7.5-dB peak-to-average power ratio, and 10-MHz BW. The proposed dual power-mode multi-band ET PA delivers good performance for high- and low-power modes, indicating that the architecture is promising for handset PA applications.

The rapid evolution of telecommunication systems has strongly influenced our lives, and the way we communicate and exchange information. Nevertheless, much progress is expected to happen in the next years with the introduction of new generations of wireless communications standards, which require signals with large bandwidth and very high Peak-to-Average Power Ratio (PAPR) in order to enhance the spectral efficiency and maximize the data rate. However, such developments can only take place through the evolution of Radio-Frequency (RF) which should be capable of working at higher frequencies, higher bandwidth and with higher efficiencies than before. In order to meet these demanding specifications, transmitter architectures have to evolve from a single linear RF Power-Amplifier (PA) into more complex architectures. Envelope Tracking (ET) is one of the most promising solutions for the efficiency-enhancement of next generation transmitters. The research described in this thesis aims to provide solutions to enhance the efficiency of the RF PA by means of an ET architecture. To this purpose, a novel discrete level supply modulator is investigated, which is based on a direct digital-to-analog power conversion. This supply modulator is capable of synthesizing eight voltage steps by means of three isolated voltage sources, thus behaving like a Power Digital-to-Analog Converter (Power-DAC). A hybrid version of the Power-DAC exploiting very fast GaN devices is developed and tested with an L-band PA achieving efficiency improvement up to 13% with 10 MHz of bandwidth. Furthermore, a monolithic GaN version of the Power-DAC is prototyped and tested with an X-band PA achieving efficiency improvement up to 20% and bandwidth of 20 MHz. This supply modulator is tested with outphasing PAs showing promising results with modulated signals and efficiency improvement up to 9%. Finally, dispersive phenomena, which affect PAs and switches in supply modulators, are investigated, characterized and modeled.

A broadband SiGe power amplifier (PA) with double gain peaks for 5G applications is presented. The differential structure is widely adopted in millimeter-wave circuit design to decrease the impact of the source parasitic inductance that is induced by the bonding wires. Since differential PA results in a higher impedance transformation ratio of the matching network, differential PAs generally have narrower bandwidth than single-ended PAs. Through the bandwidth analysis of the matching network, the transformer used for interstage matching is elaborately designed to ease gain fluctuations. By controlling the stationary points of impedance transformation, the maximum available gain characteristic of a transistor, which decreases with increasing frequency, can be compensated. The gain curve of PA, thus, has double gain peaks within operational frequencies to make its frequency responses as flat as possible. The proposed PA for the frequency band from 27 to 37 GHz is fabricated in a standard 130-nm SiGe BiCMOS process, which occupies 0.36 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Under the 2.5-V voltage supply, the SiGe PA exhibited a power gain of 33.5 dB and output power of 21.3 dBm with 24% power-added efficiency at 31 GHz. It achieves a 34% 3-dB small-signal <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$S_{21}$ </tex-math></inline-formula> bandwidth from 27.3 to 38.5 GHz.

Envelope tracking (ET) linearizability of a power amplifier (PA) is studied in this paper. ET linearization can be explained as the cancellation between two intermodulation distortion (IMD) components [1], [2]. The phase difference θ 0 between the two IMD components is identified as the criterion of ET linearizability. The IMD improvement by incorporating ET module with PA can be analytically calculated in terms of $\theta_{0}$ Excellent agreement between the prediction and measurement is achieved. Determination of $\theta_{0}$ using three-tone measurement is proposed and demonstrated. ET linearizability is an inherent feature of a standalone PA itself, and can be quantitatively predicted before incorporating an ET module.

This paper expounds on power efficiency enhancement techniques that are sought for the reduction of power consumption of wireless radio frequency power amplifiers (RFPA) and transmitters. The paper will focus on advanced power amplification architectures such as doherty power amplifiers (DPA), linear amplification using nonlinear components (LINC), envelop elimination and restoration (EER) and envelope tracking (ET) techniques. Overview on each technique will be given and performance in terms of linearity, efficiency, complexity, and bandwidth will be discussed. In addition design challenges associated with the practical implementation of these techniques in the context of emerging wireless networks will be discussed.

This letter presents a highly efficient CMOS power amplifier (PA) with adaptive envelope-tracking (ET) techniques. The linearity and efficiency of the PA are improved by ET-based techniques at the gate of the common-gate (CG), the gate of the common-source (CS), and the drain of the CG. The proposed CMOS ET PA is fabricated using a 0.18 mu m CMOS technology with a printed circuit board (PCB) transformer which has a lower insertion loss than CMOS one. Without any help of additional resources, the CMOS PA delivers an average output power of 27.5 dBm with a power-added efficiency (PAE) of 42.5%, an error vector magnitude (EVM) of 2.5%, and an ACLR(E-UTRA) of -36.5 dBc at 1.85 GHz for a long term evolution (LTE) signal with a bandwidth of 10 MHz and 7.5 dB peak-to-average power ratio (PAPR).