Envelope Tracking Techniques Applied to a Fully Monolithic Silicon‐BasedRFPower Amplifier System

Chapter 7 - Energy efficiency enhancement and linear amplifications: An envelope-tracking (ET) approach

This paper presents a SiGe envelope-tracking (ET) cascode power amplifier (PA) with an integrated CMOS envelope modulator for mobile WiMAX and 3GPP long-term evolution (LTE) transmitters (TXs). The entire ET-based RF PA system delivers the linear output power of 22.3/24.3 dBm with the overall power-added efficiency of 33%/42% at 2.4 GHz for the WiMAX 64 quadrature amplitude modulation (64QAM) and the 3GPP LTE 16 quadrature amplitude modulation, respectively. Additionally, it exhibits a highly efficient broadband characteristic for multiband applications. Compared to the conventional fixed-supply cascode PA, our ET-based cascode PA meets the WiMAX/LTE spectral mask and error vector magnitude spec at close to its P1dB compression without the need of predistortion. The SiGe PA and the CMOS envelope modulator are both designed and fabricated in the TSMC 0.35-μm SiGe BiCMOS process on the same die. This study represents an essential integration step toward achieving a fully monolithic large-signal ET-based TX for wideband wireless applications.

This letter presents a highly efficient CMOS power amplifier (PA) with adaptive envelope-tracking (ET) techniques. The linearity and efficiency of the PA are improved by ET-based techniques at the gate of the common-gate (CG), the gate of the common-source (CS), and the drain of the CG. The proposed CMOS ET PA is fabricated using a 0.18 mu m CMOS technology with a printed circuit board (PCB) transformer which has a lower insertion loss than CMOS one. Without any help of additional resources, the CMOS PA delivers an average output power of 27.5 dBm with a power-added efficiency (PAE) of 42.5%, an error vector magnitude (EVM) of 2.5%, and an ACLR(E-UTRA) of -36.5 dBc at 1.85 GHz for a long term evolution (LTE) signal with a bandwidth of 10 MHz and 7.5 dB peak-to-average power ratio (PAPR).

A common-drain power amplifier (PA) for envelope tracking systems is presented. In envelope tracking, the main PA operates mostly in compression and the power supply rejection ratio (PSRR) is not high. Furthermore, the output noise of the supply modulator can be mixed with the RF signal and generates out-of-band emissions. In this article, instead of using a common-source topology, the PSRR of the envelope tracking PA is inherently improved by utilizing a common-drain topology. A comprehensive analysis shows that the common-drain topology is less sensitive to the supply noise, as compared to the conventional common-source topology. The proposed common-drain PA is implemented using a discrete LDMOS PD20010-E RF transistor. Measurement results show that the PSRR of the proposed common-drain PA is improved by up to 7 dB as compared to that of the common-source PA. For a two-tone input with 10 MHz bandwidth at the center frequency of 700 MHz, the power added efficiency (PAE) and IM3 of the envelope tracking common-drain PA are 20% and − 28 dBc, respectively, at an average output power of 33.4 dBm. The amplifier also shows a 12.4 dB power gain. Moreover, by utilizing the envelope tracking, the PAE is improved by more than 5%.

This paper outlines an experimental demonstration of an envelope tracking (ET) technique applied to a kilowatt-level single-ended solid-state power amplifier (SSPA), aimed at enhancing the charging efficiency of superconducting radio frequency (SRF) cavities by reducing reflection power while maintaining a high degree of efficiency. The technique is particularly designed for the pulsed operation of the European Spallation Source (ESS) at a nominal frequency of 352 MHz, with a 5% duty cycle and a pulse width of 3.5 ms. The study introduces an optimal charging scheme using a solid-state-based amplifier to maintain high efficiency, allowing for power ramp-up while minimizing reflections from SRF cavities and optimizing SSPA efficiency. A fast envelope tracking power supply (ETPS) system is implemented for the approximately 300 ms charging time required by the SRF cavities at ESS. The ETPS system, demonstrated on a single module as a proof-of-concept with scalability potential to a 400 kW power station, indicates an overall average efficiency of 70% and a 24% energy saving over traditional vacuum-tube based amplifiers. This demonstrates the ET technique’s effectiveness at the kilowatt level for efficient SRF cavity charging with reduced reflection, offering significant efficiency and energy savings.

This letter presents a dual-mode multi-band second harmonic controlled SOI LDMOS power amplifier (PA). A mode selection switch is designed to have better power handing capability than a conventional switch, which improves performance in low power mode (LPM). To improve the PA's linearity in high power mode (HPM), second harmonic is controlled with the aid of a path for LPM. The PA, implemented with a 0.13- $\mu$ m SOI LDMOS process, operates in triple bands (band 5, 8, and 20) with dual power modes. It is measured using a 16 QAM long-term evolution (LTE) signal with a 10 MHz bandwidth. At 850 MHz, the results show 27.7 dBm average output power (Pout), 31.4 dB gain, and 31.4% power-added efficiency (PAE) with 4% error-vector magnitude (EVM) in HPM and 10.4 dB gain, 15.5 dBm Pout, and 22.5% PAE with 4% EVM in LPM with the LTE signal.

Envelope tracking (ET) prolongs the battery life by modulating the supply of a power amplifier (PA) according to the signal envelope. With this emerging technology, the PA efficiency is greatly improved, whereas the supply modulator (SM) itself needs to provide efficient and accurate envelope tracking for the overall performance of the SM-PA combined system (PA module). The ET technique, meanwhile, has seen limited use in high-power transmission due to the reduced SM efficiency for low output power originating from the linear stage in hybrid structures [1].

Integrated n-channel NFET-MESFET cascode power amplifiers (PAs) have been fabricated using a 45 nm SOI CMOS technology optimized for 5G applications. The cascode architecture combines the RF performance of the 40nm gate length NFET (f max > 340 GHz) with the high voltage capability (V DD > 10 V) of the SOI MESFET. Load-pull measurements at 5.8 GHz confirm that a PA with 18 dBm saturated output power, >21dB gain, and >50% power added efficiency (PAE) can support 64QAM signals with 3% error vector magnitude and 25% average PAE at 6dB backed off power levels. These results suggest that an NFET-MESFET cascode PA might be suitable for low-cost 5G picocell/femtocell applications without the need for digital pre-distortion.

We have investigated the efficiency and distortion behavior of an envelope tracking (ET) power amplifier (PA) according to the idle current. A two-stage PA is implemented using an InGaP/GaAs heterojunction bipolar transistor process and only the collector bias voltage of the power stage of the PA is modulated by a supply modulator. The gain of the power stage is decreased due to the saturated operation in the ET mode and the power burden of the drive stage is increased, lowering the overall efficiency of the ET PA. Through the idle current optimization of the power stage of the ET PA, the burden of the drive stage is reduced and the overall efficiency of the ET PA is enhanced. The intermodulation distortions (IMDs) of the ET PA change according to the idle current. The optimum linearity performance is achieved at the idle current where the magnitudes of IMD3 and IMD5 of the ET PA are low with a similar value. It is found that the optimal idle current for the high efficiency and linearity are identical. The optimized ET PA performs a power-added efficiency of 44.3% and an evolved universal terrestrial radio access adjacent channel leakage ratio of −35.2 dBc at an average power of 27 dBm and operating frequency of 1.85 GHz for a long term evolution signal having a peak-to-average power ratio of 7.5 dB, a bandwidth of 10 MHz, and a 16-quadrature amplitude modulation.

Power back-off performances of a new variant power-combining Class-E amplifier under different amplitude-modulation schemes such as continuous wave (CW), envelope elimination and restoration (EER), envelope tracking (ET) and outphasing are for the first time investigated in this study. Finite DC-feed inductances rather than massive RF chokes as used in the classic single-ended Class-E power amplifier (PA) resulted from the approximate yet effective frequency-domain circuit analysis provide the wherewithal to increase modulation bandwidth up to 80% higher than the classic single-ended Class-E PA. This increased modulation bandwidth is required for the linearity improvement in the EER/ET transmitters. The modified output load network of the power-combining Class-E amplifier adopting three-harmonic terminations technique relaxes the design specifications for the additional filtering block typically required at the output stage of the transmitter chain. Qualitative agreements between simulation and measurement results for all four schemes were achieved where the ET technique was proven superior to the other schemes. When the PA is used within the ET scheme, an increase of average drain efficiency of as high as 40% with respect to the CW excitation was obtained for a multi-carrier input signal with 12 dB peak-to-average power ratio.

The polar transmitter is an alternative RF transmitter architecture solution to achieve a high-efficiency power amplifier. In this paper the impact of polar transmitter imperfections on the UTRA long term evolution (LTE) link level performance is investigated. The most common imperfections in a polar transmitter are modelled, such as timing delay alignment and power amplifier non-idealities. Our approach is to analyze the relation between error vector magnitude (EVM) and link performance loss due to each imperfection. The results obtained are based on LTE uplink parameter settings and show that the most severe polar transmitter problem in LTE uplink is the timing delay alignment, especially for higher order modulation and coding scheme. Results also show that the EVM is a good direct measure to estimate the link level performance loss for various imperfections in the anticipated EVM range. For 16 QAM rate 3/4, an SNR loss of approximately 0.5 dB can be estimated by an EVM value of 8%.

A broadband SiGe power amplifier (PA) with double gain peaks for 5G applications is presented. The differential structure is widely adopted in millimeter-wave circuit design to decrease the impact of the source parasitic inductance that is induced by the bonding wires. Since differential PA results in a higher impedance transformation ratio of the matching network, differential PAs generally have narrower bandwidth than single-ended PAs. Through the bandwidth analysis of the matching network, the transformer used for interstage matching is elaborately designed to ease gain fluctuations. By controlling the stationary points of impedance transformation, the maximum available gain characteristic of a transistor, which decreases with increasing frequency, can be compensated. The gain curve of PA, thus, has double gain peaks within operational frequencies to make its frequency responses as flat as possible. The proposed PA for the frequency band from 27 to 37 GHz is fabricated in a standard 130-nm SiGe BiCMOS process, which occupies 0.36 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Under the 2.5-V voltage supply, the SiGe PA exhibited a power gain of 33.5 dB and output power of 21.3 dBm with 24% power-added efficiency at 31 GHz. It achieves a 34% 3-dB small-signal <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$S_{21}$ </tex-math></inline-formula> bandwidth from 27.3 to 38.5 GHz.

This paper presents the first linear bulk CMOS power amplifier (PA) targeting low-power fifth-generation (5G) mobile user equipment integrated phased array transceivers. The output stage of the PA is first optimized for power-added efficiency (PAE) at a desired error vector magnitude (EVM) and range given a challenging 5G uplink use case scenario. Then, inductive source degeneration in the optimized output stage is shown to enable its embedding into a two-stage transformer-coupled PA; by broadening interstage impedance matching bandwidth and helping to reduce distortion. Designed and fabricated in 1P7M 28 nm bulk CMOS and using a 1 V supply, the PA achieves +4.2 dBm/9% measured $P_{\text {out}}$ /PAE at −25 dBc EVM for a 250 MHz-wide 64-quadrature amplitude modulation orthogonal frequency division multiplexing signal with 9.6 dB peak-to-average power ratio. The PA also achieves 35.5%/10% PAE for continuous wave signals at saturation/9.6 dB back-off from saturation. To the best of the authors’ knowledge, these are the highest measured PAE values among published ${K}$ - and Ka -band CMOS PAs.

Long-term-evolution (LTE) communication enables high data-rates but degrades the efficiency of the power amplifiers (PAs) due to high peak-to-average power ratios of transmitted signals. Envelope tracking (ET) and envelope-elimination-and-restoration (EER) techniques have been proposed to improve the PA efficiency by adapting the PA supply voltage to the envelope. Linear PAs in ET systems are mostly implemented in non-CMOS technologies for high efficiency [1]. However, the growing demand for low-cost integrated systems has motivated the use of CMOS PAs [2]. The main drawback of this is that linear CMOS PAs have poor efficiency. The high efficiency of switching PAs makes them a promising candidate in CMOS [3]. In EER systems, where switching PAs are used, the supply modulator must satisfy stringent noise and bandwidth specifications in order to recover the amplitude information of the LTE signal. Thus, it is a challenge for supply modulators to maintain high efficiency. Recently, a number of methods have been adopted to improve supply-modulator efficiency. In [1], a dual-switching topology is proposed, but it requires an additional inductor and results in an unpredictable noise spectrum. In [4], an AC-coupling topology is adopted to reduce the supply voltage of the linear amplifier. However, due to the slow response of the switching amplifier, the efficiency is still low.

A power amplifier (PA) supporting wideband code division multiple access, long-term evolution (LTE), and wireless local area network applications has been implemented in 0.18- $\mu{\hbox{m}}$ SiGe BiCMOS technology. The PA integrates a tunable input matching network, a broadband output matching network, and adaptive bias circuits in a single chip to achieve high linearity and high power in different modulation schemes and operating bands. The three-stage PA adopts a differential-type configuration without using through-silicon-via technology to deliver 4 1.3–42 dB of gain and 28.2–28.6 dBm of 1-dB compression output power with a 20.8–27.6% power-added efficiency (PAE) at 1.85–2.5 GHz. To further validate the usefulness of the proposed PA, the envelope-tracking PA is designed to improve the PAE by 6.5% within the linearity specification of a 24.7-dBm average output power and a $-$ 33-dBc adjacent channel leakage ratio for 2.35-GHz 16 quadrature-amplitude-modulation time-division LTE signal with 20-MHz bandwidth.