Chapter 7 - Practical DSP for the Cortex-M4

The emerging applications have imposed strong requirements, such as high processing capacity, low‐power consumption, reduced size and many others, on the sensor‐based systems. Owing to their balanced combination of flexibility and hardware performance, digital signal processors (DSPs) have become more and more popular used in sensor‐based systems. Many DSPs have adopted very long instruction words (VLIW) style architecture, for its ability to greatly enhance instruction level parallelism. However, as VLIW codes are statically scheduled, the behaviour of VLIW architecture is dominated by the efficiency of its compiler. Single instruction multiple data (SIMD) instructions, which perform multiple operations in parallel on multiple data packed in registers, have been widely used in DSPs to meet the requirements of sensor‐based systems. Although hand programming still yields the best performing SIMD codes, it is both time consuming and error prone. Advanced compiler techniques to automatically generate SIMD instructions, are under urgent demand. In this study, the authors proposed an SIMD code auto generation approach for VLIW architecture. It recognises candidates of operations in the intermediate representation, evaluates the possibility of grouping them into SIMD code, reconstructs the verified ones according to the cost model and finally generates the SIMD code. The authors have implemented this approach in the compiler of a VLIW DSP named Magnolia, which is designed for sensor‐based systems. The results show that the authors’ approach is very efficient, and can largely enhance the performance.

Use of single instruction multiple data (SIMD) functional units enables multimedia systems to exploit parallelism to a higher degree resulting in significant system performance improvements. While implementation of whole SIMD system functionality for an application results in wastage of area resources, we have observed that for a specific multimedia application, we only need to implement a customized SIMD unit that is a subset of whole SIMD standard implementation. Based on this study, we have proposed an extension to the traditional system design and synthesis flow by integrating a methodology of SIMD unit synthesis. Our system synthesizes a customized SIMD unit along with an extended instruction set and generates an equivalent version of assembly code for the application using the extended instruction set. The results of area and performance obtained by experimenting over our implementation of AltiVec compatible customized SIMD units show the effectiveness of our approach.

Software defined radio (SDR) systems require programmable architectures that provide high performance combined with high energy efficiency. Wide single instruction, multiple data (SIMD) architectures could potentially satisfy these demands, but only few publications examine the interdependence between the SIMD width and the performance of typical SDR algorithms. In this paper, we present a detailed analysis of three SDR algorithm classes on a newly developed scalable SIMD architecture, which combines SIMD processing with long instruction word (LIW) execution. Although radix-2 and mixed-radix fast Fourier transform, sphere decoding, and low-density parity-check decoding all benefit from SIMD processing, our results show that there are different constraints on the performance.

With the multitude of existing and upcoming wireless standards, it is becoming increasingly difficult for hardware-only baseband processing solutions to adapt to the rapidly changing wireless communication landscape. Software defined radio (SDR) promises to deliver a cost effective and flexible solution by implementing a wide variety of wireless protocols in software. In previous work, a fully programmable multicore architecture, SODA, was proposed that was able to meet the real-time requirements of 3G wireless protocols. SODA consists of one ARM control processor and four wide single instruction multiple data (SIMD) processing elements. Each processing element consists of a scalar and a wide 512-bit 32-lane SIMD datapath. A commercial prototype based on the SODA architecture, Ardbeg (named after a brand of Scotch whisky), has been developed. In this paper, we present the architectural evolution of going from a research design to a commercial prototype, including the goals, tradeoffs, and final design choices. Ardbegpsilas redesign process can be grouped into the following three major areas: optimizing the wide SIMD datapath, providing long instruction word (LIW) support for SIMD operations, and adding application-specific hardware accelerators. Because SODA was originally designed with 180 nm technology, the wide SIMD datapath is re-optimized in Ardbeg for 90 nm technology. This includes re-evaluating the most efficient SIMD width, designing a wider SIMD shuffle network, and implementing faster SIMD arithmetic units. Ardbeg also provides modest LIW support by allowing two SIMD operations to issue in the same cycle. This LIW execution supports SDR algorithmspsila most common parallel SIMD execution patterns with minimal hardware overhead. A viable commercial SDR solution must be competitive with existing ASIC solutions. Therefore, algorithm-specific hardware is added for performance bottleneck algorithms while still maintaining enough flexibility to support multiple wireless protocols. The combination of these architectural improvements allows Ardbeg to achieve 1.5-7x speedup over SODA across multiple wireless algorithms while consuming less power.

The paper describes investigations into multiprocessor scheduling techniques for high quality audio DSP. A DSP processor/multiprocessor simulator is introduced which allows register-level simulation of multiprocessor DSP architectures and parallel DSP algorithms. The simulator has been used to investigate the implementation of recursive filtering algorithms for audio, using multiprocessor DSP architectures. Results from these studies are presented and discussed. Also described are multiprocessor DSP algorithm mapping and scheduling techniques based on genetic algorithms. These investigate techniques using genetic algorithms to schedule audio DSP algorithms written in the form of data flow graphs onto specified DSP multiprocessor arrays. The basic techniques are described and initial results from these studies are also presented and discussed. (8 pages)

SIMD (Single Instruction Multiple Data) architectures are widely used in application domains like the wireless communication, video and audio processing, and control engineering. The abundant data parallelism makes the SIMD architecture the proper match in data processing and performance improvement. However, there are also critical inefficiencies in current SIMD architectures. To understand such inefficiency, we carry out a deep investigation in the main components of Long Term Evolution (LTE) protocol, which is an important wireless communication protocol. Performance investigation is taken on a cycle-accurate simulator, featuring the main characteristics of existing SIMD architectures. Based on the investigation, we locate the inefficiencies in two aspects: the data communication operations among different processing units and the support for matrix-style computations. We have also carried out studies with enhanced SIMD architectures in the above two aspects. The overall performance of SIMD architectures can be greatly improved.

<p>Modern computing technology enters the era of parallel computing with the trend of sustainable and scalable parallelism. Single Instruction Multiple Data (SIMD) is an important way to go along with the trend. It is able to gather more and more computing ability by increasing the number of processor cores without the need of modifying the program. Meanwhile, in the field of scientific computing and engineering design, many computation intensive applications are facing the challenge of increasingly large amount of data. Data parallel computing will be an important way to further improve the performance of these applications. In this paper, we take the accurate collision detection in building information modeling as an example. We demonstrate a model for constructing a data parallel algorithm. According to the model, a complex object is decomposed into the sets of simple objects; collision detection among complex objects is converted into those among simple objects. The resulting algorithm is a typical SIMD algorithm, and its advantages in parallelism and scalability is unparalleled in respect to the traditional algorithms.</p>

Single instruction multiple data (SIMD) functional units are ubiquitous in modern microprocessors. Effective use of these SIMD functional units is essential in achieving the highest possible performance. Automatic generation of SIMD instructions in the presence of control flow is challenging, however, not only because SIMD code is hard to generate in the presence of arbitrarily complex control flow, but also because the SIMD code executing the instructions in all control paths may slow compared to the scalar original, which may bypass a large portion of the code. One promising technique introduced recently involves inserting branches-on-superword-condition-codes (BOSCCs) to bypass vector instructions. In this paper, we describe two techniques that improve on the previous approach. First, BOSCCs are generated in a nested fashion so that even BOSCCs themselves can be bypassed by other BOSCCs. Second, we generate all vec_any_* instructions to bypass even some predicate-defining instructions. We implemented these techniques in a vectorizing compiler. On 14 kernels, the compiler achieves distinct speedups, including 1.99X over the previous technique that generates single- level BOSCCs and vec_any_ne only.

SIMD (single instruction multiple data) is a processor architecture classification from Flynn's taxonomy. The concept is that a single instruction set operates on multiple units of data simultaneously. Computers use this processor architecture are known as array processors or vector processors. Most computers in use today are SISD (single instruction single data) though allowing a single instruction to operate on multiple data can also be applied to a virtual machine that is capable of parallel execution through the use of multi-threading/multi-core processors, or distributed parallel execution on a multi-computer grid. This paper proposes a language structure that applies the SIMD concept to the Java virtual machine. The motive is to reduce the complexity of the code and ease implementation of parallelization by running a single set of instructions concurrently on an entire collection of objects.

Due to the high computational complexity of the full-search algorithm for video coding, techniques to accelerate the execution of the full-search algorithm are needed for real-time implementations of current video compression standards. In this paper, a technique of using eight-bit partial sums of four luminance values is proposed to reduce the computational complexity of the original full-search algorithm without loss of its accuracy. Furthermore, since the proposed technique is suitable for the implementation on the single instruction multiple data (SIMD) architectures, the byte-type data-parallelism of the SIMD architecture can be utilized to further accelerate the execution of the proposed technique. Simulation results for the benchmark video test sequences demonstrate that the proposed technique can significantly accelerate the execution of the full-search algorithm on SIMD architectures without loss of its accuracy.

This paper introduces an efficient technique to speed up the higher-order masking scheme of the advanced encryption standard (AES), in which the S-box computation is based on the composite field, using Intel's Supplemental Streaming SIMD Extensions 3 (SSSE 3) instruction set. Different side-channel attack (SCA) countermeasures are combined to mitigate more than one type of SCA. The proposed technique solves the problem of higher-order masking's negative impact on performance and removes the need for lookup tables by applying parallel processing at the data level using single instruction multiple data (SIMD) technology. We implemented the technique on a Linux machine with an Intel processor that supports SSSE3 instructions. The technique performed nine times faster than the second order masking scheme and was seven times faster than the third order masking scheme reported in the literature. The results that we achieved through applying SIMD technology make our proposed technique practical and attractive.

This paper analyses the performance of the state-of-the-art media ISA (instruction set architecture) extensions in a general-purpose processor, when executing a video encoder based on an affine motion model. In addition to SIMD (single instruction multiple data) fixed-point instructions, these ISA extensions include SIMD floating-point instructions, special-purpose SIMD fixed-point instructions, and cacheability control instructions. In this study, eight time-consuming kernels of the video encoder were hand-optimized, using instructions in all four instruction categories of these media ISA extensions (the FLP version). These kernels were also hand-optimized using only SIMD fixed-point ISA extensions, without special-purpose instructions (the FXP version). For the FLP version, this study resulted in an average kernel-level speedup of 1.37X and an application-level speedup of 1.11X, compared to the FXP version, and an application-level speedup of 3.41X, compared to the C version.

The use of Single Instruction Multiple Data (SIMD) operations can be instrumental in meeting the needs of high performance computations. Most languages, including C/C++, give a user the power to directly exploit this hardware and inherent parallelism. We have created a retargetable native SIMD library which Java programmers are now able to use to directly access SIMD intrinsics including MMX, SSE1, SSE2 and SSE3 through prescribed Java methods in an API. This API gives users direct control over their high-performance computations instead of solely relying on the SIMD optimizations of the Java Virtual Machine (JVM), or relying on a GPU which must send and receive the data from the CPU. Through the use of this Java API and the included backing library, substantial performance gains can be achieved on large and complex vector operations. We show an example for which the API obtains a 2x to 3x speedup for both small and large data sets as compared to solely relying on the SIMD optimizations in the JVM.

The single instruction multiple data (SIMD) capability in modern processors is critical to improving the performance of current compute-intensive programs. Modern compilers use vectorization techniques to exploit the SIMD capability, by detecting data parallelism in scalar source code and transforming a group of scalar instructions into vector-based instructions. In this study, we focus on one of the most common vectorization techniques, a technique called loop-based vectorization, which targets loops and optimizes their performance by grouping multiple occurrences of the same operation across loop iterations into a single SIMD instruction. We propose a data-driven graph-based learning framework for automatic vectorization, called autograph , which takes an input program, extracts the loops, and then learns a structured representation to automatically predict the correct vectorization and interleaving factors. Our proposed framework utilizes deep reinforcement learning to learn an optimal policy (observations to actions) from an intelligent agent in a SIMD environment, and automatically injects the predicted vectorization pragmas into the input program. We conducted an extensive evaluation on multiple benchmark datasets and comparisons with state-of-the-art baselines. Our results show that autograph achieves on average 2.49× performance improvement for Polybench compared to NeuroVectorizer and 3.69× compared to the baseline -O3.

Array indirection causes several challenges for compilers to utilize single instruction, multiple data (SIMD) instructions. Disjoint memory references, arbitrarily misaligned memory references, and dependence cycles in loops are main challenges to handle for SIMD compilers. Due to those challenges, existing SIMD compilers have excluded loops with array indirection from their candidate loops for SIMD vectorization. However, addressing those challenges is inevitable, since many important compute-intensive applications extensively use array indirection to reduce memory and computation requirements. In this work, we propose a method to generate efficient SIMD code for loops containing indirected memory references. We extract both inter- and intra-iteration parallelism, taking data reorganization overhead into consideration. We also optimally place data reorganization code in order to amortize the reorganization overhead through the performance gain of SIMD vectorization. Experiments on four array indirection kernels, which are extracted from real-world scientific applications, show that our proposed method effectively generates SIMD code for irregular kernels with array indirection. Compared to the existing SIMD vectorization methods, our proposed method significantly improves the performance of irregular kernels by 91%, on average.