Characterization of Bond Wire Interconnects in QFN Packages

Since several years ago, many semiconductors companies have invested a lot of efforts and resources in the wire bonding conversion from gold (Au) wire to copper (Cu) wire in order to achieve the most competitive cost. Meanwhile, the fast growing mobile application and industry continues to leap forwards with miniaturization especially in the most popular QFN (Quad Flat No-lead) packages. From multiple analysis, it looks like breakthrough competitive edge will depend on the success of running wire bonding process of both wire types (Au & Cu) with the ultimate ultra-fine pitch (UUFP) process on the flimsy QFN leadframes. This new process can aim for targeted pitch size of 20um which is the smallest possible in the industry, and most likely it will become the ultimate pitch size for now and future. There are many challenges in the development of such process with major considerations and evaluations focusing on various designs, hardware, machine capability, process constraints, process control and amplification of respective Au and Cu wire process issues. The UUFP process is firstly started with design considerations on both direct and indirect material. From the discussions with major bonding wire suppliers, current feasible wire size of Au wire is 0.4 mils and Cu wire size is 0.5 mils. With both wires selected, next design consideration is the capillary design. The capillary tip needs to be the smallest possible together with the tightest tolerance of every major dimension. These requirements resulted in extremely tedious fabrication process which requires new molding tool and process enhancement. Furthermore, such small capillary can also encounter robustness issue due to the thin capillary wall and dimension tolerances. Upon receiving the wire and capillary, the subsequent challenge is the machine capability. There are two important considerations, resolution of process parameters (ultrasonic power and force) and bonding placement accuracy. In the previous development of 30/35 um pitch, whereby it was found that bond force requirement already hitting only several grams. It is expecting that the UUFP process will require even more stringent process window. It is expected few 0.1 gram force may result in significant change in the wire bonding responses. Despite that, the conventional process issues will get worse, which include resonance effect of QFN wire bonding, Au wire challenges (IMC growth, reliability risk) and Cu wire challenges (lifted ball, crater, short-tail). Therefore, the process window development can be extremely difficult. In order to obtain better success rate, comprehensive six sigma method is highly recommended. Upon completion of process window development, a series of robustness tests should be performed. There are some unique robustness tests which can disclose any potential issue or risk. Upon completion of bonding success, the bonded units will be loaded into reliability test for standard tests and extended tests. Sometimes, the entire development process may need to be repeated from the beginning design phase if there is any stubborn quality issue. With the utilization of comprehensive methodology, the new UUFP process is applicable to full production mode in near future. This process is believed to be the ultimate process for wire bonding pitch, for both Au & Cu wire types.

The work presented in this paper focused on moisture effects in quad flat no-lead (QFN) during the precondition test. It is well established that microelectronic packaging absorbs moisture when exposed to humid ambient conditions during the precondition test and storage. In such cases, polymer materials (molding compound and epoxy) absorb the moisture and expand, resulting in hygro-mechanical stress that causes interface delamination. To accurately simulate the moisture distribution in QFN, in this work, the moisture mechanism pertaining to material properties was investigated. Molding compound and silver epoxy were evaluated to obtain the moisture distribution according to measure data in the reference paper. In addition, finite element analysis (FEA) was performed to analyze the wetness distribution in QFN packages. Finally, the reliability of QFN was enhanced by investigating the moisture behavior of the materials comprising the QFN.

Since its introduction in 1998, the quad flat no-lead (QFN) package has been used widely in semiconductor industry for various applications. In the past few years, advanced QFN packages with large body sizes (>10 mm) and multi-row bottom I/O terminals (two or more rows) have emerged as a cost & performance competitive alternative to other BGA styles packages, particularly for small form factor products. The application space of advanced QFN packages is determined by the solder joint reliability when the packages are assembled on the printed circuit board (PCB). This paper presents a comprehensive study on the modeling and testing of board level reliability for selected advanced QFN packages. A parametric, three-dimensional (3D) finite element model was developed for the large body size, multi-row, and fine pitch QFNs on board with considerations of detailed pad design, realistic shape of solder joint and solder fillet, and non-linear material properties. The modeling predicted fatigue life was first correlated to thermal cycling test results using curve-fitting techniques. The model has the capability to predict the fatigue life of solder joint during thermal cycling test within a certain error range. Then, design for reliability and assembly analyses were performed to study the effects of various key package and PCB design parameters including package and die dimensions, material properties, and PCB pad design layout for both the signal and ground/thermal pads, and thermal cycling test conditions. The results from modeling and reliability testing were used to develop best practice design and assembly recommendations.

In this study, an equivalent model of bonding wire used in the Ka-band quad flat no-lead (QFN) package was proposed. The proposed equivalent model was constructed using resistors and inductors according to the length of the bonding wire and the mutual inductance between the multi-bonding wires. For verification, the S-parameters derived from the equivalent model were compared with the three-dimensional (3D) electromagnetic simulation results. Moreover, a Ka-band QFN package was designed using the proposed equivalent model. The number and length of the bonding wires required to optimize the return loss (S11) and the insertion loss (S21) of the designed Ka-band QFN package were derived and applied. In the fabricated Ka-band QFN package, the S11 and S21 were measured to be −26 dB to −1.8 dB at 29 GHz, respectively, and it was confirmed that the measurement results were similar to the simulation results.

It is clear that the future belongs to the ever shrinking component. The Micro Lead Frame (MLF) component and specifically Quad Flat No-Lead (QFN) packages, have gained wide scale acceptance. They typically appear in densely populated boards where real estate is at a premium. As with all components, size and pitch continue to narrow, leaving traditional hand rework behind. QFN center thermal pads and fine-pitch outer pads continue to challenge the rework world. With 0.4mm pitch in production and talk of 0.3mm pitch coming, the challenges to a repeatable rework process will be examined. The design, size and assembly process of QFN's present some unique rework challenges not seen with other components. This paper will focus on the complete rework process, including component removal, site preparation, component paste printing, and finally new component soldering. The stencil design and paste process will be looked at in depth and soldering results evaluated. Triple row QFN's will be the test case.

Bottom Termination Components (BTC) are preferred to other package types due to their good electrical and thermal performance. Fine pitch BTCs require thorough printing evaluation to determine the proper Solder Paste (SP) type to be used in the assembly process. Since the inspection of solder joint quality is difficult compared to other surface mount packages, it is critical to determine the optimum Solder Paste Inspection (SPI) tolerance setting to avoid solder defects. In this study, a PCB with 0.40 mm pitch Quad Flat No-lead (QFN) components was used for the print study. In the first phase, Type 3 and Type 4 lead-free SPs were used to study the optimum tolerance setting and understand the SP volume distribution in the QFN package. In the second phase, rework process development of the QFN package is presented. Unlike Ball Grid Array (BGA) rework, BTC rework poses many new challenges. In the case of BTC, there is no solder material present on the component side and it has different pad configurations and pitches. This makes printing SP on the PCB pads or on the component pins challenging in rework process. As a part of this study, a method of printing SP on the component side, rework process, and microstructure evaluation of the reworked BTC were carried out. Type 4 SP was seen to improve printing performance compared to Type 3 SP. Both tested rework methods show good solder joint structure. Finally, reworked solder joints show good reliability as compared to non-reworked solder joints.

We have developed a proprietary package that is fully compatible with variously sized chips. In this paper, we present design and development of a Quad Flat No-Lead (QFN) package. We will show how we have built and characterized low-loss packages using standard Printed Circuit Board (PCB) laminate materials. In particular, this package has been developed using Liquid Crystal Polymer (LCP). These packages are unique in that they fully account for and incorporate solder joint and ball bond wire parasitic effects into design. The package has a large cavity section that allow for a variety of chips and decoupling capacitors to be quickly and easily packaged. Insertion loss through a single package transition is measured to be less than 0.4 dB across DC to 40 GHz. Return losses are measured to be better than 15 dB up through 40 GHz. Further, a bare die low noise amplifier (LNA) is packaged using this technology and measured after being surface mounted onto PCB. The packaged LNA is measured to show 19 dB gain over 32 GHz to 44 GHz. Return loss for both bare die and packaged version show no difference, and both measure 15 dB. The LCP package LNA exhibits 4.5 dB noise figure over 37 GHz to 40 GHz.

The electronics industry has been moving towards lead-free solders since 2006; Sn96.5 Ag3.0 Cu0.5 (SAC305) and Sn96.5 Ag1.0 Cu0.5 ( SAC105) have been the popular solder alloys in the industry. The reliability of such alloys is an issue for thermal applications in long-term use. In this paper, the effect of different combination of solder pastes, solder sphere alloys and surface finishes are studied. The test vehicle consists of 15mm and 6mm Ball Grid Array (BGA) components, 5mm Quad Flat No-lead (QFN) packages and 2512 Surface Mount Resistors (SMR). The test vehicles were assembled using different solder pastes onto a 6 layer printed circuit boards. The boards are isothermally aged boards at 125°C for 12 months are thermally cycled between -40°C to +125°C. Since there were not many failures for 6mm BGAs, QFNs and SMRs, only data regarding 15mm BGAs were used in the study. Two-parameter Weibull analysis is used to analyze the failure data and observe the life degradation of the solder joints based on different factors such as solder pastes, solder sphere alloys and surface finishes. It was observed that in most cases, the same surface finish and the same solder sphere alloy performed better than others.

High-performance IC-to-antenna interconnection is one of the key enablers for the mass production of high-end millimeter wave (mmW) radar systems above 100 GHz. In this work, a radar system with an on-package antenna array working at 122 GHz is presented. The antenna is placed on top of the molded package and the antenna-to-chip interconnection is realized by through-polymer via (TPV) technology. The detailed fabrication process of the radar antenna-in-package (AiP) with TPV is discussed. The results from the functional tests of the radar AiP are presented and benchmarked to a commercial quad-flat no-leads (QFN) package with an open antenna cavity. The detection margin between the echo signal and the constant false alarm rate (CFAR) threshold is approximately 10 dB higher for the TPV radar AiP compared with the benchmarked commercial QFN package.

This paper presents a 2-stage GaN Doherty power amplifier module (DPAM) on a compact 7×7 quad flat no-lead (QFN) package, designed for the needs of 5G massive MIMO base transceiver systems. The interstage and input matching networks employ high-quality factor integrated passive devices (IPDs) to achieve a small form factor. This multi-chip module consists of three GaN-HEMT bare dies used for the driver stage, carrier amplifier, and peaking amplifier. Additionally, two IPD dies are included for the interstage and input matching networks. The external load network is developed using a printed circuit board (PCB). Utilizing a 5G NR signal of 100 MHz bandwidth and a 9.3 dB PAPR within the 3.4–3.8 GHz band, the developed DPAM demonstrated a power gain exceeding 26.8 dB and a power-added efficiency (PAE) greater than 37.8% at a 39 dBm average output power.

Application of deuterium oxide (D2O) isotope tracing technique for encapsulated QFN failure analysis

This paper presents an innovative additive manufacturing approach leveraging an organic interposer for low-parasitic and low-loss heterogeneous integration of monolithic microwave integrated circuits (MMICs) at RF and millimeter-wave (mm-wave) frequencies. The methodology involves precise fabrication of patterned cavities within the interposer to seamlessly embed MMICs. Conductive inks, micro-dispensed and cured to form lateral interconnections and integrated chip carriers, are further refined by pico-second pulsed laser micromachining to achieve micrometer-scale accuracy. This laser refinement significantly improves reflection coefficients, facilitating wideband impedance matching. Experimental validation through simulation and measurement of S-parameters for an embedded MMIC distributed amplifier demonstrates superior performance as compared to traditional wire-bonded quad flat no-lead (QFN) packages, with low interconnect attenuation (0.028 dB/mm at 5 GHz, 0.187 dB/mm at 20 GHz, and 0.512 dB/mm at 30 GHz). A system-in-package (SiP) protoype, comprising a cascaded MMIC amplifier and filter as a receiver module, achieved return losses below 10 dB and low package loss. Enhanced laser trimming and de-embedding techniques further reduced return losses beyond 27 dB and decreased insertion losses by 0.5-0.8 dB up to 30 GHz, significantly improving fabrication tolerance and performance consistency. Also, this study introduces and validates an equivalent circuit model for ground-signal-ground (GSG) probe pads up to 40 GHz repeatedly fabricated by laser-enhanced direct-print additive manufacturing (LE-DPAM) for several devices under test (DUTs). The findings offer critical insights for future development and verification of LE-DPAM foundry-compatible process design kits (PDKs), highlighting transformative potentials of additive manufacturing for advanced heterogeneous integration of MMICs, RFICs, and mixed-signal circuits.

Various quad-flat no-lead (QFN) packages, land grid arrays (LGA) and ball grid arrays (BGA) are being combined on a number of products with ever increasing component densities and complexities. The bottom terminated component’s (BTC) small footprint, low cost, and excellent electrical as well as thermal performance make them a preferred solution for a wide range of applications. The purpose of this study is to determine which in-process optimization techniques may be utilized to reduce voids and HiP type defects on complex assemblies. Techniques such as reflow profile adjustment and stencil design modifications will be explored, as they are applied to a 6 layer Cu-OSP test vehicle built with multiple devices including QFN, LGA, BGA, dPAK and other components. A common SAC alloy, Halogen-Free, No-Clean, Type 3 solder paste was used for these tests.

This brief presents a sub-2 dB noise figure (NF) packaged wideband receiver front-end for high sensitivity multi-standard radio. An inductive source degeneration technique with a low- $V_{T}$ CMOS transistor is adopted in composite pair low noise amplifier (CPLNA) to extend the bandwidth and to improve the NF, a current commutating multi-gate transistor pair (MGTR) down conversion passive mixer for better linearity of the packaged receiver. Fabricated in 65 nm CMOS technology, the receiver provides a maximum conversion voltage gain of 37 dB and NF of 1.85–2 dB with a 3 dB bandwidth from 0.3 GHz to 3 GHz in quad-flat no-leads (QFN) package. The receiver has a third-order intermodulation intercept point (IIP3) of −7 dBm at 2 GHz and consumes a 44.5 mW power (LNA + Mixer).

We present the design and test results of a Drivers and Limiting AmplifierS ASIC operating at 10 Gb/s (DLAS10) and three miniature optical transmitter/ receiver/transceiver modules (MTx+, MRx+, and MTRx+) based on DLAS10. DLAS10 can drive two transmitter optical subassemblies (TOSAs) of vertical cavity surface emitting lasers (VCSELs), receive the signals from two receiver optical subassemblies (ROSAs) that have no embedded limiting amplifiers (LAs), or drive a VCSEL TOSA and receive the signal from a ROSA, respectively. Each channel of DLAS10 consists of an input continuous time linear equalizer (CTLE), a four-stage LA, and an output driver. The LA amplifies the signals of variable levels to a saturation amplitude of 800 mV (peak-peak). The output driver drives VCSELs or impedance-controlled traces. DLAS10 is fabricated in a 65-nm CMOS technology. The die is 1 mm ×1 mm. DLAS10 is packaged in a 4 mm ×4 mm 24-pin quad-flat no-leads (QFNs) package. DLAS10 has been tested in MTx+, MRx+, and MTRx+ modules. Both measured optical and electrical eye diagrams pass the 10-Gb/s eye mask test. The input electrical sensitivity is 40 mVp-p, while the input optical sensitivity is -12 dBm. The total jitter of MRx+ is 29 ps (P-P) with a random jitter of 1.6 ps (rms) and a deterministic jitter of 9.9 ps. Each MTx+/MRx+ module consumes 82.6 and 174.4 mW/ch, respectively.