Eliminating BTC Voiding on the Fly: In-Production Optimization Techniques

This study is part three in a series of papers on voiding in solder joints and methods for mitigation of voids. In this study several new variables were tested and compared to previous data on voiding. A new circuit board design was used which is different than the circuit board used in previous studies. The new circuit board design includes two sizes of QFNs (Quad Flat No Lead), BGA's (Ball Grid Array), and LGA (Land Grid Array) components which are susceptible to voiding. The following variables were evaluated with respect to voiding: Solder powder size was varied using a no-clean lead-free solder paste and IPC Type 3, Type 4 and Type 5 SAC305 solder powders. Solder alloy was studied using SAC305 alloy, SN100C® alloy, SN100CV® alloy and a mixture of SAC305/SN100C alloys. Surface finish on the circuit board is thought to have an impact on voiding. Organic solderability preservative (OSP) surface finish is more difficult to wet with solder than other surface finishes and in theory should produce higher voiding levels, and this was evaluated with multiple solder pastes. The performance of a new “low voiding” no clean solder paste was compared to other industry standard no clean solder pastes. Several new stencil designs on QFN thermal pads were tested. Data was gathered and statistical analysis performed to compare and contrast the voiding data. What was learned from this work is summarized below: Solder powder particle size affects voiding for some solder pastes. Voiding tends to decrease as solder powder size becomes smaller. Solder alloy affects voiding and seems to follow a trend with melting range. Wider melting ranges tend to generate lower voiding levels. Organic solderability preservative (OSP) surface finish gave higher voiding than electroless nickel immersion gold (ENIG) surface finish for a no clean lead free solder paste that was tested. Two different water soluble lead free solder pastes showed similar voiding levels for OSP and ENIG finishes. New “low voiding” solder pastes are becoming more common in our industry. In this work, low voiding solder paste F showed lower voiding than an industry standard solder paste C. Stencil design has an impact on voiding. In this study, area of printed solder paste coverage was varied. Voiding levels were much higher for 50 to 60% solder paste coverage than for 70 to 80% solder paste coverage. Based on the results of this work, the following recommendations were made to reduce voiding. Use of smaller solder powder sizes can reduce voiding with certain types of solder paste. Use of specific solder alloys may help mitigate voiding. Use a solder paste that works well with the surface finish to minimize voiding. Use “low voiding” solder pastes to reduce the overall potential for voiding. Optimize the stencil design for the components to allow for complete wetting and gas escape routes. Applying these recommendations may create issues on the printed circuit board assembly (PCBA). For example, use of smaller solder powder particle sizes may lead to increased random solder balling and/or graping. Increasing the volume of printed solder paste may lead to bridging for micro BGA and ultra-fine pitch components. Reduction of voiding may be important enough to risk these potential issues. This is left to the reader's judgement. It is the intent of this work to analyze general trends in voiding and give recommendations to help the reader to “Fill the Void.

A Land Grid Array (LGA) is an area array component similar to a Ball Grid Array (BGA), but without solder balls attached to the bottom surface of the package. Due to the absence of solder balls, the LGA package has a lower thickness as compared to an equivalent BGA package. Accordingly, this reduces the thickness of the module assembly. This is a critical consideration especially for modules using stacked packages. On the other hand, the lower standoff height of the solder joints could have an impact on the performance of the package during temperature cycling. For high density modules, along with ‘minimizing’ the thickness, it is desirable to avoid increasing the package size in the length and width directions. This allows maintaining the same number of Inputs/Outputs (I/Os) as a comparable BGA device and accommodates the package on existing Printed Circuit Board (PCB) designs. For this reason, the LGA package used for the current research was identical to the BGA device that is currently used for the stacked package, but without solder balls on the bottom side. The stacked package utilizing these LGA devices and the modules were assembled using Sn3.8Ag0.7Cu lead-free solder. The reliability of the assembly was assessed using thermal cycling test. Based on the results, the first failure was recorded at the end of 1250 thermal cycles, whereas the comparable stacked package using BGA components was able to withstand 1500 cycles without failures. Dye & pry analysis was also performed on the failed stacked packages as a part of failure analysis.

The electronics industry has been moving towards lead-free solders since 2006; Sn96.5 Ag3.0 Cu0.5 (SAC305) and Sn96.5 Ag1.0 Cu0.5 ( SAC105) have been the popular solder alloys in the industry. The reliability of such alloys is an issue for thermal applications in long-term use. In this paper, the effect of different combination of solder pastes, solder sphere alloys and surface finishes are studied. The test vehicle consists of 15mm and 6mm Ball Grid Array (BGA) components, 5mm Quad Flat No-lead (QFN) packages and 2512 Surface Mount Resistors (SMR). The test vehicles were assembled using different solder pastes onto a 6 layer printed circuit boards. The boards are isothermally aged boards at 125°C for 12 months are thermally cycled between -40°C to +125°C. Since there were not many failures for 6mm BGAs, QFNs and SMRs, only data regarding 15mm BGAs were used in the study. Two-parameter Weibull analysis is used to analyze the failure data and observe the life degradation of the solder joints based on different factors such as solder pastes, solder sphere alloys and surface finishes. It was observed that in most cases, the same surface finish and the same solder sphere alloy performed better than others.

Despite the prevalence of reliability tests throughout the electronics packaging industry, only a relatively small number of them are used to help predict the actual in-service life for an electronics assembly. Much more often ‘engineering testing’ is essentially focused on comparisons to previous performance or between different designs, materials, or process parameters. Empirical testing can, however, often be misleading. For example, Ball Grid Array (BGA) assemblies on a specific product are found to have longer lives than Thin Small-Outline Packages (TSOP) assemblies in accelerated thermal cycling. In order for this result to be meaningful a vital question is then: Are the acceleration factors the same and, if not, how do they differ? Significant knowledge has been gathered about the performance of lead-free solder joints in thermal cycling. A systematic mechanistic understanding has been established in the case of typical BGA joints and we are starting to develop guidelines for comparisons of accelerated test results [1-4]. Nevertheless, a serious concern is that very different solder joint configurations (e.g., those with very different shapes and/or ratios of solder volume-to-pad areas) may lead to different solder microstructures and, therefore, different acceleration factors. We have addressed this concern for Land Grid Array (LGA), TSOP, and Quad Flat No-Lead (QFN) assemblies with SAC 305 solder joints by a combined study of the initial post-reflow solder microstructure, its subsequent evolution, and the associated type and propagation of damage. Based on a discussion of the results, judgments were made as to whether acceleration factors to long term service conditions are likely to be similar to or different from those for BGA assemblies.

Bottom Termination Components (BTC) are preferred to other package types due to their good electrical and thermal performance. Fine pitch BTCs require thorough printing evaluation to determine the proper Solder Paste (SP) type to be used in the assembly process. Since the inspection of solder joint quality is difficult compared to other surface mount packages, it is critical to determine the optimum Solder Paste Inspection (SPI) tolerance setting to avoid solder defects. In this study, a PCB with 0.40 mm pitch Quad Flat No-lead (QFN) components was used for the print study. In the first phase, Type 3 and Type 4 lead-free SPs were used to study the optimum tolerance setting and understand the SP volume distribution in the QFN package. In the second phase, rework process development of the QFN package is presented. Unlike Ball Grid Array (BGA) rework, BTC rework poses many new challenges. In the case of BTC, there is no solder material present on the component side and it has different pad configurations and pitches. This makes printing SP on the PCB pads or on the component pins challenging in rework process. As a part of this study, a method of printing SP on the component side, rework process, and microstructure evaluation of the reworked BTC were carried out. Type 4 SP was seen to improve printing performance compared to Type 3 SP. Both tested rework methods show good solder joint structure. Finally, reworked solder joints show good reliability as compared to non-reworked solder joints.

PurposeSolder paste printing is the most common method for attaching surface mount devices to printed circuit boards (PCB), and it has been reported that a majority of all assembly defects occur during the stencil printing process. It is also recognized that the solder paste printing process is wholly responsible for the solder joint formation of leadless package technologies such as land grid array (LGA) and quad-flat no-lead (QFN) components and therefore is a determining factor in the long-term reliability of said devices. The aim of this experiment is to determine the acceptable lower limit for solder paste volume deposit tolerances during stencil printing process to ensure both good assembly yield and reliability expectations.Design/methodology/approachStencils with modified aperture dimensions at particular locations for LGA and QFN package footprints were designed to vary the solder paste volume deposited during the stencil printing process. Solder paste volumes were measured using solder paste inspection system. Low volume solder paste deposits were generated using the modified stencil designs to evaluate assemble yield. Accelerated thermal cycling (ATC) was used to determine the reliability of the solder joints. Failure analysis was used to determine if the failure was attributed to the low paste volume locations.FindingsSolder joints formed with nominal paste volume survived longer in ATC compared to intentionally low volume joints. Transfer efficiency numbers for both good assembly yield and good reliability are reported for LGA and QFN devices. A lower volume limit is reported for leadless devices that should not significantly affect yield and reliability in thermal cycling.Originality/valueVery little literature is available on solder paste volume tolerance limits in terms of assembly yield and reliability. Manufacturers often use ±50 or ±30 per cent of stencil aperture volume with no evidence of its effectiveness in determining yield and reliability of the solder joints.

Package surface coating technology has been around for years. It can be used to protect assembly product from the interference of electromagnetic wave. The industry generally uses PVD sputter method to complete the package surface coating process. So far, the surface coating for land grid array (LGA) has been mass produce by many different suppliers. But, ball grid array (BGA) product with PVD sputter process still faces a lot of issue with process control. The main bottleneck for BGA surface coating with sputter process is the high temperature (>250oC) generated by ion collision during PVD process and back side deposition (BSD) defect. When the temperature is greater than the melting point of solder balls (217oC), the solder ball will melt and lead function fail. But PVD sputter require high vacuum environment to keep processing stable. Back side deposition is another main problem for package surface coating, because BSD will cause pin short to happen. Therefore, a method of lowering the temperature during PVD sputter process and avoiding BSD is the key point for BGA surface coating technology. For the temperature issue, the most viable way to transfer heat in high vacuum deposition chamber is by contact. But it is hard to find a suitable material which can endure high temperature (>250oC) without gas releasing during process and not affect the product. So far, several different kind of silicone type material such as PI base silicone tape or silicone glue and silicone film have been tested to produce BGA product with surface coating layer. As result shows, silicone can help transfer heat from BGA into metal carrier to lower the temperature. To achieve lowering of temperature, alumina is chosen as the main metal to produce the carrier due to its high heat capacity. Silicone can also protect the substrate from back side deposition by sealing the PKG edge of backside with the silicone material. To sum up, we can lower the process temperature from 280°C to less than 160°C by using silicone to transfer heat from the package to metal carrier.

Since several years ago, many semiconductors companies have invested a lot of efforts and resources in the wire bonding conversion from gold (Au) wire to copper (Cu) wire in order to achieve the most competitive cost. Meanwhile, the fast growing mobile application and industry continues to leap forwards with miniaturization especially in the most popular QFN (Quad Flat No-lead) packages. From multiple analysis, it looks like breakthrough competitive edge will depend on the success of running wire bonding process of both wire types (Au & Cu) with the ultimate ultra-fine pitch (UUFP) process on the flimsy QFN leadframes. This new process can aim for targeted pitch size of 20um which is the smallest possible in the industry, and most likely it will become the ultimate pitch size for now and future. There are many challenges in the development of such process with major considerations and evaluations focusing on various designs, hardware, machine capability, process constraints, process control and amplification of respective Au and Cu wire process issues. The UUFP process is firstly started with design considerations on both direct and indirect material. From the discussions with major bonding wire suppliers, current feasible wire size of Au wire is 0.4 mils and Cu wire size is 0.5 mils. With both wires selected, next design consideration is the capillary design. The capillary tip needs to be the smallest possible together with the tightest tolerance of every major dimension. These requirements resulted in extremely tedious fabrication process which requires new molding tool and process enhancement. Furthermore, such small capillary can also encounter robustness issue due to the thin capillary wall and dimension tolerances. Upon receiving the wire and capillary, the subsequent challenge is the machine capability. There are two important considerations, resolution of process parameters (ultrasonic power and force) and bonding placement accuracy. In the previous development of 30/35 um pitch, whereby it was found that bond force requirement already hitting only several grams. It is expecting that the UUFP process will require even more stringent process window. It is expected few 0.1 gram force may result in significant change in the wire bonding responses. Despite that, the conventional process issues will get worse, which include resonance effect of QFN wire bonding, Au wire challenges (IMC growth, reliability risk) and Cu wire challenges (lifted ball, crater, short-tail). Therefore, the process window development can be extremely difficult. In order to obtain better success rate, comprehensive six sigma method is highly recommended. Upon completion of process window development, a series of robustness tests should be performed. There are some unique robustness tests which can disclose any potential issue or risk. Upon completion of bonding success, the bonded units will be loaded into reliability test for standard tests and extended tests. Sometimes, the entire development process may need to be repeated from the beginning design phase if there is any stubborn quality issue. With the utilization of comprehensive methodology, the new UUFP process is applicable to full production mode in near future. This process is believed to be the ultimate process for wire bonding pitch, for both Au & Cu wire types.

Flip-chip carriers have become the preferred solution for high-performance ASIC and microprocessor devices. Typically these are packaged in organic or ceramic Ball Grid Array (BGA) packages. IBM has developed both Ceramic Ball Grid Array (CBGA) and Ceramic Column Grid Array (CCGA) packages which cover a wide range of package I/O capabilities required for high-performance devices, typically between 300 to more than 1600 I/O. Recently, there has been a lot of interest in Pb-free solders to replace typical Pb-based solders such as eutectic Sn-Pb used for balls in plastic BGAs (PBGA) for their assembly. The common feature of all proposed Pb-free solder alloys to date is that they are all Sn-based solders with the wt.% of Sn in the alloy typically greater than 90%. Antimony-based lead-free solders have been considered, but recently there has been a concern over the use of antimony (Sb) as well. The leading antimony-free (Sb-free) solder that has emerged from various Pb-free solder evaluations by industry and academic consortia at present is: 95.5Sn/3.8Ag/0.7Cu (SAC). The primary issues with changing from high-Pb based solders that are used in BGA assembly to electronic cards are: (1) wettability of the Pb-free solders to both Ni/Au I/O pads typically used in ceramic BGAs and card lands (Cu or Cu tinned with solder paste) with water soluble or no-clean fluxes; (2) the rate of intermetallic growth and its structure, with much higher Sn containing Pb-free solders; and (3) thermal fatigue reliability of the CBGA joints to organic cards. In this paper, initial assessment of a few leading Pb-free solders regarding wettability, microstructure and thermal fatigue life for CBGA applications is presented.

The work presented in this paper focused on moisture effects in quad flat no-lead (QFN) during the precondition test. It is well established that microelectronic packaging absorbs moisture when exposed to humid ambient conditions during the precondition test and storage. In such cases, polymer materials (molding compound and epoxy) absorb the moisture and expand, resulting in hygro-mechanical stress that causes interface delamination. To accurately simulate the moisture distribution in QFN, in this work, the moisture mechanism pertaining to material properties was investigated. Molding compound and silver epoxy were evaluated to obtain the moisture distribution according to measure data in the reference paper. In addition, finite element analysis (FEA) was performed to analyze the wetness distribution in QFN packages. Finally, the reliability of QFN was enhanced by investigating the moisture behavior of the materials comprising the QFN.

Area array components are increasingly used to miniaturize modern day circuitry. Assembling these surface-mount components using lead-free solder pastes has been the subject of interest for several years. Reworking a ball grid array (BGA) is complicated as the solder joints are hidden underneath the component. The process window to rework a BGA is narrow. There are several critical factors which complicate and affect the repeatability of the rework process. The objective of this research is to develop a reliable and repeatable process to rework lead-free fine-pitch BGAs. The process steps to rework a BGA are component removal, site redressing, solder paste/flux deposition, component replacement, and reflow. This study applied designed experiments to evaluate multiple alternatives for several rework process steps. Two alternatives for site redressing, namely copper wick with soldering iron and vacuum desoldering are evaluated. Similarly, the application of solder paste versus flux is compared. A localized reflow method at the rework machine is compared with solder reflow using a reflow oven. The pros and cons of using the two reflow methods and the effect of multiple reflow cycles on solder joint reliability is discussed. Nozzles with and without thermal shields were evaluated. A nozzle with deflectors on the outer side was found to work satisfactorily. Localized reflow in a semiautomated rework machine resulted in partial reflow of components adjacent to the reworked BGA. Thermal repeatability was also a concern. A 15degC drop in temperature was observed with the use of CoolCaps. The soldering iron with wick redressing method was less time consuming. Applying paste using a ministencil posed challenges due to lack of real-estate around the reworked BGA. A reliability study consisting of cross-sectional analysis, scanning electron microscopy (SEM), thermal shock, and thermal cycling were conducted to determine the reliability of the reworked solder joints. The copper wick with soldering iron method was favorable in terms of cycle time. The reflow oven is preferred as it avoids partial reflow of adjacent components. Localized reflow is effective when CoolCaps are used. The flux attachment process was easier as the real-estate around the reworked BGA is very limited. All the assemblies subjected to thermal shock and cycling passed the functional test.

This paper discusses models and measurements of bond wire interconnects in Quad-Flat No-lead (QFN) packages. A bond wire interconnect between a 3 mm, 14-lead QFN lead frame and a GaAs chip is used as an example to demonstrate the modelling and measurement process. Measurement results are compared with extracted models and electromagnetic (EM) simulations to verify model and simulation accuracy. Based on the extracted simplified model, theoretical bandwidth limitations of bond wire interconnects are discussed.

A Land Grid Array (LGA) package was designed and fabricated to utilize specific materials and design concepts for high speed operation. The performance of this LGA was compared with that of a functionally and dimensionally equivalent Pin Grid Array (PGA) that is currently being used to package high speed silicon ECL gate arrays. Two structures that were sources of signal degradation in the PGA, the pins and a layer of plating lines, were eliminated in the design of the LGA. The package was fabricated out of Du Pont Green Tape low temperature co-fired ceramic (LTCC) with gold conductors and vias. This combination of an improved LGA, structure and materials with superior high speed properties resulted in a package with improved performance and decreased signal degradation when compared with conventional high temperature co-fired ceramic (HTCC) PGAs. Time domain reflectometry measurements of the LGA, when compared with those of the equivalent PGA, showed less than half the deviation from a 50 /spl Omega/ characteristic impedance. A 'package risetime' performance factor, which describes the contribution the package makes to the output risetime, was calculated from time domain transmission (TDT) data. These results also showed significantly improved performance in the LGA. For the best line in the LGA, the package risetime was 104 ps, which is a 98% improvement over the equivalent line in the PGA. A ground delay effect due to the separation between the signal I/O and nearest ground I/O was observed. This effect, which increased with increasing signal-nearest ground I/O spacing, was seen to cause significant degradation and increased risetimes that should be avoided in high speed packages.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The impact of voiding on BGA (Ball Grid Array) solder joint reliability has been a debatable topic for some time. It is believed that certain categories of voiding do not significantly affect the reliability of the solder joints and that voiding is preferred and acceptable to a certain extent. The reason for this is that voids are believed to change the direction of, or halt the propagation of cracks and thereby improve the reliability of the solder joint. However, excess voiding is considered to aggravate the solder joint failure. The formation of voids can be attributed to different process parameters – surface contamination and moisture absorption in BGAs and Printed Circuit Boards (PCBs), solder paste &amp; operating conditions and reflow profiles – to mention a few. Among these, the reflow profile is one of the very critical parameters in electronics manufacturing. Several experiments have been conducted in the past to study the impact of reflow profile. In addition, the electronics manufacturing industry is gradually moving towards a lead-free environment. This has resulted in higher peak temperatures for the reflow profiles. However, with higher peak temperatures, the other reflow parameters also have to be varied. An optimum range for all the reflow parameters would reduce (or even eliminate) the formation of solder voids. This paper investigates the impact of the reflow profile on the quality of the lead-free surface mount solder joint. In particular, the impact of the reflow profile on solder joint voiding for lead-free assemblies is analyzed. The critical reflow profile parameters that are responsible for voiding such as preheat temperature, ramp-up rate, and peak temperature were varied within the allowable process limits to verify if the voiding could be minimized. Ball Grid Arrays (BGAs) were assembled using varying reflow profiles. The analysis involved x-ray examination to observe the formation of solder voids.

Since its introduction in 1998, the quad flat no-lead (QFN) package has been used widely in semiconductor industry for various applications. In the past few years, advanced QFN packages with large body sizes (>10 mm) and multi-row bottom I/O terminals (two or more rows) have emerged as a cost & performance competitive alternative to other BGA styles packages, particularly for small form factor products. The application space of advanced QFN packages is determined by the solder joint reliability when the packages are assembled on the printed circuit board (PCB). This paper presents a comprehensive study on the modeling and testing of board level reliability for selected advanced QFN packages. A parametric, three-dimensional (3D) finite element model was developed for the large body size, multi-row, and fine pitch QFNs on board with considerations of detailed pad design, realistic shape of solder joint and solder fillet, and non-linear material properties. The modeling predicted fatigue life was first correlated to thermal cycling test results using curve-fitting techniques. The model has the capability to predict the fatigue life of solder joint during thermal cycling test within a certain error range. Then, design for reliability and assembly analyses were performed to study the effects of various key package and PCB design parameters including package and die dimensions, material properties, and PCB pad design layout for both the signal and ground/thermal pads, and thermal cycling test conditions. The results from modeling and reliability testing were used to develop best practice design and assembly recommendations.