Characterizing Microarchitecture Soft Error Vulnerability Phase Behavior

Program power profiling based on phase behaviors

A superscalar pipeline applied Tomasulo's algorithm is presented in this paper. The design begins with a dual-issue superscalar processor based on LEON2. Tomasulo's algorithm is adopted to implement out-of-order execution. Instructions are separated into three different parts and executed by three different function units so as to reduce area and promote execution speed. Results wrote back into registers are still in program order, for the aim of ensure the function veracity. Mechanisms of the reservation station, common data bus, and reorder buffer are presented in detail. The structure can sends and executes three instructions at most at a time. Branch prediction can also be realized by reorder buffer. Performance of the scalar pipeline applied Tomasulo's algorithm is promoted by 41.31% compared to singleissue pipeline..

The development and implementation of performance metrics for assessing the impact of pharmacists' activities in ambulatory care clinics are described. Ambulatory care clinic pharmacists within an integrated health system were surveyed to ascertain baseline practices for documenting and tracking performance metrics. Through literature review and meetings with various stakeholders, priorities for metric development were identified; measures of care quality, financial impact, and patient experience were developed. To measure the quality of care, pharmacists' interventions at five ambulatory care clinics within the health system were assessed. Correlation of pharmacist interventions with estimated cost avoidance provided a measure of financial impact. Surveys were distributed at the end of clinic visits to measure satisfaction with the patient care experience. An electronic system for metric documentation and automated tabulation of data on quality and financial impact was built. In a 12-week pilot program conducted at three clinic sites, the metrics were used to assess pharmacists' activities. A total of 764 interventions were documented (a mean of 24 accepted recommendations per pharmacist full-time equivalent each week), resulting in estimated cost avoidance of more than $40,000; survey results indicated high patient satisfaction with the services provided by pharmacists. Biweekly report auditing and solicitation of feedback guided metric refinement and further training of pharmacists. Tools and procedures were established for future metric expansion. Development and implementation of performance metrics resulted in successful capture and characterization of pharmacists' activities and their impact on patient care in three ambulatory care clinics.

Improving building operation by tracking performance metrics throughout the building lifecycle (BLC)

Along with sharply increasing bandwidth requirements, modern network applications and new protocols demand highly intelligent and sophisticated processing over the network. Since these workloads require processing capability beyond state-of-the-art microprocessors, parallel architectures are required in order to handle the packet data without slowing down line speed. Network processors with various parallel architectures are appearing in the market, however, a thorough investigation of the implications of static versus dynamic scheduling of this class of emerging workloads has not been done. In this paper, we characterize the performance and power dissipation of statically identified ILP architectures, and we also compare them to dynamically scheduled architectures for network processing. In dynamically scheduled architectures, the power consumption of the instruction window greatly increases with increasing issue widths. On the other hand, statically scheduled architectures show better performance, as well as tremendous advantages in power, since they do not have instruction window wakeup/select, reorder buffer, and other scheduling related hardware modules. With the large parallelism and the loop nature of network applications, our experimental analysis supports static scheduling as an appropriate strategy for network processor applications.

A Wireless Intelligent Network for Industrial Control

This paper combines interval type-2 fuzzy logic with adaptive control theory for the control of a three degree-of-freedom (DOF) helicopter. This strategy yields robustness to various kinds of uncertainties and guaranteed stability of the closed-loop control system. Thus, precise trajectory tracking is maintained under various operational conditions with the presence of various types of uncertainties. Unlike other controllers, the proposed controller approximates the helicopter’s inverse dynamic model and assumes no a priori knowledge of the helicopter’s dynamics or parameters. The proposed controller is applied to a 3-DOF helicopter model and compared against three other controllers, i.e., PID control, adaptive control, and adaptive sliding-mode control. Numerical results show its high performance and robustness under the presence of uncertainties. To better assess the performance of the control system, two quantitative tracking performance metrics are introduced, i.e., the integral of the tracking errors and the integral of the control signals. Comparative numerical results reveal the superiority of the proposed method by achieving the highest tracking accuracy with the lowest control effort.

Network-centric multisensor-multitarget tracking has numerous advantages over single-sensor or single-platform tracking. In this paper, we present a solution to one of the main problems of network-centric tracking, namely, decentralized information sharing among the platforms participating in the distributed data fusion. This paper presents a decision mechanism that provides each platform with the required data for the distributed data fusion process while reducing redundancy in the information flow in the overall system. We consider a distributed data fusion system consisting of platforms that are decentralized, heterogeneous, and potentially unreliable. The proposed approach, which is based on Markov decision processes and decentralized lookup substrate, will control the information exchange process based, among the other parameters, on tracking performance metrics of individual platforms, thereby enhancing the whole distributed system's reliability as well as that of each participating platform. Simulation examples demonstrate the operation and the performance results of the system

With aggressive technology scaling, soft errors (changes in logic state arising from single-event transients due to radiation or electrical noise) are becoming a serious concern in logic circuits. Existing soft-error rate (SER) reduction schemes, which use explicit hardware and/or temporal redundancy, have significant power overheads and are impractical in systems where power is a key design metric. Our technique exploits the inherent redundancy of operand values across instructions by storing and reusing previously-computed results. Functional units are partitioned so that subunits operate on input subwords to generate output subwords that are combined to form the complete output word. We use a partitioned reuse cache which stores previously computed results for each functional subunit. The stored entries in the cache are compared against computed results of functional subunits to detect soft errors. We show that a partitioned reuse cache has a much better hit rate compared to a non-partitioned cache and it is possible to achieve SER reduction up to 51.87% in functional units with a power overhead of only 7.5%.

Modern microprocessors achieve high application performance at the acceptable level of power dissipation. In terms of power to performance trade-off, the instruction window is particularly important. This is because enlarging the window size achieves high performance but naive scaling of the conventional instruction window can severely increase the complexity and power consumption. In this paper, we propose low-power instruction window techniques for contemporary microprocessors. First, the separated reorder buffer (SROB) reduces power dissipation by deferred allocation and early release. The deferred allocation delays the SROB allocation of instructions until their all data dependencies are resolved. Then, the instructions are executed in program order and they are released faster from the SROB. This results in higher resource utilization and low power consumption.

High-performance superscalar processors have been adopted to satisfy the rising demand for processing applications of ever-growing complexity. This extra complexity, added to the increasing vulnerability of transistors due to technology scaling, poses a great challenge since these effects have also been proven to affect ground-level safety-critical applications. To increase microarchitectural resilience, designers may adopt Dual Modular Redundancy (DMR), which offers full fault detection. However, given that DMR incurs in high area and energy overheads, we propose a design-time methodology aiming to achieve the best tradeoff between resilience and area overhead, decreasing DMR costs and maintaining acceptable detection levels for such a complex design. This is done by adopting the Knapsack Problem (KSP) as a heuristic to identify the optimal micro-architectural structures that should be duplicated to achieve target resilience with the smallest possible area overhead. By injecting over 800k faults in 12 significant micro-architectural structures of different versions of the complex Berkeley Out-of-Order Machine (BOOM) superscalar processor modeled with RTL accuracy, we compare this optimal strategy against a greedy one, showing that 90% of vulnerability reduction may be achieved with 50.6% and 107.8% area overheads for the optimal and greedy strategies, respectively.

Performance, energy consumption and soft error have become parallel important design concerns for microprocessors. As the largest on-chip structures, cache memories play an impressive role in microprocessor design. The awareness of cache reliable energy-efficiency is highly important for microprocessor designers, especially at early design stage. The dynamic behavior of cache reliable energy-efficiency has been characterized, motivating the development of predicting reliable energy-efficiency to track runtime characteristics of cache. In this paper, a BART (Bayesian Additive Regression Trees) model is created to predict the reliable energy-efficiency of Level-1 data cache (L1D) accurately across different execution phases and benchmarks, as well as to illustrate the effects of performance metrics on L1D reliable energy-efficiency. Experimental results demonstrate the accuracy of BART in reliable energy-efficiency prediction, and present the intrinsic correlation between reliable energy-efficiency and the key performance metrics.

Cross-layer reliability is becoming the preferred solution when reliability is a concern in the design of a microprocessor-based system. Nevertheless, deciding how to distribute the error management across the different layers of the system is a very complex task that requires the support of dedicated frameworks for cross-layer reliability analysis. This paper proposes SyRA, a system-level cross-layer early reliability analysis framework for radiation induced soft errors in memory arrays of microprocessor-based systems. The framework exploits a multi-level hybrid Bayesian model to describe the target system and takes advantage of Bayesian inference to estimate different reliability metrics. SyRA implements several mechanisms and features to deal with the complexity of realistic models and implements a complete tool-chain that scales efficiently with the complexity of the system. The simulation time is significantly lower than micro-architecture level or RTL fault-injection experiments with an accuracy high enough to take effective design decisions. To demonstrate the capability of SyRA, we analyzed the reliability of a set of microprocessor-based systems characterized by different microprocessor architectures (i.e., Intel x86, ARM Cortex-A15, ARM Cortex-A9) running both the Linux operating system or bare metal in the presence of single bit upsets caused by radiation induced soft errors. Each system under analysis executes different software workloads both from benchmark suites and from real applications.

In recent years, modern CPUs have been suffering from Meltdown-type attacks. These attacks are delivered by exploiting transient execution created by a faulting load operation. A secret value is encoded into the cache by transient instructions, which in turn is deduced from a microarchitectural covert channel such as Flush+Reload. Recent studies on these attacks mainly focus on finding new vulnerable microarchitectural structures, while lacking interest in how many transient instructions can be executed in the transient execution. If attackers know the exact attack capacity, i.e., the maximum number of instructions available within a transient execution window, they will be able to maximize information leakage by executing additional transient instructions. In order to devise security solutions against Meltdown-type attacks, it is of crucial importance to measure and evaluate the attack capacity. In this paper, we quantitatively analyze the attack capacity in terms of the number of \(\mu \)ops, the latency of transient instructions, and the size of the Reorder Buffer (ROB). Specifically, we present our method in detail that measures the capacity by reconstructing the original implementations of Meltdown-type attacks. We analyze the attack capacity by conducting experiments with various CPU models and identify several elements that affect the capacity. Based on our findings, we propose two methods that reinforce the Meltdown-type attacks.

This paper presents a bi-level planning approach to find an optimal layout for a large-scale wind farm (WF) from economic and reliability perspectives. The upper level of the planning approach is formulated as constrained multi-objective optimization (MOO) to obtain the optimal WF layout, where two conflicting objectives are optimized simultaneously. Two objectives for MOO are i) yearly gross energy production and ii) annual loan repayment (for cable and land area of the WF), where the first objective is maximized and the second objective is minimized. Jensen's wake model is used to calculate the wake effect, and to evaluate the multiple wake effect within a WF, a coordinate-transformation-based approach has been adopted in this study. An efficient hybrid multi-objective metaheuristic algorithm, which is based on nondominated sorting multi-objective particle swarm optimization and improved archive multi-objective simulated annealing, has been proposed to find the optimized WF layout. The superiority of the Pareto front obtained by the proposed algorithm for the large-scale WF layout is supported by its comparison with different powerful and well-established MOO algorithms. In the lower level of the proposed approach, economic and reliability analyses of the solutions (WF layout), obtained in the Pareto front by the proposed hybrid algorithm, have been done. In this context, two performance metrics, a) generation economy index and b) expected wind energy generation (EWEG), have been considered. A sequential Monte Carlo simulation has been developed to calculate the EWEG considering random failure of both wind turbines and cables in this paper. The most suitable WF layout is selected by trading off between economy and reliability using a fuzzy decision-making approach.