Exploiting Statically Identified ILP for Network Processor Applications

Computer systems increasingly depend on exploiting program dynamic behavior to optimize performance, power and reliability. Prior studies have shown that program execution exhibits phase behavior in both performance and power domains. Reliabilityoriented program phase behavior, however, remains largely unexplored. As semiconductor transient faults (soft errors) emerge as a critical challenge to reliable system design, characterizing program phase behavior from a reliability perspective is crucial in order to apply dynamic fault-tolerant mechanisms and to optimize performance/reliability trade-offs. In this paper, we compute run-time program vulnerability to soft errors on four microarchitecture structures (i.e. instruction window, reorder buffer, function units and wakeup table) in a high-performance out-of-order execution superscalar processor. Experimental results on the SPEC2000 benchmarks show a considerable amount of time varying behavior in reliability measurements. Our study shows that a single performance metric, such as IPC, cache miss or branch misprediction, is not a good indicator for program vulnerability. The vulnerabilities of the studied microarchitecture structures are then correlated with program code-structure and run-time events to identify vulnerability phase behavior. We observed that both program code-structure and run-time events appear promising in classifying program reliability phase behavior. Overall, performance counter based schemes achieved an average Coefficient of Variation (COV) of 3.5%, 4.5%, 4.3% and 5.7% on the instruction queue, reorder buffer, function units and the wakeup table, while basic block vectors offer COVs of 4.9%, 5.8%, 5.4% and 6% on the four studied microarchitecture structures respectively. We found that in general, tracking performance metrics performs better than tracking control flow in identifying reliability phase behavior of applications. To our knowledge, this paper is the first to characterize program reliability phase behavior at the microarchitecture level.

This paper analyzes the impact of dynamic task scheduling, processing element allocation and data transfer management on system performance of heterogeneous MPSoCs. Therefore, all parts of a runtime scheduling unit are analyzed. Bottlenecks are identified and their complexity evaluated. Furthermore, traced information is processed with two newly introduced tools. The first one generates an annotated SDF3 file. The second one creates a static schedule which applies the same scheduling and allocation decision as the dynamic scheduler. The execution of the static schedule reduces the burden of task management to a minimum. The resulting static execution is compared with the execution of the dynamic schedule. Hence, runtime overhead of dynamic scheduling is unveiled.

Energy minimization in dynamic train scheduling and control for metro rail operations

In this paper, we study a simple question: when are dynamic relaying strategies essential in optimizing the diversity-multiplexing tradeoff (DMT) in half-duplex wireless relay networks? This is motivated by apparently two contrasting results even for a simple three-node network with a single half-duplex relay. When all channels in the system are assumed to be independent and identically fading, a static schedule where the relay listens half the time and transmits half the time combined with quantize-map-and-forward (QMF) relaying is known to achieve the full-duplex performance. However, when there is no direct link between the source and the destination, a dynamic decode-and-forward (DDF) strategy is needed to achieve the optimal tradeoff. In this case, a static schedule is strictly suboptimal and the optimal tradeoff is significantly worse than the full-duplex performance. In this paper, we study the general case when the direct link is neither as strong as the other links nor fully nonexistent, and identify regimes where dynamic schedules are necessary and those where static schedules are enough. We identify four qualitatively different regimes for the single-relay channel, where the tradeoff between diversity and multiplexing is significantly different. We show that in all these regimes one of the above two strategies is sufficient to achieve the optimal tradeoff by developing a new upper bound on the best achievable tradeoff under channel state information available only at the receivers. A natural next question is whether these two strategies are sufficient to achieve the DMT of more general half-duplex wireless networks with a larger number of relays. We propose a generalization of the two existing schemes through a dynamic QMF (DQMF) strategy, where the relay listens for a fraction of time depending on received channel state information but not long enough to be able to decode. We show that such a DQMF strategy is needed to achieve the optimal DMT in a parallel channel with two relays, outperforming both DDF and static QMF strategies.

Network processors are programmable devices that can process packets at a high speed. A network processor is typified by multi-threading and heterogeneous multiprocessing, which usually requires programmers to manually create multiple tasks and map these tasks onto different processing elements. This paper addresses the problem of automating task creation and mapping of network applications onto the underlying hardware to maximize their throughput. We propose a throughput cost model to guide the task creation and mapping with the objective of both minimizing the number of stages in the processing pipeline and maximizing the average throughput of the slowest task simultaneously. The average throughput is modeled by taking communication cost, computation cost, memory access latency and synchronization cost into account. We envision that programmers write small functions for network applications, such that we use grouping and duplication to construct tasks from the functions. The optimal solution of creating tasks from m functions and mapping them to n processors is an NP-hard problem. Therefore, we present a practical and efficient heuristic algorithm with an O((n + m)m) complexity and show that the obtained solutions produce excellent performance for typical network applications. The entire framework has been implemented in the Open Research Compiler (ORC) adapted to compile network applications written in a domain-specific dataflow language. Experimental results show that the code produced by our compiler can achieve the 100% throughput on the OC-48 input line rate. OC-48 is a fiber optic connection that can handle a 2.488Gbps connection speeds, which is what our targeted hardware was designed for. We also demonstrate the importance of good creation and mapping choices on achieving high throughput. Furthermore, we show that reducing communication cost and efficient resource management are the most important factors for maximizing throughput on the Intel IXP network processors.KeywordsNetwork ProcessorsThroughputIntel IXPDataflow ProgrammingTask Creation and Mapping

Modern microprocessors achieve high application performance at the acceptable level of power dissipation. In terms of power to performance trade-off, the instruction window is particularly important. This is because enlarging the window size achieves high performance but naive scaling of the conventional instruction window can severely increase the complexity and power consumption. In this paper, we propose low-power instruction window techniques for contemporary microprocessors. First, the separated reorder buffer (SROB) reduces power dissipation by deferred allocation and early release. The deferred allocation delays the SROB allocation of instructions until their all data dependencies are resolved. Then, the instructions are executed in program order and they are released faster from the SROB. This results in higher resource utilization and low power consumption.

In this paper classic static and dynamic scheduling strategy is analyzed first, and then communication network of schedule ability judgment basis is given. An improved dynamic EDF scheduling algorithm is proposed in order to improve the scheduling task of real-time. The scheduling strategy is to change task priority according to the transmission error over deadline task when applying dynamic EDF scheduling strategy. True Time tool is used to build CAN network control system simulation platform. Dynamic EDF scheduling algorithm and improved scheduling algorithm are simulated respectively. The effectiveness of improved scheduling algorithm is verified by the simulation Keywords-Network control system; Scheduling Algorithm; True Time toolbox result.

Pipelining allows the execution of loop iterations with cross-iteration dependences to overlap in time, provided that the loop body is partitioned into stages such that the data dependences are not violated. Then, the stages are mapped onto threads and communication and synchronization between stages is typically achieved using queues. Pipelining techniques that rely on static scheduling perform poorly for load-imbalanced loops. Moreover, previous research efforts that achieve load-balancing are restricted to work-stealing and imply high overhead for fine-grained loops. In this article, we present URTS, a unified runtime system with compiler support that provides a lightweight dynamic scheduler by combining mapping, communication and synchronization algorithms with a suitable data structure and an efficient ticket mechanism. Particularly, URTS shows that it is possible to combine the efficiency of static scheduling with the load-imbalance tolerance of work-stealing by using a unified design that exploits the properties of a novel data structure. The evaluation on 8- and 32-core machines shows that URTS implies low overhead, of the same order as a static scheduler, for a set of benchmarks chosen from widely-used collections. URTS is a scalable solution that performs efficient dynamic scheduling for fine-grained loops, i.e., a class of interesting loops that is poorly handled by the state-of-the-art due to high overhead.

In the network applications domain, different network environments and scenarios demand various line rates, and restrain the design of the network processor by several constraints such as power and area. Additionally, new network services and applications with different processing requirements are increasingly emerging day by day. In this regard, having a multi-objective and flexible performance model that can be used to minimize the cost and time of designing network processors is an inevitable need. In this paper, we propose an accurate and fast prediction model that exploits just a few numbers of system-level parameters to estimate the performance and power of a commercial network processor, Intel IXP2800. The proposed design methodology uses a non-linear learning algorithm - a combination of the polynomial transformation of design parameters and higher-order spline functions - which in the face of newly introduced applications needs only a small training set, i.e. a small number of simulations, to train the model. Our experimental results show the proposed models can achieve a median error rate as low as 8.7 percent for performance and 2.6 percent for power metric.

Mapping packet processing tasks on network processor micro-engines involves complex tradeoffs that relating to maximizing parallelism and pipelining. Due to an increase in the size of the code store and complexity of the application requirements, network processors are being programmed with heterogeneous threads that may execute code belonging to different tasks on a given micro-engine. Also, most network applications are streaming applications that are typically processed in a pipelined fashion. Thus, the tasks on different micro-engines are pipelined in such a way as to maximize the throughput. Tasks themselves could have different run time performance demands. Traditionally, runtime management involving processor sharing, real-time scheduling etc. is provided by the runtime environment (typically an operating system) using the hardware support for timers and interrupts that allows time slicing the resource amongst the tasks. However, due to stringent performance requirements on network processors (which process packets from very high speed network traffic), neither OS nor hardware mechanisms are typically feasible/available.In this paper, we show that it is very difficult and inefficient for the programmer to meet the constraints of runtime management by coding them statically. Due to the infeasibility of hardware or OS solution (even in the near future), the only choice left is a compiler approach.We propose a complete compiler solution to automatically insert explicit context switch (ctx) instructions provided on the processors so that the execution of programs is better manipulated at runtime to meet their constraints. We show that such an approach is feasible opening new application domains that would need heterogeneous thread programming. Such approaches would in general become important for multi-core processors.

In this paper, the optimal dynamic scheduling of electric vehicles (EVs) in a parking lot (PL) is proposed to minimize the charging cost. In static scheduling, the PL operator can make the optimal scheduling if the demand, arrival, and departure time of EVs are known well in advance. If not, a static charging scheme is not feasible. Therefore, dynamic charging is preferred. A dynamic scheduling scheme means the EVs may come and go at any time, i.e., EVs’ arrival is dynamic in nature. The EVs may come to the PL with prior appointments or not. Therefore, a PL operator requires a mechanism to charge the EVs that arrive with or without reservation, and the demand for EVs is unknown to the PL operator. In general, the PL uses the first-in-first serve (FIFS) method for charging the EVs. The well-known optimization techniques such as particle swarm optimization and shuffled frog leaping algorithms are used for the EVs’ dynamic scheduling scheme to minimize the grid’s charging cost. Moreover, a microgrid is also considered to reduce the charging cost further. The results obtained show the effectiveness of the proposed solution methods.

To meet the demand for higher performance, flexibility, and economy in today's state-of-the-art networks, great emphasis is placed on unconventional hardware architectures of network processors. This paper analyzes the problem of processor internal resource and traffic management and proposes a programmable scheduler architecture implemented in a novel protocol processor that deals with the above problems in an integrated way. We briefly outline the architecture of the protocol processor and we support that the innovative scheduling scheme integrated in PRO3 is, in general, crucial for network Systems-on-Chip since it makes it feasible to use scheduler's architecture are discussed that lead to efficient integration of the component to different network processor architectures at a similar cost. Its beneficial features are easy hardware implementation, low memory bandwidth requirements and high flexibility so as to support multiple service disciplines in a programmable way, thousands of flows and even perform different scheduling tasks.

Explicit congestion control schemes use router feedback to overcome limitations of the standard mechanisms of the Transmission Control Protocol (TCP). These approaches require additional packet processing in every router and therefore raise the question whether, and how, this can be achieved in high-speed routers. This paper investigates the realization complexity of these router functions of two such schemes, the TCP Quick-Start extension and the Explicit Control Protocol (XCP). Our focus lies on the implementation using a network processor. We show that synchronization issues among parallel processing entities have to be considered, and that this affects the router performance. We develop and compare different synchronization mechanisms for highly parallel packet processing. Our prototype implementation on an Intel IXP network processor allows to quantify the impact on throughput and delay caused by the additional packet processing in the fast path. The measurements reveal that Quick-Start and XCP processing is feasible at multiple Gbit/s line speed, with Quick-Start being simpler to scale. We expect similar results for the implementation of the Rate Control Protocol (RCP), which is another router-assisted congestion control scheme, requiring no elaborate synchronization. Finally, we study the implementation using programmable logic and show the applicability of XCP and in particular Quick-Start even at significantly higher line speeds.

This special issue is based on a collection of selected papers presented at the Fifth International Conference on Advanced Computing held in Chennai (Madras), India in December 97. The International Conference on Advanced Computing is organized annually in India by the Advanced Computing Society (ACS) which is a premier professional society set up in India to cater to the broad interests in the area of Advanced Computing. One of the significant activities of the Society is to organize regular Meetings/Conferences/Symposia. The Conferences are held annually in India during December. Out of the shortlisted papers presented at the Conference held in Chennai (Madras) during December 97, the following six papers were finally selected after a second round of detailed review of the papers. The first paper On designing and implementing collaborative system using Java-RMI by Rajeev R. Raje, Snehasis Mukhopadhyay, Michael Boyles and Nila Patel describe the use of Java-RMI in designing a collaborative information classifier. The principles of RMI, the details of the prototype, and some preliminary results are presented. The paper primarily concentrates on web-based computing paradigms. In the second paper A framework for performance-based program partitioning , Ram Subramanian and Santosh Pande present an efficient and accurate performance model based program-partitioning approach for parallel architectures. The interactions between computation and communication are captured through behavioral edges . The approach yields significant performance improvement. The third paper DDSCHED: a distributed dynamic real-time scheduling algorithm by Anup K. Bhattacharjee, K. Ravindranath, R. Mall and A. Pal presents a dynamic soft real-time scheduling algorithm for distributed systems. The algorithm is based on a local scheduler and a distributed scheduling scheme. The algorithm takes care of the network delays assuming that the communication protocol is CSMA/CD. In the fourth paper Generic operational decomposition for concurrent systems semantics and reflection , Annie Marcoux, Christine Maurel, Frederic Migeon and Patrick Salle discuss about the reflection in concurrent languages, particularly in actor-based languages. The main objective of the paper is to extend concurrent systems to reflection. The authors present a modular and dynamic description of entity operational management, and extend the decomposition to obtain reflective entities. The fifth paper Parallel programming using visual patterns by A. S. M. Sajeev proposes a two level approach to parallel programming within the context of a visual environment. The first level is the specification of patterns encapsulating process communation and synchronization, and the second level is the use of patterns for parallel programming. The approach encourages reuse of patterns. In the sixth paper An application framework for dynamic distributed software architectures , G. R. Ribeiro-Justo and P. R. F. Cunha present an object-oriented application framework for developing evolving (reconfigurable) software architectures for distributed systems. The application framework is called C++CL. Such a requirement is encountered in banking, industrial control and telecommunications applications. We are extremely thankful to the following reviewers who have helped us in reviewing the papers submitted for this special issue: Lawrence Jenkins N. Mohan Ram Nishit Narang Rajeev Shorey Sameer Adhikari K. Balaji K. Rajan Sumit Kasera Subhrajyothi Bhar Pankaj Sethi Ravindranath Kokku Guest Editors: L. M. Patnaik, Ravi Mittal and K. M. Mehta

GPU based parallel genetic algorithm for solving an energy efficient dynamic flexible flow shop scheduling problem