Charge storage impact on input capacitance in p-GaN gate AlGaN/GaN power high-electron-mobility transistors

GaN power transistors are attracting increasing attention for next-generation power switching applications. However, GaN power transistors should not be regarded as a direct replacement for silicon power metal–oxide–semiconductor field-effect transistors, since the unique properties of GaN power transistors require special treatment. In this work we review a unique and critical property of GaN power transistors, the dynamic threshold voltage (V th). GaN power transistors feature a p-GaN gate structure, while the gate metal contacts the p-GaN layer through a Schottky junction. This unique p-GaN gate structure is distinctively different from the silicon metal–oxide–semiconductor gate structure in that the p-GaN layer is actually a floating region without direct electrical contact to the external electrodes of the device. The floating p-GaN layer enables a charge storage process during the switching operation of a p-GaN gate high-electron-mobility transistor. Through carefully designed experiments, the strong correlation between charge storage and the dynamic V th shift has been revealed; this also serves as an approach to accurately predict the dynamic V th during switching operation. The influence of the dynamic V th on power switching applications is discussed. For example, with a positive dynamic V th shift, the reverse conduction voltage of a GaN power transistor is significantly increased, adding to the power loss. This positive V th shift also demands a sufficiently high gate drive voltage to ensure that the GaN power transistor can be fully turned on, which reduces the safety margin for the gate reliability of the device. To design a GaN based power switching circuit, accurate simulation of the device/circuit characteristics is necessary. Circuit simulations that do not consider the dynamic V th lead to a large deviation from the measurement circuit characteristics. We demonstrate that by incorporating the dynamic V th into the circuit model this deviation can be effectively eliminated.

We report a selective area growth (SAG) method to define the p-GaN gate of AlGaN/GaN high electron mobility transistors (HEMTs) by metal-organic chemical vapor deposition. Compared with Schottky gate HEMTs, the SAG p-GaN gate HEMTs show more positive threshold voltage (Vth) and better gate control ability. The influence of Cp2Mg flux of SAG p-GaN gate on the AlGaN/GaN HEMTs has also been studied. With the increasing Cp2Mg from 0.16 μmol/min to 0.20 μmol/min, the Vth raises from −0.67 V to −0.37 V. The maximum transconductance of the SAG HEMT at a drain voltage of 10 V is 113.9 mS/mm while that value of the Schottky HEMT is 51.6 mS/mm. The SAG method paves a promising way for achieving p-GaN gate normally-off AlGaN/GaN HEMTs without dry etching damage.

Highly uniform AlGaN/GaN high electron mobility transistors (HEMTs) were fabricated on a low-cost 3-inch conductive n-SiC substrate for the first time. Average values of threshold voltage (Vth) and transconductance (gm) of AlGaN/GaN HEMT were -1.55V and 194 mS/mm. Standard variations of those values were only 0.15V and 3.9mS/mm across an entire 3-inch conductive substrate. The 1-mm-gate-periphery GaN HEMT chip, which was operated at 60V, achieved high CW output power density of 7.0W/mm, with a high linear gain of 22.2dB and power added efficiency (PAE) of 70% at 2.14GHz. Standard variations of power density, linear gain and PAE at 50V were only 0.42W/mm, 0.2dB and 3.0 point, respectively. This low-cost highly uniform high-gain chip technology is sufficient for mass production of wireless base station application using GaN-HEMTs.

This study explores gate reliability in p-GaN high electron mobility transistors (HEMTs) using different gate stack engineering (GSE) techniques. It analyses normally-off HEMTs with p-GaN gates, fabricated with varying Mg doping concentrations and an additional stack between the Schottky gate metal and p-GaN region. The analysis is based on device characteristics like threshold voltage (V TH), On-state resistance (RDS-ON), and gate breakdown (G<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BD</inf>). Also, a novel approach, the successive multi-stage compliance ramp voltage sweep (MSC-RVS) methodology, is employed to investigate forward gate breakdown mechanisms. MSC-RVS allows the observation of various gate BD mechanisms associated with GaN in a single short-duration stress test. This involves gradually increasing gate current compliance (ICOMP) and repeatedly initiating multiple BD events through a ramped voltage sweep along the Schottky, Passivation, and PiN regions. These comprehensive studies on p-GaN gate performance, utilizing diverse GSE approaches, offer deeper insights into achieving high gate reliability for p-GaN gate HEMTs.

This study proposes a new gate architecture that integrates both a p-GaN gate and a metal–insulator–semiconductor (MIS) structure for a normally-off AlGaN/GaN high electron mobility transistor. Silvaco TCAD simulation software is used to assess the performance of the proposed design. A comprehensive analysis of the device’s transfer, output, and breakdown characteristics is carried out and compared with the conventional p-GaN gate AlGaN/GaN HEMT. The findings indicate that incorporating MIS in conjunction with the p-GaN gate leads to an augmentation in the on-state current density and a reduction in on-resistance. The proposed HEMT exhibits superior attributes, with an 80% increase in drain current compared to the conventional p-GaN gate HEMT, but remains similar to threshold voltage and breakdown voltage. Consequently, the proposed HEMT demonstrates elevated current density and enhances gate control over the channel without modifying the threshold voltage compared to the conventional p-GaN gate HEMT.

In this paper, study on the heat transfer of GaN-based high electron mobility transistors (HEMTs) on SiC substrate was carried out utilizing transient thermal analysis method. Gate-source voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{{\text {gs}}}$ </tex-math></inline-formula> ) is used as the temperature sensitive parameter. Linear relationship ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${K}$ </tex-math></inline-formula> factor) between <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{{\text {gs}}}$ </tex-math></inline-formula> and temperature is obtained. It is found that the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${K}$ </tex-math></inline-formula> factor is proportional with drain-source current and does not change with the variation of drain-gate voltage in the linear region of HEMT. We proposed and proved that the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${K}$ </tex-math></inline-formula> factor should be calibrated with HEMT working at linear region to insure the accuracy of subsequent thermal evaluation. Moreover, the temperature rise and thermal resistance keeps as constant when <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${K}$ </tex-math></inline-formula> factors were calibrated within the linear region. Transient thermal measurement turns out to be a non-destructive, fast, and precise method for the thermal performance analysis and quality control of the power HEMTs.

In this paper, several methods suitable for real time on-chip temperature measurements of power AlGaN/GaN based high-electron mobility transistor (HEMT) grown on SiC substrate are presented. The measurement of temperature distribution on HEMT surface using Raman spectroscopy is presented. We have deployed a temperature measurement approach utilizing electrical I-V characteristics of the neighboring Schottky diode under different dissipated power of the transistor heat source. These methods are verified by measurements with micro thermistors. The results show that these methods have a potential for HEMT analysis in thermal management. The features and limitations of the proposed methods are discussed. The thermal parameters of materials used in the device are extracted from temperature distribution in the structure with the support of 3-D device thermal simulation. The thermal analysis of the multifinger power HEMT is performed. The effects of the structure design and fabrication processes from semiconductor layers, metallization, and packaging up to cooling solutions are investigated. The analysis of thermal behavior can help during design and optimization of power HEMT.

Simulations are carried out to explore the possibility of achieving high breakdown voltage of GaN HEMT (high-electron mobility transistor). GaN cap layers with gradual increase in the doping concentration from 2 × 1016 to 5 × 1019 cm−3 of N-type and P-type cap are investigated, respectively. Simulation results show that HEMT with P-doped GaN cap layer shows more potential to achieve higher breakdown voltage than N-doped GaN cap layer under the same doping concentration. This is because the ionized net negative space charges in P-GaN cap layer could modulate the surface electric field which makes more contribution to RESURF effect. Furthermore, a novel GaN/AlGaN/GaN HEMT with P-doped GaN buried layer in GaN buffer between gate and drain electrode is proposed. It shows enhanced performance. The breakdown voltage of the proposed structure is 640 V which is increased by 12% in comparison to UID (un-intentionally doped) GaN/AlGaN/GaN HEMT. We calculated and analyzed the distribution of electrons' density. It is found that the depleted region is wider and electric field maximum value is induced at the left edge of buried layer. So the novel structure with P-doped GaN buried layer embedded in GaN buffer has the better improving characteristics of the power devices.

Recently, p-GaN gate high electron mobility transistors (HEMTs) have emerged as competitive participants for next-generation high-performance power supply applications. However, the threshold voltage ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) instability caused by short-circuit events jeopardizes the overall reliability of p-GaN gate HEMT and the power system in real applications. Hence, a noninvasive condition-based monitoring technique for critical device parameters is urgently required to enhance system safety without affecting the features of power electronic systems. In this paper, the threshold voltage instability dynamics of p-GaN gate HEMT under repetitive short stress were investigated to achieve high estimation accuracy and good monitoring efficiency. A double-phase adaptive neural network to predict the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> degradation kinetics based on the historical degradation recordings of the target device is developed. The degradation process contains a monotonous increasing process and an oscillation process divided by random changing point subject to Weibull distribution. Based on such characteristics, the extreme learning machines were combined with classic activation functions and periodic activation functions to predict the threshold voltage tendencies of p-GaN HEMTs under repetitive SC stress. The experiment results validate that the developed model based on static investigations can provide degradation predictions with high accuracies. Besides, the proposed method endows substantial benefits for the conditional-based monitoring problem of other newly emerging semiconductor devices that feature multiple scenarios during the dynamic process and differences between individual units.

Synchronous buck converter comprises a low side (LS) and a high side (HS) switch, where the HS switch works in the first quadrant (forward conduction)whereas the LS switch works in the third quadrant (reverse conduction). However, the reliability of the p-GaN gate high electron mobility transistor (HEMT) in reverse conduction is unclear. In this work, a comprehensive evaluation of this conduction mode for 200-V HEMTs was conducted. First, devices were subjected to time-dependent breakdown (TDB) measurements. By comparing different device configurations, the time to failure (TTF) was found to only scale with the number of gate fingers instead of the gate width W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> , proving the critical spots are the intersection of gate fingers over the N implantation isolation. The reverse operation voltage of V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> for ten years lifetime was extrapolated to be -5.4 V, corresponding to a failure of 0.01% and 100 gate fingers. Second, the devices were submitted to 200-V VDS OFF-state stress for 10 s, after which the reverse drain current saw a negligible degradation. Third, the reverse conduction of the HEMTs only showed a very limited deterioration after a long-time bias temperature instability (BTI) stress at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> = -5.5 V and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> = 0 V. This work proves the p-GaN gate HEMTs bear a high reliability in reverse conduction, which can simplify the design of synchronous power system.

In this letter, we present an extensive analysis on the role of both switching frequency (ranging from 100 kHz to 1 MHz) and duty cycle (from 10% to 90%) on the time-dependent gate breakdown of high electron mobility transistors (HEMTs) with Schottky metal to p-GaN gate. More specifically, results show how the gate lifetime of GaN HEMTs increases by reducing the frequency and the duty cycle of the stressing gate signal (VG). Such behavior is ascribed to the OFF-time, which is responsible to alter the electrostatic potential in the p-GaN layer during the rising phases of VG (from OFF- to ON-state). Findings of this analysis are useful both for further technology improvement and for GaN-based power circuit designers.

Undoped AlGaN-GaN power high electron mobility transistors (HEMTs) on sapphire substrate with 470-V breakdown voltage were fabricated and demonstrated as a main switching device for a high-voltage dc-dc converter. The fabricated power HEMT realized a high breakdown voltage with a field plate structure and a low on-state resistance of 3.9 m/spl Omega//spl middot/cm/sup 2/, which is 10 /spl times/ lower than that of conventional Si MOSFETs. The dc-dc converter operation of a down chopper circuit was demonstrated using the fabricated device at the input voltage of 300 V. These results show the promising possibilities of the AlGaN-GaN power HEMTs on sapphire substrate for future switching power devices.

We have demonstrated an Al-free Ti/Mo/Ta/Au-based n-type ohmic contact for high power AlGaN/GaN high electron mobility transistors (HEMTs). Our fabricated ohmic contact has an extremely smooth surface morphology and almost the same specific contact resistance (ρc) of 9.1 × 10–6 Ωcm2 as conventional Ti/Al-based contacts. We have found that Mo, which is generally inserted as a barrier layer, has the effect of reducing contact resistance. Moreover, we have applied this ohmic technique to fabricate an AlGaN/GaN HEMT and obtained sufficient transconductance (gm) of 210 mS/mm. (© 2005 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

A microwave power high electron mobility transistor (HEMT) has been developed and tested in the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">K</tex> -band frequency range. The HEMT has a unique configuration of a selectively low-doped (AlGa)As/GaAs/(AlGa)As double heterojunction resulting in both capability of high-current density and high gate breakdown voltage. The structure showed electron mobility of 6800 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V.s and two-dimensional (2-D) electron density as high as 1.2 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> at room temperature. An output power of 660 mW (550 mW/mm) with 3.2-dB gain and 19.3-percent power added efficiency was achieved at 20 GHz with 1-µm gate length and 1.2-mm gate periphery. A similar device with 2.4-mm gate width produced an output power of 1 W with 3-dB gain and 15.5-percent efficiency. These results offer microwave high power capability in a double-heterojunction HEMT (DH-HEMT).

Numerous studies have highlighted the significant potential of III-N High Electron Mobility Transistors (HEMTs) for power applications. Despite the commercialization of III-N HEMTs fabricated on silicon-based heterostructures, they have captured only a small share of the power electronics market. A major challenge is the introduction of electrically active defects, such as traps, during device fabrication and operation. These defects, which are unevenly distributed in the device heterostructure, contribute to device aging and severely impact reliability and operational lifespan. This work investigates the temperature dependence of key device characteristics in commercial III-N HEMTs. Using the generalized Unified Charge Control Model (UCCM), we extract temperature-dependent parameters, including electron mobility, output conduction, and maximum driving current, from in situ measured device characteristics. By distinguishing between two temperature-related effects, ambient operating temperature vs. self-heating, we found that at high drain-to-source and gate-to-source voltages, self-heating becomes the dominant factor. To account for this, we incorporate the self-heating phenomenon into the UCCM model and introduce a figure of merit for comparing the impact of self-heating across devices from different manufacturers. Additionally, we analyze the maximum driving current in relation to the material properties of III-N heterojunctions. The temperature profiles inside the HEMT devices (e.g., distribution of temperature along the channel) will be evaluated experimentally and by TCAD simulations combined with heat transfer finite element simulations. Future applications of our model aim to link self-heating with long-term reliability and lifetime, two critical factors that currently limit the broader adoption of III-N HEMTs in power electronics.