Reliability of p-GaN Gate HEMTs in Reverse Conduction

We report a selective area growth (SAG) method to define the p-GaN gate of AlGaN/GaN high electron mobility transistors (HEMTs) by metal-organic chemical vapor deposition. Compared with Schottky gate HEMTs, the SAG p-GaN gate HEMTs show more positive threshold voltage (Vth) and better gate control ability. The influence of Cp2Mg flux of SAG p-GaN gate on the AlGaN/GaN HEMTs has also been studied. With the increasing Cp2Mg from 0.16 μmol/min to 0.20 μmol/min, the Vth raises from −0.67 V to −0.37 V. The maximum transconductance of the SAG HEMT at a drain voltage of 10 V is 113.9 mS/mm while that value of the Schottky HEMT is 51.6 mS/mm. The SAG method paves a promising way for achieving p-GaN gate normally-off AlGaN/GaN HEMTs without dry etching damage.

Recently, p-GaN gate high electron mobility transistors (HEMTs) have emerged as competitive participants for next-generation high-performance power supply applications. However, the threshold voltage ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) instability caused by short-circuit events jeopardizes the overall reliability of p-GaN gate HEMT and the power system in real applications. Hence, a noninvasive condition-based monitoring technique for critical device parameters is urgently required to enhance system safety without affecting the features of power electronic systems. In this paper, the threshold voltage instability dynamics of p-GaN gate HEMT under repetitive short stress were investigated to achieve high estimation accuracy and good monitoring efficiency. A double-phase adaptive neural network to predict the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> degradation kinetics based on the historical degradation recordings of the target device is developed. The degradation process contains a monotonous increasing process and an oscillation process divided by random changing point subject to Weibull distribution. Based on such characteristics, the extreme learning machines were combined with classic activation functions and periodic activation functions to predict the threshold voltage tendencies of p-GaN HEMTs under repetitive SC stress. The experiment results validate that the developed model based on static investigations can provide degradation predictions with high accuracies. Besides, the proposed method endows substantial benefits for the conditional-based monitoring problem of other newly emerging semiconductor devices that feature multiple scenarios during the dynamic process and differences between individual units.

In this paper, we present our recent research on the demonstration of normally-OFF operation and high-performance device merits in GaN high electron mobility transistors (HEMTs), which are enabled by the employment of thin-barrier AlGaN/GaN heterostructures. Two types of thin-barrier HEMTs are investigated: one is with a metal–oxide–semiconductor (MOS) gate structure, and the other is with a p-GaN gate stack. The MOSHEMTs feature an as-grown thin-barrier heterostructure with a gate-recess-free fabrication process and a high-k ZrO2 gate dielectric. Approaches including selective area barrier regrowth and selective area surface passivation are implemented to minimize the access resistance in the MOSHEMTs. For the p-GaN gate HEMTs, a T-shaped Schottky gate contact scheme is employed to realize superior gate stack reliability. Normally-OFF operation with a large threshold voltage ⩾1.5 V, a high maximum drain current ⩾450 mA mm−1, a steep subthreshold slope ⩽95 mV dec−1, and negligible hysteresis are achieved in all the demonstrated device structures. Moreover, in analyzing the reported device results with the corresponding heterostructure design, we discuss the benefits and tradeoffs of thin-barrier MOSHEMTs and p-GaN gate HEMTs, respectively.

We have evaluated specific on-state resistance (Ron,sp) and switching performance of various GaN power field-effect transistors (FETs) with 600 and 1200 V ratings using analytical calculation and numerical simulation. The normally-off GaN power FET family includes lateral p-GaN gate high electron mobility transistors (HEMTs), lateral metal-oxide-semiconductor (MOS) channel HEMTs, current aperture vertical electron transistors (CAVETs) and vertical U-shaped trench-gate MOS field-effect transistors (UMOSFETs). This study shows the advantages of vertical GaN power FETs over lateral GaN power HEMTs. These advantages include lower Ron,sp and smaller switching energy loss, especially at higher blocking voltages (1200 V). At 600 V, lateral P-GaN gate HEMTs are competitive with vertical power FETs. Vertical GaN CAVETs perform better than both lateral HEMTs and vertical UMOSFETs at both voltage ratings, benefiting from its lowest Ron*QG figure-of-merit.

The GaN-based high-electron mobility transistors (HEMTs) can operate efficiently in reverse conduction mode without requiring an intrinsic antiparallel diode, reducing power losses and enabling higher switching frequencies. This study investigates degradation mechanisms in Schottky p-GaN gate HEMTs (SP-HEMTs) under reverse conduction mode on devices featuring different gate geometries. It assesses threshold voltage shift (Δ<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>TH</roman></sub>), ON-resistance drift (Δ<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>ON</roman></sub>), and device lifetime across a range of temperatures (10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">∘</sup>C–175 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">∘</sup>C) and negative drain-to-source voltages (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>DS</roman></sub>). Results reveal two distinct degradation mechanisms: the first occurring in the AlGaN barrier at the source-side gate edge, and a second, a long-term process at the metal/p-GaN Schottky junction, which leads to irreversible breakdown. Activation energy for both mechanisms has been determined using current deep-level transient spectroscopy (I-DLTS), providing insights into the temperature and voltage dependencies of mechanisms affecting SP-HEMTs reliability.

This study explores gate reliability in p-GaN high electron mobility transistors (HEMTs) using different gate stack engineering (GSE) techniques. It analyses normally-off HEMTs with p-GaN gates, fabricated with varying Mg doping concentrations and an additional stack between the Schottky gate metal and p-GaN region. The analysis is based on device characteristics like threshold voltage (V TH), On-state resistance (RDS-ON), and gate breakdown (G<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BD</inf>). Also, a novel approach, the successive multi-stage compliance ramp voltage sweep (MSC-RVS) methodology, is employed to investigate forward gate breakdown mechanisms. MSC-RVS allows the observation of various gate BD mechanisms associated with GaN in a single short-duration stress test. This involves gradually increasing gate current compliance (ICOMP) and repeatedly initiating multiple BD events through a ramped voltage sweep along the Schottky, Passivation, and PiN regions. These comprehensive studies on p-GaN gate performance, utilizing diverse GSE approaches, offer deeper insights into achieving high gate reliability for p-GaN gate HEMTs.

991013426071003412 HKUST Electronic Theses Device engineering for stable and reliable gate operation in Schottky-type p-GaN gate HEMTs by Junting Chen thesis 2025 1 online resource (xiv, 132 pages) : color illustrations Schottky-type p-GaN gate high electron mobility transistors (HEMTs) are…Read more ›

In this paper, input capacitance (CISS) of p-GaN gate AlGaN/GaN power high-electron-mobility transistors (HEMTs) is systemically investigated. CISS includes gate-to-source capacitance (CGS) and gate-to-drain capacitance (CGD). In comparison with the normally-on HEMTs, it is found that the phenomenon of CISS variation is different in the commercial p-GaN gate HEMTs. The unique charge storage effect in the typical p-GaN layer is adopted and discussed to explain the variation of CISS and establish the underlying mechanism. Owing to the depletion of holes, net negative charges are induced in the p-GaN layer under an off-state drain bias. It is demonstrated that the negative charge storage makes significant contribution to the increase of CGS before the two-dimensional-electron-gas channel under source-field-plate (SFP) pinches off. Due to the clamped electric field distributions at drain-side edge of the p-GaN layer, the charge storage stops changing CGS after the SFP pinche-off. Additionally, the storage has a minor influence on the variation of CGD. Verified by the experimentally calibrated TCAD simulation, this work reveals a novel mechanism of charge storage impact on CISS variation in p-GaN gate AlGaN/GaN power HEMTs, which is of benefit to the CISS related capacitance design and gate driver optimization of the devices.

Titanium disilicide/copper (TiSi2/Cu) gate AlGaN/GaN high electron mobility transistors (HEMTs) with low gate leakage current are demonstrated. The TiSi2/Cu gate devices demonstrate electrical characteristics that are comparable to those of conventional Ni/Au gate devices. At gate voltage of −20 V, typical gate leakage current for a TiSi2/Cu gate device with a gate length of 5 μm and width of 200 μm is found to be as low as 5.15 × 10−7 mA mm−1, which is three orders lower than that of the Ni/Au gate device. The lower gate leakage current is primarily caused by the higher Schottky barrier height of TiSi2/Cu on AlGaN/GaN HEMTs than that of Ni/Au by 0.36 eV. The threshold voltages of the TiSi2/Cu gate HEMTs were maintained to be equivalent to that of the Ni/Au gate device. No Cu diffusion was found at the metal and AlGaN interface by secondary ion mass spectrometry and scanning transmission electron microscopy. These results indicate that TiSi2 is a good barrier layer of Cu diffusion, and titanium disilicide/copper is a promising candidate for high-performance AlGaN/GaN HEMTs.

In this paper we report the first monolithic integration of InGaAs/InAlAs resonant tunneling diode (RTD) and high electron mobility transistor (HEMT) epitaxially grown on an InP substrate. The transconductance for a 1- mu m gate HEMT was 400 mS/mm and the peak-to-valley current ratio of the RTD was 3.1. Using this integrated structure, we demonstrate a static RAM cell circuit, consisting of a single transistor with two RTDs on the transistor. The memory cell circuit exhibits bistability, based on the RTD's negative differential resistance (NDR), at supply voltages from 0.6 to 1.1 V.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Unveiling the abnormal response behavior of AlGaN-based high electron mobility transistors (HEMTs) under ultraviolet light illumination

This work investigates the resistance distribution of the E-mode GaN-on-Si active-passivation (AP) p-GaN gate high-electron-mobility transistor (HEMT) using the transfer length method (TLM). The AP-HEMT has a unique active-passivation layer that is electrically connected to the p-GaN gate and covers most area of the device. The active-passivation layer changes the way the 2DEG is generated in the device, so the constitution of the device R ON is expected to differ from the conventional p-GaN gate HEMT (Conv-HEMT). According to our study, the sheet resistance of the 2DEG under the active-passivation layer is lower than that of the access region, leading to the reduced R ON in AP-HEMT compared to Conv-HEMT. The temperature dependence of the resistance is also investigated. Additionally, AP-HEMT exhibits an improved reverse conduction performance across the temperature range of 25 °C to 150 °C, due to the reduced gate-to-drain resistance in the device.

In this work, a novel GaN vertical junction field-effect transistor (JFET) with intrinsic reverse conduction capability (RC-JFET) is proposed and studied by simulation. The RC-JFET features two separate source electrodes, one of which performs as an embedded freewheeling diode that can enable the reverse conduction function of the device. Benefiting from a structure with two separate source electrodes, the forward and reverse current conduction paths are also separated, which allows us to independently design the forward and reverse conduction characteristics of the RC-JFET. The forward threshold voltage V TH is 1.6 V while the reverse turn-on voltage V on,rev is as low as 0.7 V. In addition, the buried floating p-base can effectively modulate the E-field in the GaN drift region, which can achieve a high breakdown voltage of 1720 V with an R on,sp of 2.79 mΩ cm2. Due to the embedded freewheeling diode, the device exhibits a short reverse recovery time T rr of 13 ns. By featuring an intrinsic reverse conduction capability, the proposed RC-JFET is capable of eliminating the externally connected diode, which is beneficial for improved switching speed and switching power loss due to the reduction of parasitic effects and chip size of power circuits.

In this work, substrate-coupled cross-talk effects are systematically investigated on p-GaN gate high electron-mobility transistors (HEMTs) fabricated on GaN-on-Sapphire and GaN-on-Si platforms. The vertical leakage and substrate-coupled voltage are significantly suppressed in GaN-on-Sapphire devices at high-voltage (HV) bias and high temperatures. At HV bias of 600 V, the current degradation (CD) of GaN-on-Si devices reaches 20.6 % at <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$75{ }^{\circ} \mathrm{C}$</tex> and 6.3 % at <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$150{ }^{\circ} \mathrm{C}$</tex> due to the cross-talk effects, while that of GaN-on-Sapphire devices stays below 1 %. The energy band diagrams are drawn to illustrate the mechanisms of the cross-talk effects with different substrates. The impacts of cross-talk effects on dynamic performance were further evaluated on side-by-side power HEMTs using a hybrid chip-to-board circuit. In the GaN-on-Si platform, the CD is more pronounced at high temperatures. In contrast, for GaN-on-Sapphire platform, the CD remains below 1 % under kHz high-voltage switching conditions up to <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$150{ }^{\circ} \mathrm{C}$</tex>. The GaN-on-Sapphire platform is an effective approach for eliminating the cross-talk effects, which provides a promising choice for high-voltage GaN monolithically power integration applications.

The low ionization rate of Mg acceptors in the p-gallium nitride (GaN) layer is a critical factor accounting for the low current density of E-mode GaN p-FETs. In this work, polarization-enhanced technology was adopted to enhance the ionization rate of the p-GaN channel. High-performance recessed-gate E-mode GaN p-FETs were fabricated to enable GaN complementary logic (CL) circuits. During fabrication, the channel thickness (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>x</i></sub>) is found to be a critical parameter that influences the device metrics. With a decrease in <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>x</i></sub> (i.e., larger recess depth), a more negative threshold voltage (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>th</roman></sub>) is achieved; however, the trade-off is an increase in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\textit{R}_{\biosc{on}}$</tex-math></inline-formula>. The E-mode GaN p-FET with <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>x</i></sub> = 32 nm exhibits a <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>th</roman></sub> of -1.1 V, a high current density of 17.7 mA/mm, a high <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\textit{I}_{\biosc{on}}$</tex-math></inline-formula>/<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\textit{I}_{\biosc{off}}$</tex-math></inline-formula> of 6.9 × 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>7</roman></sup>, and a low subthreshold swing (SS) of 93 mV/dec. Furthermore, an E-mode n-channel p-GaN gate high electron mobility transistor (HEMT) was fabricated on the same epi-wafer, exhibiting a <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>th</roman></sub> of 1.3 V and an <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\textit{R}_{\biosc{on}}$</tex-math></inline-formula> of 6 <roman xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Ω⋅</roman>mm. Finally, a GaN CL inverter was fabricated and demonstrated under <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>DD</roman></sub> = 6 V. Rail-to-rail voltage swing and low static power consumption were both achieved. This work further validates the feasibility of GaN CL integrated circuits and power integrated circuits (PICs).