Design and Development of Polarization-Enhanced E-Mode GaN p-FET and Complementary Logic (CL) Circuits

Reports a novel low-voltage silicon-on-insulator (SOI) CMOS complementary pass-transistor logic (CPL) circuit using asymmetrical dynamic threshold pass-transistor (ADTPT) technique., Using the ADTPT technique to dynamically control the body bias of the pass-transistor via only one auxiliary transistor, the new SOI CMOS complementary pass-transistor logic (CPL) circuit provides superior speed performance at a low supply voltage as compared to the conventional pass-transistor logic circuits without the ADTPT technique as verified by the MEDICI simulation results. The ADTPT technique is especially effective for use in CPL circuits with serially-connected multiple inputs.

We report a selective area growth (SAG) method to define the p-GaN gate of AlGaN/GaN high electron mobility transistors (HEMTs) by metal-organic chemical vapor deposition. Compared with Schottky gate HEMTs, the SAG p-GaN gate HEMTs show more positive threshold voltage (Vth) and better gate control ability. The influence of Cp2Mg flux of SAG p-GaN gate on the AlGaN/GaN HEMTs has also been studied. With the increasing Cp2Mg from 0.16 μmol/min to 0.20 μmol/min, the Vth raises from −0.67 V to −0.37 V. The maximum transconductance of the SAG HEMT at a drain voltage of 10 V is 113.9 mS/mm while that value of the Schottky HEMT is 51.6 mS/mm. The SAG method paves a promising way for achieving p-GaN gate normally-off AlGaN/GaN HEMTs without dry etching damage.

We have evaluated specific on-state resistance (Ron,sp) and switching performance of various GaN power field-effect transistors (FETs) with 600 and 1200 V ratings using analytical calculation and numerical simulation. The normally-off GaN power FET family includes lateral p-GaN gate high electron mobility transistors (HEMTs), lateral metal-oxide-semiconductor (MOS) channel HEMTs, current aperture vertical electron transistors (CAVETs) and vertical U-shaped trench-gate MOS field-effect transistors (UMOSFETs). This study shows the advantages of vertical GaN power FETs over lateral GaN power HEMTs. These advantages include lower Ron,sp and smaller switching energy loss, especially at higher blocking voltages (1200 V). At 600 V, lateral P-GaN gate HEMTs are competitive with vertical power FETs. Vertical GaN CAVETs perform better than both lateral HEMTs and vertical UMOSFETs at both voltage ratings, benefiting from its lowest Ron*QG figure-of-merit.

Titanium disilicide/copper (TiSi2/Cu) gate AlGaN/GaN high electron mobility transistors (HEMTs) with low gate leakage current are demonstrated. The TiSi2/Cu gate devices demonstrate electrical characteristics that are comparable to those of conventional Ni/Au gate devices. At gate voltage of −20 V, typical gate leakage current for a TiSi2/Cu gate device with a gate length of 5 μm and width of 200 μm is found to be as low as 5.15 × 10−7 mA mm−1, which is three orders lower than that of the Ni/Au gate device. The lower gate leakage current is primarily caused by the higher Schottky barrier height of TiSi2/Cu on AlGaN/GaN HEMTs than that of Ni/Au by 0.36 eV. The threshold voltages of the TiSi2/Cu gate HEMTs were maintained to be equivalent to that of the Ni/Au gate device. No Cu diffusion was found at the metal and AlGaN interface by secondary ion mass spectrometry and scanning transmission electron microscopy. These results indicate that TiSi2 is a good barrier layer of Cu diffusion, and titanium disilicide/copper is a promising candidate for high-performance AlGaN/GaN HEMTs.

In this paper we report the first monolithic integration of InGaAs/InAlAs resonant tunneling diode (RTD) and high electron mobility transistor (HEMT) epitaxially grown on an InP substrate. The transconductance for a 1- mu m gate HEMT was 400 mS/mm and the peak-to-valley current ratio of the RTD was 3.1. Using this integrated structure, we demonstrate a static RAM cell circuit, consisting of a single transistor with two RTDs on the transistor. The memory cell circuit exhibits bistability, based on the RTD's negative differential resistance (NDR), at supply voltages from 0.6 to 1.1 V.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Recently, p-GaN gate high electron mobility transistors (HEMTs) have emerged as competitive participants for next-generation high-performance power supply applications. However, the threshold voltage ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) instability caused by short-circuit events jeopardizes the overall reliability of p-GaN gate HEMT and the power system in real applications. Hence, a noninvasive condition-based monitoring technique for critical device parameters is urgently required to enhance system safety without affecting the features of power electronic systems. In this paper, the threshold voltage instability dynamics of p-GaN gate HEMT under repetitive short stress were investigated to achieve high estimation accuracy and good monitoring efficiency. A double-phase adaptive neural network to predict the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> degradation kinetics based on the historical degradation recordings of the target device is developed. The degradation process contains a monotonous increasing process and an oscillation process divided by random changing point subject to Weibull distribution. Based on such characteristics, the extreme learning machines were combined with classic activation functions and periodic activation functions to predict the threshold voltage tendencies of p-GaN HEMTs under repetitive SC stress. The experiment results validate that the developed model based on static investigations can provide degradation predictions with high accuracies. Besides, the proposed method endows substantial benefits for the conditional-based monitoring problem of other newly emerging semiconductor devices that feature multiple scenarios during the dynamic process and differences between individual units.

Synchronous buck converter comprises a low side (LS) and a high side (HS) switch, where the HS switch works in the first quadrant (forward conduction)whereas the LS switch works in the third quadrant (reverse conduction). However, the reliability of the p-GaN gate high electron mobility transistor (HEMT) in reverse conduction is unclear. In this work, a comprehensive evaluation of this conduction mode for 200-V HEMTs was conducted. First, devices were subjected to time-dependent breakdown (TDB) measurements. By comparing different device configurations, the time to failure (TTF) was found to only scale with the number of gate fingers instead of the gate width W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> , proving the critical spots are the intersection of gate fingers over the N implantation isolation. The reverse operation voltage of V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> for ten years lifetime was extrapolated to be -5.4 V, corresponding to a failure of 0.01% and 100 gate fingers. Second, the devices were submitted to 200-V VDS OFF-state stress for 10 s, after which the reverse drain current saw a negligible degradation. Third, the reverse conduction of the HEMTs only showed a very limited deterioration after a long-time bias temperature instability (BTI) stress at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> = -5.5 V and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> = 0 V. This work proves the p-GaN gate HEMTs bear a high reliability in reverse conduction, which can simplify the design of synchronous power system.

Comparative assessment of InGaAs sub-channel and InAs composite channel double gate (DG)-HEMT for sub-millimeter wave applications

In this article, we propose a highly sensitive vertically plug-in source drain contacts high Schottky barrier based bilateral gate and assistant gate controlled bidirectional tunnel field Effect transistor (VPISDC-HSB-BTFET). It can achieve much more sensitive forward current driving ability than the previously proposed High Schottky barrier source/drain contacts based bilateral gate and assistant Gate controlled bidirectional tunnel field Effect transistor (HSB-BTFET). Silicon body of the proposed VPISDC-HSB-BTFET is etched into a U-shaped structure. By etching both sides of the silicon body to form vertically plug-in source drain contacts, the source and drain electrodes are plugged into a certain height of the vertical parts of both sides of the U-shaped silicon body. Thereafter, the efficient area of the band-to-band tunneling generation region near the source drain contacts is significantly increased, so as to achieve sensitive ON-state current driving ability. Comparing to the mainstream FinFET technology, lower subthreshold swing, lower static power consumption and Higher Ion-Ioff ratio can be achieved.

Complementary logic and memory circuits based on n-type indium gallium zinc oxide (IGZO) and p-type tin monoxide (SnO) thin-film transistors (TFTs) were demonstrated with low-voltage, hysteresis-free operation. Optimization of IGZO channel thickness precisely tuned the inverter switching point to near VDD/2, achieving a high voltage gain of 146.6 V/V at VDD = 3 V and ultra-low static power consumption in the nanowatt range. SU-8 passivation effectively suppressed bias-stress-induced degradation in both IGZO and SnO TFTs, enhancing long-term stability and reducing device variation. Using these optimized devices, a 3-stage ring oscillator exhibited stable oscillations, and 6T-SRAM cells achieved tunable static noise margins by adjusting transistor strength ratios. This work represents one of the first implementations of IGZO/SnO-based 6T-SRAM and demonstrates the potential of oxide semiconductor complementary circuits for low-power and reliable system integration, with promising future applicability to non-volatile memory and on-device artificial intelligence hardware.Graphical abstract

991013426071003412 HKUST Electronic Theses Device engineering for stable and reliable gate operation in Schottky-type p-GaN gate HEMTs by Junting Chen thesis 2025 1 online resource (xiv, 132 pages) : color illustrations Schottky-type p-GaN gate high electron mobility transistors (HEMTs) are…Read more ›

Nano/microelectromechanical systems (N/MEMS) based complementary logic circuits offer a physically robust alternative to conventional CMOS control systems, which are able to function in environments unsuitable for transistor devices. In this work we demonstrate novel, configurable, complementary logic circuits comprised entirely of relays at both NEMS and MEMS scale, which are capable of fulfilling all primary logic functions. Lifetime testing of the fabricated devices revealed two key failure modes: contact degradation and welding of high voltage cantilevers, both of which are caused by the charging and discharging of unwanted parasitic capacitances inherent to complementary relay structures. Devices are consequently damaged by high transient current and arc discharge between contacts. Several solutions are proposed and implemented to mitigate these issues, including minimization of unwanted capacitances, optimization of metallization scheme, introduction of intermediate operation cycles intended to increase time between state changes, and prevention of welding by preemptively charging capacitors to an intermediate voltage. To this effect, a detailed study of lifetimes for both single cantilevers and logic gate structures is presented comparing a variety of metallization schemes using Pt, Ti, TiN, and W, including their multilayer combinations. These varied optimization methods yielded single cantilever lifetimes of 1.74 billion cycles on average for devices with a Ti adhesion layer, a Pt primary layer, and a W surface layer to increase durability. Using the same metallization scheme, complementary logic structures achieved 0.6 million cycles on average. These results demonstrate the viability of robust N/MEMS based complementary logic circuits for safety critical control applications.[2024-0203]

A new low-power design method based on multiple low swing internal voltage values is proposed in this paper. It can be applied in logic circuits, which are designed with different logic family techniques such as Complementary Pass Transistor Logic (CPL), Domino Logic and Cascade Voltage Switch Logic (CVSL). The goal of this method is the reduction of the circuit power dissipation, with only a negligible increase in the area, without a reduction in the circuit operating speed. This is achieved with the replacement of a number of selected full swing voltage circuit components by low swing voltage components. The application of the proposed technique in a CPL 4-bit multiplier proved that 70% power dissipation reduction was achieved, with 30% area overhead, and no reduction in the circuit speed.

A new low-power design method based on multiple low swing internal voltage values is proposed in this paper. The proposed technique can be applied in logic circuits, which are designed with different logic family techniques such as Complementary Pass Transistor Logic (CPL), Domino Logic and Cascade Voltage Switch Logic (CVSL). The goal of this method is the reduction of the circuit power dissipation, with only a negligible increase in the area, and without a reduction in the circuit operating speed. This is achieved with the replacement of a number of selected full swing voltage circuit components by low swing voltage components. The application of the proposed technique in a CPL 4 bit multiplier proved that 30% power dissipation reduction was achieved, with 5% area overhead, and no reduction in the circuit speed.

This paper presents the impact of strain on the electrical characteristic such as drain current, threshold voltage, and subthreshold swing (SS) of double-gate tunnel FETs (DG TFETs) with a SiO 2 /High- ${k}$ stacked gate-oxide structure. The results obtained from simulation are discussed using energy band diagram, tunneling barrier width, and compared with conventional DG TFETs structure. From the simulation results, it is clear that application of strain on DG TFETs with stacked gate structure shows higher ${I}_{\mathrm{ON}}/{I}_{\mathrm{OFF}}$ , lower subthreshold swing (SS) and minimum ${V}_{\mathrm{T}}$ as compare to conventional DG TFETs structure. All the simulation are done in ATLAS 2-D device simulator from SILVACO for channel length of 60 nm using nonlocal band-to-band tunneling model and application of strain in the channel region.