Multi-level low swing voltage values for low power design applications

A new low-power design method based on multiple low swing internal voltage values is proposed in this paper. The proposed technique can be applied in logic circuits, which are designed with different logic family techniques such as Complementary Pass Transistor Logic (CPL), Domino Logic and Cascade Voltage Switch Logic (CVSL). The goal of this method is the reduction of the circuit power dissipation, with only a negligible increase in the area, and without a reduction in the circuit operating speed. This is achieved with the replacement of a number of selected full swing voltage circuit components by low swing voltage components. The application of the proposed technique in a CPL 4 bit multiplier proved that 30% power dissipation reduction was achieved, with 5% area overhead, and no reduction in the circuit speed.

Today, the major limitation of designing of high-speed integrated circuits (ICs) with conventional technology is the delay limiting the switching speed of the gates. As evident from already established logic styles like complementary pass transistor logic (CPL), differential cascode voltage swing logic (DCVSL), etc., the circuit exploits the property of noise reduction due to differential inputs. Ideally current mode circuits have constant current gain with no input impedance and finite output impedance. The current gain of the circuit is set to unity as current amplification leads to higher consumption of static power. MOS current mode logic (MCML) is graced with certain advantages which include low level of noise generation, static power dissipation independent of switching activity, low voltage swing, a weak dependence of propagation delay on fan-out load capacitance, lower power dissipation at higher frequencies, etc., out way the few disadvantages such as elaborated design process and increased number of design parameters. In this paper, we present an in-depth study of MCML base approach in which the analysis of low-power applications is performed at the target data rate of 1 Gbps. Work has been done on a standard CMOS technology of 0.18 μm.

Reports a novel low-voltage silicon-on-insulator (SOI) CMOS complementary pass-transistor logic (CPL) circuit using asymmetrical dynamic threshold pass-transistor (ADTPT) technique., Using the ADTPT technique to dynamically control the body bias of the pass-transistor via only one auxiliary transistor, the new SOI CMOS complementary pass-transistor logic (CPL) circuit provides superior speed performance at a low supply voltage as compared to the conventional pass-transistor logic circuits without the ADTPT technique as verified by the MEDICI simulation results. The ADTPT technique is especially effective for use in CPL circuits with serially-connected multiple inputs.

A new pass-transistor logic called the current-sensing complementary pass-transistor logic tree (CSCPTL) is proposed and investigated. The new logic circuit can be used in low-voltage low-power systems for high-speed applications. To examine the low-voltage applications, a 1.2 V supply voltage is selected for one battery back-up systems. The current-sensing scheme yields a good sensing speed with small voltage swing. The dc power dissipation of the current mode circuit makes it difficult to apply in low power applications. The new circuit can resolve the dc power problem in the current-sensing scheme. The new circuit has superior speed performance with a power-delay product comparable to LCPL which is acknowledged to have the most potential in low-voltage low-power digital circuits design. The CSCPTL can be operated at 1.2 V without changing the conventional 5 V CMOS process.

Two new structures for Differential Cascode Voltage Switch Logic (DCVSL) pull-up stage are proposed. In conventional DCVSL structure, low-to-high propagation delay is larger than high-to-low propagation delay this could be brought down by using DCVSL-R. Promoting resistors in DCVSL-R structure increase the parasitic effects and unavoidable delay and it also occupies more area on the chip (Turker et al., 2011). In order to minimize these problems, a new Ultra-Low-Power Diode (ULPD) structures in place of resistors have been suggested. This provides the minimum parasitic effects and reduces area on the chip. Second proposed circuit uses Complementary Pass Transistor Logic (CPTL) structure, which provides complementary outputs. This contributes an alternate circuit for conventional DCVSL structure. The performances of the proposed circuits are examined using Cadence and the model parameters of a 180 nm CMOS process. The simulation results of these two circuits are compared and presented. These circuits are found to be suitable for VLSI implementation.

This work examines the metal-ferroelectric-insulator-semiconductor (MFIS) negative-capacitance FinFET (NC-FinFET) based VLSI subsystem-level logic circuits. With the aid of a short-channel NC-FinFET compact model, we confirm the functionality and determine the standby-power/switching-energy/delay performance of logic circuits (5-stage inverter and 4-bit Manchester carry-chain (MCC) adder) employing 14nm ULP NC-FinFETs versus FinFETs. We show that the inverse $V_{ds}$-dependency of threshold voltage $(V_{T})$, also known as the negative DIBL, of NCFET is not only acceptable but also beneficial for the speed performance of both the static and pass-transistor logic (PTL) circuits, especially for the PTL at low $V_{DD}$.

Pass Transistor Logic (PTL) has attracted more and more interest during recent years, since it has proved to be an attractive alternative to static CMOS designs with respect to area, performance and power consumption. Existing automatic PTL synthesis tools use a direct mapping of (decomposed) BDDs to pass transistors. Thereby, structural properties of BDDs like the ordering restriction and the fact that the select signals of the multiplexers (corresponding to BDD nodes) directly depend on input variables, are imposed on PTL circuits although they are not necessary for PTL synthesis. General multiplexer circuits can be used instead and should provide a much higher potential for optimization compared to a pure BDD approach. Nevertheless-to the best of our knowledge-an optimization of general Multiplexer Circuits (MCs) for PTL synthesis has not been tried so far due to a lack of suitable optimization approaches. In this paper we present such an algorithm which is based on efficient BDD optimization techniques. Our experiments prove that there is indeed a high optimization potential by the use of general MCs-both concerning area and depth of the resulting PTL networks.

This paper presents low-power complementary pass-transistor adiabatic logic (CPAL) using two-phase power-clocks instead of four-phase ones. The two-phase CPAL uses complementary pass-transistor logic for evaluation and transmission gates for energy-recovery. It is more suitable for design of flip-flops and sequential circuits, as it uses fewer transistors than conventional CMOS transmission gate-based implementations and other adiabatic logic circuits such as 2N-2N2P. Adiabatic flip-flops (D, T and JK) based on the two-phase CPAL are introduced. A practical sequential system realized with the proposed adiabatic flip-flops is demonstrated. SPICE simulations show that the two-phase CPAL flip-flops consume less power than 2N-2N2P and CMOS implementation.

This paper explores different Full adder techniques such as Transmission Gate(TG) logic, Complementary pass transistor logic(CPL), Complementary metal oxide semiconductor(CMOS), Gate diffusion input (GDI) and Modified GDI (Gate Diffusion Input) logic. The main objective is find full adders providing low powered and high-speed with good voltage swing. GDI (Gate Diffusion Input) is one of the area effective, high speed and low power technique. It needs smallest amount of transistors as compared to conventional CMOS technology. But the drawback of GDI (Gate Diffusion Input) is that its output has poor logic swing. Modified Gate diffusion technique overcomes this problem.

Concurrent Error Detection (CED) methods are commonly employed to provide some level of error detection capability at the cost of some area and power overhead. In many applications, however, the error detection capability must be reconfigured dynamically, in order to adapt to the available power budget, criticality of the processed data, a thermal-safe schedule, etc. In this work, we propose a reconfigurable duplication-based CED infrastructure for logic circuits. The key idea is to enable/disable the operation of the duplicate circuit according to a set of control conditions. When CED is disabled, the inputs to the duplicate circuit retain their previous values (i.e., reduction in power dissipation via elimination of switching activity), yet errors are not detected (i.e., reduction in CED coverage). Experimental results using judicious and random selection of control conditions yield the same end-result; power dissipation is commensurate with CED coverage. Therefore, LFSR structures can be used to easily generate and reconfigure conditions, enabling their dynamic adjustment to adapt to the power constraints of the system.

A 64-bit low threshold voltage conditional carry adder using complementary pass-transistor logic for low-voltage and high-speed application was presented. The improved conditional sum addition rule can reduce the number of internal nodes and multiplexers in the adder design. And reducing the threshold voltage increases the speed of operation. Thus, a low threshold voltage design is favourable for implementing low-voltage, high-speed arithmetic systems. The performances of such circuits are compared with that of normal and zero threshold voltage schemes; the proposed circuit gets the lowest power-delay product and energy-delay product from 1.0V to 2.5V. The circuit is demonstrated to balance between power consumption and performance effectively.

Carbon nanotubes (CNT) field-effect transistor (CNTFET) could be a possible alternative to CMOS technology for future VLSI applications. In this work, a comparative study has been carried out on the effects of technology nodes and logic styles on power dissipation, delay, leakages, etc. The technology nodes that are considered here are 90 nm and 32 nm MOSFET technology, and 32 nm CNTFET technology. The logic families considered here are the conventional complementary metal-oxide-semiconductor (CMOS), complementary pass transistor logic (CPL) and transmission gate (TG). The digital circuits considered are NAND, NOR, XOR and MUX gates. HSPICE simulations have been carried out and observed that at 32 nm CNTFET technology, the least power, worst-case delay and least PDP are found as 15.5 nW, 3.11 ps and 0.048 aJ, respectively. It is witnessed that CNTFET-based logics are superior compared to other logic families at different technology nodes.

The low ionization rate of Mg acceptors in the p-gallium nitride (GaN) layer is a critical factor accounting for the low current density of E-mode GaN p-FETs. In this work, polarization-enhanced technology was adopted to enhance the ionization rate of the p-GaN channel. High-performance recessed-gate E-mode GaN p-FETs were fabricated to enable GaN complementary logic (CL) circuits. During fabrication, the channel thickness (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>x</i></sub>) is found to be a critical parameter that influences the device metrics. With a decrease in <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>x</i></sub> (i.e., larger recess depth), a more negative threshold voltage (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>th</roman></sub>) is achieved; however, the trade-off is an increase in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\textit{R}_{\biosc{on}}$</tex-math></inline-formula>. The E-mode GaN p-FET with <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>x</i></sub> = 32 nm exhibits a <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>th</roman></sub> of -1.1 V, a high current density of 17.7 mA/mm, a high <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\textit{I}_{\biosc{on}}$</tex-math></inline-formula>/<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\textit{I}_{\biosc{off}}$</tex-math></inline-formula> of 6.9 × 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>7</roman></sup>, and a low subthreshold swing (SS) of 93 mV/dec. Furthermore, an E-mode n-channel p-GaN gate high electron mobility transistor (HEMT) was fabricated on the same epi-wafer, exhibiting a <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>th</roman></sub> of 1.3 V and an <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\textit{R}_{\biosc{on}}$</tex-math></inline-formula> of 6 <roman xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Ω⋅</roman>mm. Finally, a GaN CL inverter was fabricated and demonstrated under <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>DD</roman></sub> = 6 V. Rail-to-rail voltage swing and low static power consumption were both achieved. This work further validates the feasibility of GaN CL integrated circuits and power integrated circuits (PICs).

The speed and area advantage of domino logic circuits compared to static logic circuits makes them a favorite choice for the critical path of high performance processors. However they suffer from low noise margin. Noise is not scaling at the same rate as the supply voltage, and therefore new domino logic circuits are required to increase the noise margin. In this paper a new domino circuit is introduced. Simulations for a 3-input 180 nm AND gate shows that the noise margin can be increased by 62% with only 3% reduction in speed.

A high-performance adder is one of the most critical components of a processor which determines its throughput, as it is used in the ALU, the floating-point unit, and for address generation in case of cache or memory access. In this paper, low-power design techniques for various digital circuit families are studied for implementing high-performance adders, with the objective to optimize performance per watt or energy efficiency as well as silicon area efficiency. While the investigation is done using 100 MHz, 32 b carry lookahead (CLA) adders in a 0.6 /spl mu/m CMOS technology, most techniques presented here can also be applied to other parallel adder algorithms such as carry-select adders (CSA) and other energy efficient CMOS circuits. Among the techniques presented here, the double pass-transistor logic (DPL) is found to be the most energy efficient while the single-rail domino and complementary pass-transistor logic (CPL) result in the best performance and the most area efficient adders, respectively. The impact of transistor threshold voltage scaling on energy efficiency is also examined when the supply voltage is scaled from 3.5 V down to 1.0 V. >