Three phase domino logic circuit

An ultra-thin natural-source-based cellulose derivate is used in a bilayer gate dielectric for organic complementary inverters. Extraordinarily high small-signal gains up to 1600, a very sharp transition region (as low as 40 mV), a full rail-to-rail swing, a balanced noise margin of 92.5%, and “long-time” stability are shown, revealing that these inverters are highly suitable for complex circuit designs. For more than a decade now the research in organic electronics was driven by unique consumer markets demanding for electronic circuits on flexible substrates over large areas and ideally at low cost. Meanwhile, versatile macroelectronic applications with attractive form factors such as flexible displays,1-4 large-area sensor arrays,5-11 e-paper,12, 13 low-cost radio-frequency identification tags,14-18 and bendable microprocessors19 have been realized using organic thin-film transistors (OTFTs) as the essential element. In the majority of these applications OTFTs are integrated either in the form of arrays or as digital logic. The fundamental building block of digital logic is the inverter, a circuit that inverts an input signal. Much work has been devoted in the last five years to design unipolar inverters using p-type-only OTFTs.18-23 Unfortunately, unipolar logic based on single gate OTFTs always suffers from high power consumption and low noise margin coupled with high noise margin variability and therefore impedes the fabrication of complex circuits having hundreds or more logic gates.19, 22, 23 In this context, it stands beyond doubt that the integration of both n-type and p-type transistors in complementary organic-based circuits12 is very advantageous due to a lower power dissipation, higher noise margin, better operational stability, and easier design of the circuit.24-27 To date, several major obstacles complicated the development of organic complementary circuits, which are as follows: i) the lack of n-channel OTFTs with a performance comparable to the p-channel OTFTs, ii) the challenge of device stability (difficulty in fabricating OTFTs with hysteresis-free characteristics), and iii) the difficulty in fabricating sufficiently thin gate dielectrics allowing for low supply voltages. Although many recently reported complementary organic inverters are impressive with respect to their low operation voltages (≤5 V),27-36 high static gains (>100 V/V),25, 28, 30, 32 and large noise margins (>80%),25, 35, 37, 38 only few of those can combine low-voltage operation with high gain and sufficient immunity against electrical noise.39 Moreover, there have been few investigations of the influence of hysteresis and threshold voltage shifts on the inverter characteristics, which typically gives rise to electrical instabilities and performance limitations of those devices.32, 39 The inverter's noise margin is the most critical parameter, since it directly determines the maximum complexity of circuits.22 Particularly, interesting applications of organic electronic circuits are found in analog electronics that allow for the read-out and processing of signals from printed large-area sensors and form an interface to silicon electronics. Examples are analog-to-digital (A/D) converters, operational amplifiers, and comparators, all including several tens of transistors, thus requiring both high gain and a large noise margin to be functional as well as sufficient processability. It is interesting to note that the majority of organic complementary inverters already mentioned24-34, 36-40 relied on pentacene as the p-type semiconductor (14 incidences), fluorinated copper phthalocyanine (6 incidences), or N,N′-ditridecylperylene-3,4,9,10-tetracarboxylic diimide (5 incidences) as the n-type material. On the contrary, the variation in gate dielectric materials that are used is much higher with an emphasis on hybrid dielectric systems. Hybrid systems allow accounting for both a high dielectric breakdown voltage and an engineered interface to the semiconductor. Moreover, the implementation of biodegradable and biocompatible materials represents a new niche in the organic electronics research, aimed to address the issues of cost and toxicity to humans and environment posed by nowadays electronics, a topic that was recently reviewed elsewhere.41-43 Accordingly, we have demonstrated the usage of a novel hybrid and biodegradable high-k gate dielectric material system based on a cellulose derivative for low-voltage complementary organic circuits with exceptional high noise margins.35 Previous work done in our laboratories demonstrated the fabrication feasibility of complex circuits, where the electrode patterning was performed by a self-aligned photolithography technique.44, 45 This process can easily be transferred to an anodized aluminum (Al2O3) + trimethylsilyl cellulose (TMSC) based bilayer system; the respective results will be published soon. To follow on this preliminary work we have developed an extraordinarily well-performing complementary inverter technology based on a hybrid dielectric composed of a bilayer of alumina (Al2O3) and trimethylsilyl cellulose (TMSC) and pentacene or C60 for the p-channel and the n-channel organic semiconductor, respectively. It outperforms any inverter reported so far with respect to the combination of excellent key parameters, such as record DC gain of above 500 V/V, low operation voltage of only 4 V, and large noise margin up to 92.5%. In order to clarify the origin for this high performance, special attention is given to the investigation of the semiconductor–dielectric interface, the semiconductor morphology, the nature of traps, the influence of mobility levels on the inverter performance and its long-term stability. This article is not meant to report new materials and systems, but rather find explanations and present a thorough analysis of the extraordinary performance of the cellulose derivative (TMSC) dielectric and the TMSC to semiconductor interface in organic field-effect transistors and simple inverter circuits. All OTFTs presented in this work have a bottom gate, top contact device architecture, as illustrated in Figure 1a. The transistor fabrication process is described in detail in the Experimental Section. The semiconducting layer is pentacene for p-type and C60 (fullerene) for n-type conduction. For the gate dielectric, an inorganic (Al2O3)–organic (TMSC) bilayer is chosen with 28 and 30 nm layer thickness, respectively. The dielectric properties of both single-layer TMSC films and bilayer Al2O3 + TMSC films, were investigated by current–voltage (I(V)), capacitance–frequency (C(f)), and capacitance–voltage (C(V)) measurements in appropriate capacitor structures with 72 nm insulator layer thickness of pure TMSC and 28 + 30 nm of bilayer film of Al2O3 + TMSC, respectively. In Figure 1b, the I(V) curves of a representative capacitor formed by a single layer cellulose dielectric is shown, whereas in Figure S1a (in the Supporting Information) the curve with bilayer dielectric is displayed. A comparison of I(V) curves of a single layer and bilayer dielectric is displayed in Figure 1c. At an electric field of 3.0 MV cm−1 (equivalent to ≈22 V) a current density on the order of 10−6 A cm−2 is observed for the single-layer TMSC. A breakdown field of 4.5 ± 0.3 MV cm−1 is extracted from eight appropriate capacitor structures. One representative C(V) measurement is displayed in Figure 1d. Its capacitance of about 29 nF cm−2 corresponds to a dielectric constant of εR = 2.4 ± 0.2 at 1 kHz with an excellent stability at frequencies down to 0.5 mHz (virtually flat dielectric constant and low dielectric losses which are indicative of a high purity and negligible amount of mobile ionic species) as illustrated in Figure 1e.46 In comparison, capacitors based on the bilayer dielectric have three orders of magnitude lower leakage currents (≈10−9 A cm−2) at an electric field of 3.0 MV cm−1 corresponding to ≈17.5 V and an effective capacitance of 53 nF cm−2 at 1 kHz (see Figure S1a,b, Supporting Information). As can be derived from Figure S1c (in the Supporting Information) the permittivity of the bilayer dielectric also shows excellent stability over the tested frequency range (1 mHz to 10 kHz). The measured capacitance value of the dielectric is in good agreement with calculations by assuming a permittivity of 9 and a thickness of 28 nm for the Al2O3 layer as well as a measured permittivity of 2.4 ± 0.2 (Figure 1e) and 30 nm thickness for the TMSC layer (see the Experimental Section). In any OTFT with bottom gate architecture the surface properties of the gate dielectric (surface energy, surface roughness) decisively affect the arrangement and growth of small molecule semiconductors. The surface energy of spin-coated TMSC thin films was determined by contact angle measurements. With a water contact angle of 98.5°, TMSC can be regarded as a hydrophobic, low energy surface material with a total surface energy of γ = 24.2 ± 0.6 mN m−1, separable in a small polar component γP = 1.8 ± 0.5 mN m−1 and a dispersive component γD = 22.4 ± 0.1 mN m−1. The average surface roughness, indicated by the root mean square (rms)–roughness values, was found to be only 0.77 ± 0.1 nm by atomic force microscopy (AFM) measurements. On this smooth and low energy TMSC surface, a small-grain growth mode with average grain sizes between 150 and 300 nm for pentacene (shown in Figure 1a) and 50 nm for C60 was observed by AFM measurements. In Figure 2, typical electrical characteristics of OTFTs with either C60 or pentacene as the semiconducting layer are plotted. Both p- and n-type transistors are based on the inorganic–organic bilayer gate dielectric composed of Al2O3 and TMSC. The output characteristics ID(VDS) are displayed in Figure 2a,b, whereas the transfer characteristics ID(VGS) are shown in Figure 2c,d. Both transistor types display very small hysteresis between forward and reverse voltage sweeps. The output characteristics show clear saturation, but for the pentacene-based OTFT a non-linear behavior of the drain current at very low drain voltages is observable (Figure 2b). Such an S-shape of the output curve has been already observed and reported for many different device configurations and has sometimes been attributed to a lateral field dependent contact resistance.47-55 In Table 1, the critical device parameters Von (onset voltage), Vthr (threshold voltage), S (subthreshold swing), μlin (charge carrier mobility in the linear regime), and μsat (charge carrier mobility in the saturation regime) are compiled and averaged over eight devices for each transistor type. On average, C60-based OTFTs show a charge carrier mobility of 0.7 cm2 V−1 s−1 in the saturation regime, a threshold voltage of 1.3 V, and a small subthreshold swing of 305 mV dec−1. Pentacene-based OTFTs have on average a mean threshold voltage of −4.7 V, a very small subthreshold swing of 225 mV dec−1, and a field-effect mobility of 0.22 cm2 V−1 s−1 in the saturation regime. The gate leakage currents are very low and in the range of 10−10 A. The balanced performance of our p- and n-type OTFTs, as well as the fact that both transistor types strictly behave as normally off transistors at zero applied gate voltage is a good base for integrating them in complementary organic inverters. A schematic image of such a complementary inverter circuit is displayed in Figure 3a together with the voltage transfer characteristics (VTCs) of a typical device and the static gain measured for operation voltages of VDD = 4, 5, 6, and 7 V. The inverter exhibits extraordinarily high small-signal gains; for all operation voltages, gains above 500 V/V are measured with a maximum value of about 1000 V/V for VDD = 7 V. The best performing device even has a maximum gain value of 1600 V/V. Moreover, a very sharp transition regime (ΔVin ≤ 40 mV) and a full rail-to-rail swing are observed. The extracted inverter parameters are compiled in Table 2. The switching threshold voltages VM are found to be very close to the ideal value of VDD/2 at all operation voltages with a nearly perfect fit (e.g., VM = 2.04 V at VDD = 4 V). In Figure 3b, the mismatches of the threshold voltages to the ideal values (ΔVM) are plotted as a function of VDD revealing a linear increase of ΔVM with the supply voltage. This means that the asymmetry of the VTCs increase with increasing the operation voltages. Additionally, the noise margins (NM) are plotted in Figure 3b as a function of VDD, illustrating the linear decrease of the NM with increasing operation voltage. Such a behavior reveals the direct correlation between ΔVM and NM and is an indication of the deviation of the VTCs from perfect symmetry. The noise margin is an important figure of merit of an inverter stage and measures the immunity against inevitable transistor parameter variations and electrical noise.56 There are several ways to determine the noise margin of an inverter. One convenient way is called the “maximum equal criterion” (MEC), where the NM is found by the maximum square that fits between inverter transition curve and the mirrored inverter curve as shown in Figure 3c.22, 35 The NM values for all the supplied voltages are listed in Table 2. The noise margin is mainly limited by the steepness of the transition ΔVin and the position of the switching threshold voltage VM (VM = Vin = Vout) as shown in Figure 3c. High and balanced noise margins are found when the ideal condition VM = VDD/2 is met, thus when VM = Vin =VDD/2 = Vout. The inverter in Figure 3c has a NM of 1.79, which is 90% of the maximum theoretical value for a supply voltage of 4 V, determined by the “maximum equal criterion.” Additionally, the “negative slope criteria” reveals a balanced NM of 1.85 V (92.5%) for a supply voltage of 4 V. The OTFTs with pentacene and C60 semiconductor layers (as used in the complementary inverters) were also analyzed with regard to their long-term stability. The dependence of their onset voltage and charge carrier mobility on the time period after preparation is plotted in Figure 4 based on measurements of at least five devices for each transistor type. The error bars display the standard deviations. p- and n-type devices exhibit an onset voltage shift of +1.3 and +0.95 V, respectively, over a period of 45 days. The main part of the shift occurred either after the first or after the second measurement and then the onset voltage shift tended to saturate. It seems that both pentacene- and fullerene-based devices stabilized their electrical properties after few days. Between day 8 and day 45 no significant change in the transfer characteristics was observed. Concerning the subthreshold swing, no significant change was observed over 45 days (S = 215 mV dec−1 (0 days), 210 mV dec−1 (8 days), and 225 mV dec−1 (45 days)) in the pentacene OTFTs, indicating that the interface trap density is stable. On the contrary, after 8 days an increase of the swing was observed for the C60 devices from 305 mV dec−1 (0 days), to 410 mV dec−1 (8 days), to 430 mV dec−1 (45 days). The mean value of the charge carrier mobility of the pentacene OTFTs showed no significant variation over 45 days: 0.22 cm2 V−1 s−1(fresh sample), 0.19 cm2 V−1 s−1 (after 8 days), 0.21 cm2 V−1 s−1 (after 45 days). In contrast, a strong reduction of about one order of magnitude (from 0.7 to 0.06 cm2 V−1 s−1 within the first 8 days and to 0.05 cm2 V−1 s−1 after 45 days) was observed for the fullerene transistors. In order to test the reliability of our OTFT devices we have also performed negative and positive bias stress tests. The bias stress was done 1 day after fabrication, on devices which had been previously measured only once. A reversible negative onset voltage shift of about 400 mV was observed under negative bias of −7.5 V over 21 hours stress (see Figure 5a,b) The main part of the negative voltage shift occurred during the first 2 hours (300 mV) whereas shift saturation was reached after 6 hours. The positive bias stress resulted in a significantly smaller positive onset voltage shift (ca. +100 mV over 4 hours stressing the device). Devices that were stored for seven months in the glovebox showed no bias stress effect at all (i.e., shift of the onset voltage) when their transistor characteristics were measured at regular intervals during the storage period. In order to investigate the “long-time” behavior of complementary inverters, electrical measurements were done after 1, 4, 8, and 45 days of the respective device preparation. Inverters were measured 1 day after device stabilization (see Figure 4a,b). The “long-time” behavior of complementary inverters is shown in Figure 4c,d where the VTC and gain curves are plotted as a function of time. For the lowest VDD of only 4 V, a small shift of the switching threshold voltage was measured: starting from 2.04 V after 1 day to an identical value of 2.17 V after 8 and 45 days, respectively, with a related exceptional high noise margin of 1.79 V (90% of the theoretical maximum) after 1 day and 1.74 V (87%) after 8 and 45 days. It is interesting to note that, after 8 days of storage time, the hysteresis in inverter characteristics was virtually negligible (<100 mV, see Figure 4d) and moreover, repeated measurements did not change the inverter transition, although the gain was somewhat reduced (from 503 (0 days) to 320 (8 days) and 195 (45 days)). The operational stability of the VTC was shown over a period of at least 45 days (Figure 4c for VDD = 4 V). Furthermore, the remarkable long-term stability of these TMSC-based complementary inverters was demonstrated by 16 consecutively recorded inverter curves that are virtually superimposed over one another (Figure 5c). The current–voltage characteristics show that the Al2O3 + TMSC bilayer capacitors have substantially lower leakage currents than the single TMSC layer devices. Due to the roughness of the aluminum bottom electrode with spikes up to 10 nm, the anodization process is a convenient method to reduce the leakage currents for at least three orders of magnitude at an electric field of 3 MV cm−1 as displayed in Figure 1d and make the dielectric layer more robust.57 Another advantage of the anodization step is the substitution of the hydroxide of the native oxide layer. Finally, the subsequent short oxygen plasma treatment (see the Experimental Section) is sufficiently removing all residuals left after the anodization process. This procedure allows for the generation of a pure and trap-reduced dielectric interface to the organic semiconductors, by measurements at low revealing a virtually flat permittivity in the mHz to kHz frequency range and low dielectric losses which both are indicative of a high purity and negligible amount of mobile ionic The generation of this excellent interface is in virtually hysteresis-free characteristics of all the One important that the performance of OTFTs, and in the charge carrier is the of the As shown by several the of the surface energy of the to that of the is one important the growth For a low surface energy material with a smooth surface TMSC, a growth mode is and with a rather high density and small grain sizes are formed (see Figure The high density of grain a significant decrease of the charge carrier since grain as charge On the a better between pentacene on low surface energy materials TMSC with and better reduce the of trap thus the mobility of charge in the In there is an between grain related and interface with regard to their influence on charge carrier The low subthreshold swing observed in all our pentacene-based OTFTs is indicative of a low interface trap density which the influence of the large grain trap density on the charge carrier Accordingly, a mobility 0.2 cm2 V−1 s−1 is observed in the p-type devices. In C60 films, the influence of on the charge carrier mobility is by far not as significant as in pentacene films, which is attributed to the of the fullerene In the pentacene OTFTs (see Figure a non-linear current increase in the linear regime of the ID(VDS) output characteristics is at higher gate have been in to such a which can be observed in bottom gate The explanations i) the of the charge carrier mobility for semiconductor ii) currents that the of the mobile by an effective under the drain and iii) large at the electrode from an energy between the work of contact material and semiconductor films, a gate or large contact are found in our of these it has been shown that a mobility in combination with a small contact in a non-linear drain voltage dependence of the current due to The from a of from trap and a dependence of on the drain A respective of the pentacene output curve in Figure the dependence in the regime 2 V, thus indicating that a mobility has to be The of any hysteresis in the I(V) curves and the low and value of the subthreshold swing a low density of interface in the pentacene are not for the observed and the of the as by the of the pentacene layer gives rise to which to a field dependence of the charge carrier This is all the more given that the pentacene grain sizes are 300 nm at a large density of grain As by Figure 4 the characteristics of both pentacene- and C60-based OTFTs show a positive onset voltage shifts storage which after a of measurements. The virtually subthreshold swing in pentacene as well as the negligible hysteresis as the origin of the On the contrary, it seems that trap are for the positive onset voltage shift in are either over time or during the first measurements by the applied positive gate be easily by the gate bias and therefore are not to the swing, but the small onset voltage in pentacene-based It has been reported by many that the of the of trap in pentacene trap also be due to such as at the a at the or a at the fabrication and transfer from the to the measurement stage the semiconductor layer and rise to such For oxygen can even the devices are to but transferred directly and measured in a glovebox with reduced oxygen and water have also observed that the of oxygen with pentacene is in the that these are under device operation with the of oxygen in the grain observed that the storage of devices in and their subsequent measurement in did not a change in their I(V) also observed that the storage time to the first measurement has influence on the device (i.e., on the onset voltage in this of and the first measurement the of to the of oxygen or with the which in a second are by Moreover, also are are not as in the as the (see and This an for the positive shift of the onset voltage between first and second measurement (Figure and also for the saturation of the onset voltage shift in In order to clarify which of are present in our we performed measurements on pentacene films (in and after storage in for (see Figure Supporting Information). storage under a small increase of the at energy is observed that can be attributed to the to and The analysis reveals an increase of the from 0.2 to At the position no change is that trap in our devices for bias stress and the positive onset voltage can mainly be attributed to It be that the of any mobility in pentacene OTFTs against an of pentacene both are to oxygen For the C60 transistors, one a strong decrease of the charge carrier mobility during 8 days of storage which is by all over the device grain This is a effect of The decrease in charge carrier mobility and the at the interface that the subthreshold swing is in a positive onset voltage shift of the C60 transistors. With respect to the complementary inverters, noise margin values beyond from the maximum theoretical value for all supply voltages are and the high operational of the OTFT devices. At a very low supply voltage of 4 V, our bilayer organic complementary inverters have a static gain of more than 500 V/V with a noise margin of 92.5%, which is already reported devices with architecture (see the of inverter performance given in 38 and also gain values above 1000 V/V values up to 1600 were measured for our devices. This is all the most as the charge carrier mobility values of the transistors are not thus the that the of the mobility values between p- and n-channel with the virtually hysteresis are the factors for high gain and high noise margin Accordingly, a mobility 1 be the the is not high ≤ it can be by and p-channel transistors with different In our the mobility is The static of a complementary inverter is determined by technology parameters, the parameters of p- and n-type transistors. A good of these parameters a good saturation of both output can to a significant increase of the gain A is shown in the Supporting Furthermore, high gain values are also determined by the interface An insulator with an low trap density (as this is the for is in having I(V) curves with virtually zero Accordingly, it is to measurements with a very high voltage small voltage thus one to the high gain value of the complementary inverter it by hysteresis The noise margin with increasing VDD due to their strong this is also for the of the VTCs by see Figure A for this behavior can be found in the bias stress that was observed for both types of transistors. The negative shift of Von under negative gate and the positive

Compared to binary logic, the multi-valued logic circuits provide very small chip size, higher speed, and considerably small number of interconnections and simpler realization of logic functions. However, the main drawback of these circuits is the lower noise margin. The noise margin decreases as the radix of multi-valued system increases. Due to the low noise margins, it is necessary to restore or recover the nominal levels of the signal after a certain number of cascaded stages. In this paper a new current mode CMOS restoration circuit is presented and evaluated.

Dynamic logic can provide significant performance and power benefit compared to implementations using static gates. Unfortunately dynamic gates have traditionally suffered from low noise margins, which limits their reliability. A new logic family, called complementary dynamic logic (CDL), is presented. CDL replaces the standard keeper logic with a dual dynamic keeper gate that is applicable to all dynamic gate structures. CDL provides dynamic gates with two novel characteristics: hysteresis and arbitrarily configurable noise margins. However, these two benefits come at the cost of reducing the gain and increasing the energy of the dynamic gate. This paper compares the noise, energy, performance, gain, and total transistor width trade- offs of CDL and three other logic families applied to a 65nm cell library consisting of 23 functions. The results show that the performance advantages of dynamic domino gates can be maintained while providing significantly enhanced noise margins using CDL structures.

In recent years, due to the high ability of the multi‐valued logic design in nanotechnology, the interest in the design of it has been renewed. Using multi‐valued logic can lead to reduction of interconnections in the chip. This study presents two novel designs of a ternary memory cell using carbon nanotube field effect transistors (CNFETs) with only one supply voltage. In the previous works, a ternary latch has been used to store the ternary value, which has a considerably more static power and lower static noise margin in comparison to a binary latch. The proposed memory cells are based on decoding the ternary value to the binary one and saving in two binary latches; in this way, the storage power is sharply decreased and the static noise margin of the proposed ternary memory cell is also increased considerably to get close to that of a binary memory cell. The results of the simulation, using the HSPICE software and the Stanford 32 nm CNFET library with the voltage of 0.9 V, demonstrated that the proposed ternary memory cell achieved significant power saving and static noise margin improvement, as compared to the previous works with the same transistor count, which was expected.

With the scaling of the CMOS technology, domino logic circuits experience larger leakage currents, which affect their robustness and performance. The leakage can be compensated by using a properly sized PMOS keeper transistor, at the cost of circuit delay increase. Hence, it is expected that the performance improvement of domino logic will stop in future technology nodes, due to increased required keeper size to maintain robustness. In this paper, we will study different methods of keeper sizing for comparing the performance of CMOS-OR domino logic circuits designed using Predictive Technology models of 32nm, 22nm and 16nm CMOS technology nodes. The keeper size will be adjusted to obtain the same robustness (noise immunity) across the technology generations. With this method of keeper sizing across technology nodes, the simulation results shows that indeed the delay of a low fan-in domino circuit increases from 32nm to 22nm node and the domino circuits fail to operate at 16nm node. For a high fan-in domino gate, however, the delay reduces from 32nm to 22nm; and the circuit fails at 16nm.

This paper demonstrates the critical role that Ferroelectric (FE) layer thickness (tFE) plays in Negative Capacitance (NC) transistors connecting device and circuit levels together. The study is done through fully-calibrated TCAD simulations for a 14nm FDSOI technology node, exploring the impact of tFE on the figures of merit of n-type and p-type devices, voltage transfer characteristic (VTC) and noise margin of inverter as well as the speed of buffer circuits. First, we analyze the device electrical parameters (e.g., ION, SS, ION/IOFF and Cgg) by varying tFE up to the maximum level at which hysteresis in the I-V characteristic starts. Then, we analyze the deleterious impact of Negative Differential Resistance (NDR), due to the drain to gate coupling, demonstrating how it imposes an additional constraint limiting the maximum tFE. We show the consequences of NDR effects on the VTC and noise margin of inverter, which are essential components for constructing robust clock trees in any chip. We demonstrate how the considerable increase in the gate’s capacitance due to FE seriously degrades the circuit’s performance imposing further constraints limiting the maximum tFE. Further, we analyze the impact of tFE on the SRAM cell static performance metrics such hold noise margin (HNM), read noise margin (RNM) and write noise margin (WNM) at supply voltages of 0.7V and 0.4V. We demonstrate that the HNM and RNM in a NC-FDSOI FET based SRAM cell are higher then those of the baseline FDSOI FET based SRAM cell noise margin and further increase with tFE. However, the WNM in general follows a non monotonic trend w.r.t tFE, and the trend also depends on the supply voltage. Finally, we optimize the design of the SRAM cell considering overall performance metrics. All in all, our analysis provides guidance for device and circuit designers to select the optimal FE thickness for NCFETs in which hysteresis-free operations, reliability, and performance are optimized.

In this work, bulk negative capacitance junctionless (NCJL) transistor design is proposed as an alternative to conventional silicon-on-insulator (SOI) NCJL devices to minimize the temperature induced variations. The bulk architecture enables improved gate electrostatic control by shifting the conduction channel towards the front interface, thereby enhancing the matching between gate and ferroelectric capacitances. Through careful design optimization, results showcase that bulk NCJL transistor designed with moderate bulk doping of 7×10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">18</sup> cm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> achieves superior threshold voltage (V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</inf>) stability and relatively lower subthreshold swing (S<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">swing</inf>) as compared to its SOI counterpart at elevated temperatures. The improved V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</inf> stability translates into an enhanced noise margin (NM) along with lower NM variation in bulk NCJL inverter operation at elevated temperatures. The results underscore the outperformance of bulk NCJL transistors for low-power logic applications.

A new low-power design method based on multiple low swing internal voltage values is proposed in this paper. It can be applied in logic circuits, which are designed with different logic family techniques such as Complementary Pass Transistor Logic (CPL), Domino Logic and Cascade Voltage Switch Logic (CVSL). The goal of this method is the reduction of the circuit power dissipation, with only a negligible increase in the area, without a reduction in the circuit operating speed. This is achieved with the replacement of a number of selected full swing voltage circuit components by low swing voltage components. The application of the proposed technique in a CPL 4-bit multiplier proved that 70% power dissipation reduction was achieved, with 30% area overhead, and no reduction in the circuit speed.

A new low-power design method based on multiple low swing internal voltage values is proposed in this paper. The proposed technique can be applied in logic circuits, which are designed with different logic family techniques such as Complementary Pass Transistor Logic (CPL), Domino Logic and Cascade Voltage Switch Logic (CVSL). The goal of this method is the reduction of the circuit power dissipation, with only a negligible increase in the area, and without a reduction in the circuit operating speed. This is achieved with the replacement of a number of selected full swing voltage circuit components by low swing voltage components. The application of the proposed technique in a CPL 4 bit multiplier proved that 30% power dissipation reduction was achieved, with 5% area overhead, and no reduction in the circuit speed.

Dynamic CMOS logic circuits are used in modern VLSI circuits because of its high system performance and its performance is high due to higher speed over static CMOS circuit. However dynamic logic circuit has less noise immunity and increased leakage power dissipation. Increase in leakage current combine with reduced noise margin results in performance degradation of dynamic circuits. In this paper DOIND logic approach is proposed for domino logic which reduces the leakage current with minimum delay penalty. Simulation is performed at 70 nm technology node for a domino logic and DOIND logic buffer using tanner EDA tool. Simulation results shows that proposed DOIND approach decreases the leakage current 93.3%, static power 93.3% and static energy 86.66% at supply voltage 1.15V. Proposed circuit also improves dynamic power 60.78%, dynamic energy delay product (EDP) 62.18% and dynamic power delay product (PDP) 62.07% at 1.15V supply voltage.

As compared to static logic, domino logic circuits are always preferable for high performance circuit designs because of their less number of transistor requirement and high operational speed. Due to the presence of charge sharing problem and less noise tolerance this logic is not broadly accepted for all logic designs. The desired output of the circuit can change with a little noise pulse in the input of domino logic. Domino logic circuit has two stages first is dynamic logic part which is followed by a static inverter. This static inverter consumes very less power and has high noise immunity. In this paper a novel circuit called current mirror footed domino logic has been proposed for CMOS domino logic. This proposed domino logic is noise tolerant and has low power consumption than the basic footed and footless domino logic styles. Unity noise gain (UNG) found is also good for this logic style as compared to the previous proposed logic styles.

As continue scaling down the transistor feature size subthreshold leakage current becomes major component of total power dissipation. This paper presents comparative analysis of different dynamic logic circuits for reducing subthreshold leakage current with improved performance in dynamic logic circuits. In this paper DOIND logic approach is proposed with and without body biasing of DOIND transistors for domino logic which reduces the leakage current with minimum delay penalty. Simulation is performed at 70 nm technology node for a different logic buffer using tanner EDA tool. Simulation results shows that reduction in leakage current by DOIND and reverse body biased (RBB) DOIND approaches are 89.72% and 89.35% respectively. Static power and energy for DOIND and RBB DOIND approaches are also improved by 45.46%, 37.07%, 45.28% and 8.66% respectively.

A variable threshold voltage keeper circuit technique is proposed for simultaneous power reduction and speed enhancement of domino logic circuits. The threshold voltage of the keeper transistor is dynamically modified during circuit operation to reduce the contention current without sacrificing noise immunity. A four-bit multiple-output domino carry generator for a carry lookahead adder is designed with the proposed circuit technique. It is shown that the variable threshold voltage keeper circuit technique enhances the circuit evaluation speed by up to 60% while reducing power dissipation by 37% as compared to a standard domino logic circuit. It is also shown that the proposed domino logic circuit technique offers 20% higher noise immunity as compared to a standard domino circuit with the same evaluation delay characteristics.

Energy efficient computing is one of the primary requirements of ubiquitous battery-operated edge devices including mobile phones, wearables, active implantable medical devices, unmanned aerial, autonomous, and electric vehicles, and hardware modules used in smart IoT infrastructure and cyber-physical systems. One of the primary sources of loss in energy efficiency is the leakage current of logic and memory circuits. In addition, the emergence of on-device intelligence requires a greater number of computations, increased storage per device, and an increased number of operations per watt. Operating circuits at ultra-low voltages including near- and sub-threshold is an effective means to improve the energy efficiency. However, circuit techniques, algorithms, and power management methodologies are required that are tailored to ultra-low voltage operation. Moreover, novel techniques and architectures are needed to improve the overall energy efficiency of circuits that implement neural network models. Techniques to reduce and conserve the leakage current of an IC are, therefore, essential to further minimize the consumed power of a circuit. In this research, novel circuits and algorithms are developed that allow for robust and energy efficient ultra-low voltage operation. Completed research tasks include the development of dynamic differential signaling based logic (DDSL) families, interface circuits that allow for signal propagation between ultra-low voltage and nominal voltage power domains, supply and threshold voltage optimization, and clock-power co-design for sub-threshold operation. The developed DDSL families operate between 400 mV and 450 mV and reduce the total power consumption to 0.96x that of CMOS logic circuits, while improving the performance and noise margin by, respectively, 1.4x and 2.5x. The developed interface circuits include a single ended level shifter and a bidirectional input/output (I/O) circuit, which efficiently convert an input voltage of 450 mV to an output voltage of 3.3 V while consuming only 4.87 mW. The developed clock-power co-design methodology provides a robust power supply voltage of 250 mV to the clock distribution network while assuring resilience to as much as 10% noise on the power network. A novel power management technique defined as 'leakage reuse' is developed to recycle the leakage current from idle circuits or cores and deliver the recycled energy to active circuit blocks or cores. The circuit techniques, scheduling algorithms, and the determination of the energy break-even point are completed for the leakage reuse technique. The power delivery to sub-Vt circuits through leakage reuse reduces the total power consumption to 0.41x that of a conventional power delivery system when generating a supply voltage of 380 mV from the recycled leakage current of circuits operating at 1.2 V. Two scheduling algorithms are developed that allow for the simultaneous execution of power gating and leakage reuse and reduce the total power consumption by 50.2% as compared to a baseline topology that includes neither leakage reuse or power gating. In addition, techniques and methodologies are developed to recycle leakage energy from idle on-chip SRAM memories. Moreover, a novel multi-voltage domain heterogeneous accelerator architecture is developed for energy efficient execution of neural network models. A near-memory computing architecture is developed for the heterogeneous accelerator that leverages the leakage reuse technique applied to an SRAM memory array, where the leakage current of idle memory banks within each processing element is utilized to deliver current to the adjacently placed multiply-and-accumulate (MAC) units. The proposed heterogeneous architecture with leakage reuse results in an energy efficiency of 3.27 tera-operations per second per watt (TOPS/W) as compared to a conventional monolithic and single voltage domain architecture that exhibits an energy efficiency of 0.0458 TOPS/W.

Sleep switch dual threshold voltage domino logic with reduced subthreshold and gate oxide leakage current