Variable threshold voltage keeper for contention reduction in dynamic circuits

Sleep switch dual threshold voltage domino logic with reduced subthreshold and gate oxide leakage current

A low swing domino logic technique is proposed to decrease power consumption without sacrificing noise immunity. With the proposed low swing domino logic circuit technique, active power consumption is reduced by up to 9.4% while improving the noise immunity by 2.6% as compared to standard domino logic circuits. It is also shown that by applying a low swing contention reduction technique, the power savings can be further increased by 6.7% while the delay can be improved by 8.6%. A simple and efficient dual threshold voltage (dual-Vt) circuit technique that incorporates low swing signals is also proposed. It is shown that the proposed dual-Vt technique reduces the standby leakage current by approximately 235 times while offering enhanced delay characteristics as compared to a standard low threshold voltage implementation.

High performance circuits demands domino logic design. A new technique for reducing the power consumption and increasing the speed without effecting noise margin is reviewed in this paper. In this technique threshold voltage of the keeper transistor is varied using body bias generator circuit. Three different body bias generator circuits are simulated, they are dynamic body bias generator, capacitive body bias generator and cross couple capacitive body bias generator circuit. Simulations are performed on tanner EDA tool at 180 nm and 65nm technology, for carry look ahead adder. The simulation results show that CBBG and CCCBBG have reduced power consumption and delay in comparison to other circuit techniques.

As compared to static logic, domino logic circuits are always preferable for high performance circuit designs because of their less number of transistor requirement and high operational speed. Due to the presence of charge sharing problem and less noise tolerance this logic is not broadly accepted for all logic designs. The desired output of the circuit can change with a little noise pulse in the input of domino logic. Domino logic circuit has two stages first is dynamic logic part which is followed by a static inverter. This static inverter consumes very less power and has high noise immunity. In this paper a novel circuit called current mirror footed domino logic has been proposed for CMOS domino logic. This proposed domino logic is noise tolerant and has low power consumption than the basic footed and footless domino logic styles. Unity noise gain (UNG) found is also good for this logic style as compared to the previous proposed logic styles.

For the design and manufacture of complex integrated circuits, control over the threshold voltage of the transistors is essential. In the present contribution, we present a non-invasive method to tune the threshold voltage of organic thin-film transistors after device assembly over a wide range without any significant degradation of the device characteristics. This is realized by incorporating a thin, chemically reactive siloxane layer bonded to the gate oxide. This results in threshold voltages of around 70 V in the as-prepared devices. By exposing a transistor modified in this way to ammonia at different concentrations, the threshold voltage can be tuned in steps of only a few volts. This treatment affects only the charge density at the semiconductor–dielectric interface, leaving the overall shape of the transistor characteristics and the charge-carrier mobility largely unaltered.

Silicon-on-insulator (SOI) CMOS technology is a very attractive option for implementing digital integrated circuits for low power applications. This paper presents migration of standby subthreshold leakage control technique from a bulk CMOS to SOI CMOS technology. An improved SOI CMOS technology based circuit technique for effective reduction of standby subthreshold leakage power dissipation is proposed in this paper. The proposed technique is validated through design and simulation of a one-bit full adder circuit at a temperature of 27℃, supply voltage, VDD of 0.90 V in 120 nm SOI CMOS technology. Existing standby subthreshold leakage control techniques in CMOS bulk technology are compared with the proposed technique in SOI CMOS technology. Both the proposed and existing techniques are also implemented in SOI CMOS technology and compared. Reduction in standby subthreshold leakage power dissipation by reduction factors of 54x and 45x foraone-bit full adder circuit was achieved using our proposed SOI CMOS technology based circuit technique in comparison with existing techniques such as MTCMOS technique and SCCMOS technique respectively in CMOS bulk technology. Dynamic power dissipation was also reduced significantly by using this proposed SOI CMOS technology based circuit technique. Standby subthreshold leakage power dissipation and dynamic power dissipation were also reduced significantly using the proposed circuit technique in comparison with other existing techniques, when all circuit techniques were implemented in SOI CMOS technology. All simulations were performed using Microwindver 3.1 EDA tool.

The dynamic circuits are supposed to offer superior speed and low power dissipation over static CMOS circuits. The domino logic circuits are used for high system performance but suffer from the precharge pulse degradation. This article provides different design topologies on the domino circuits to overcome the charge sharing and charge leakage with reference to the power dissipation and delay. The precharge keeper circuit has been proposed such that the keeper transistors also work as the precharge transistors to realize multiple output function. The performance improvement of the circuit’s analysis have been done for adders and logic gates using HSPICE tool. The proposed keeper techniques reveal lower power dissipation and lesser delay over the standard keeper circuit with less transistor count for different process variation.

This paper presents an adaptive RF-DC power converter designed to efficiently convert RF signals to DC voltages utilizing auxiliary transistors to control the threshold voltage of the transistors in the main rectifier chain dynamically. The proposed circuit passively reduces the threshold voltage of the forward-biased transistors to increase the harvested power and the output voltage and increases the threshold voltage of the reverse-biased transistors to reduce the leakage current to prevent the loss of previously stored energy. A 12-stage adaptive threshold-compensated rectifier is designed and implemented in IBM's 0.13 $\mu{\rm m}$ CMOS technology. The proposed rectifier exhibits measured maximum power conversion efficiency (PCE) of 32% at $-$ 15 dBm (32 $\mu{\rm W}$ ) of input power while delivering 3.2 V to a 1 M $\Omega$ load. At a remarkably low input power of $-$ 20.5 dBm (8.9 $\mu{\rm W}$ ) for a 1 M $\Omega$ load, the rectifier produces an output voltage of 1 V.

Dual‐rail dynamic logic circuits can provide inverting and noninverting outputs, especially for asynchronous designs, to implement complicated gates at the cost of approximately doubling the area and power consumption. In this paper, a new dual‐rail dynamic circuit is proposed which has lower die area consumption and higher noise immunity without dramatic speed degradation for even wide fan‐in gates for asynchronous circuits. The main idea in the proposed circuit is that voltage due to the current of the pulldown network (PDN) is compared with the reference voltage to provide two complementary outputs. The reference voltage almost corresponds to the leakage current of the PDN with all transistors being off. The proposed circuit is compared with conventional dual‐rail circuits such as differential domino logic and differential cross‐coupled domino logic. Simulation results for 32‐bit‐wide OR gates designed using high‐performance 16‐nm predictive technology model demonstrate significant performance advantages such as 66% power reduction and at least 2.86× noise‐immunity improvement at the same delay compared to the differential domino circuits. © 2012 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.

As continue scaling down the transistor feature size subthreshold leakage current becomes major component of total power dissipation. This paper presents comparative analysis of different dynamic logic circuits for reducing subthreshold leakage current with improved performance in dynamic logic circuits. In this paper DOIND logic approach is proposed with and without body biasing of DOIND transistors for domino logic which reduces the leakage current with minimum delay penalty. Simulation is performed at 70 nm technology node for a different logic buffer using tanner EDA tool. Simulation results shows that reduction in leakage current by DOIND and reverse body biased (RBB) DOIND approaches are 89.72% and 89.35% respectively. Static power and energy for DOIND and RBB DOIND approaches are also improved by 45.46%, 37.07%, 45.28% and 8.66% respectively.

Comparison of floating probe transient technique for on-state channel characterization & threshold voltage of an organic thin film transistor for sensing applications

With the scaling of the CMOS technology, domino logic circuits experience larger leakage currents, which affect their robustness and performance. The leakage can be compensated by using a properly sized PMOS keeper transistor, at the cost of circuit delay increase. Hence, it is expected that the performance improvement of domino logic will stop in future technology nodes, due to increased required keeper size to maintain robustness. In this paper, we will study different methods of keeper sizing for comparing the performance of CMOS-OR domino logic circuits designed using Predictive Technology models of 32nm, 22nm and 16nm CMOS technology nodes. The keeper size will be adjusted to obtain the same robustness (noise immunity) across the technology generations. With this method of keeper sizing across technology nodes, the simulation results shows that indeed the delay of a low fan-in domino circuit increases from 32nm to 22nm node and the domino circuits fail to operate at 16nm node. For a high fan-in domino gate, however, the delay reduces from 32nm to 22nm; and the circuit fails at 16nm.

Wide fan-in dynamic logic OR gate has always been an integral part of high speed microprocessors. However, low noise immunity of wide fan-in dynamic logic gate is always an issue of concern. For maintaining high noise immunity, various large sized PMOS keeper-based dynamic OR gates are proposed in the literature. These designs allow large leakage through them for maintaining high noise immunity which unnecessarily increases the power dissipation. This can be a critical issue for microprocessors used in battery operated devices. Independent gate (IG) FinFET devices are known to reduce leakage current through them using back gate biasing technique. In this paper, a novel FinFET-based wide fan-in dynamic OR gate has been proposed with effective leakage control and high noise immunity. This work reports a maximum leakage power reduction up to 70% while maintaining up to 90% higher noise immunity as compared to standard dynamic OR gate at low keeper size. This work also mathematically illustrates the effective leakage reduction capability of FinFET as compared to CMOS and hence proves its preference over CMOS in wide fan-in dynamic OR gate.

We fabricated novel dual in-plane-gate electric-double-layer (EDL) SnO2 nanowire transistors gated by chitosan using only one transmission electron microscopy (TEM) nickel grid mask at room temperature, and we successfully controlled its threshold voltage. By changing the second in-plane gate bias from 1.0 to −1.0 V, we tuned the threshold voltage of these transistors from −0.35 to 0.21 V. Their operation voltage was 1.0 V, because the EDL gate dielectric can lead to high gate dielectric capacitance (4.24 µF/cm2). These dual in-plane-gate nanowire transistors could pave the way to useful low-voltage nanoelectronic devices.

The usage of noise-sensitive dynamic circuits has become commonplace due to speed and area requirements, making the noise issue even more prominent. This paper focuses on the trends of coupling and its effects on dynamic circuits. It presents closed form analytical solutions for noise, as well as noise tolerance metrics for dynamic circuits. These solutions are within 5% of dynamic simulations. It is shown that not all scaling trends are negative for noise, and that the scaling down of supply voltage and increasing frequency, help improve certain aspects of the noise immunity of dynamic circuits. Most of the works treated the noise immunity and the noise content separately. This paper introduces an analysis of noise scalability by looking at the noise immunity and the noise content simultaneously