Realistic scalability of noise in dynamic circuits

Noise has become an important metric of deep submicron digital integrated circuit performance, and is becoming even more prominent due to the increasing usage of noise sensitive dynamic circuits for speed and area requirements. This paper presents closed form analytical solutions for noise as well as noise tolerance metrics for dynamic circuits to analyze the effects of coupling, which is considered as the dominant source of noise. These solutions are within 5% of dynamic simulations. It is shown that not all the scaling trends are negative for noise, and that the scaling down of supply voltage and increasing frequency help improve certain aspects of the noise immunity of dynamic circuit. Most of the work treated noise immunity and the noise content separately. This paper introduces a positive analysis of noise scalability by looking at the noise immunity and the noise content simultaneously.

Dual‐rail dynamic logic circuits can provide inverting and noninverting outputs, especially for asynchronous designs, to implement complicated gates at the cost of approximately doubling the area and power consumption. In this paper, a new dual‐rail dynamic circuit is proposed which has lower die area consumption and higher noise immunity without dramatic speed degradation for even wide fan‐in gates for asynchronous circuits. The main idea in the proposed circuit is that voltage due to the current of the pulldown network (PDN) is compared with the reference voltage to provide two complementary outputs. The reference voltage almost corresponds to the leakage current of the PDN with all transistors being off. The proposed circuit is compared with conventional dual‐rail circuits such as differential domino logic and differential cross‐coupled domino logic. Simulation results for 32‐bit‐wide OR gates designed using high‐performance 16‐nm predictive technology model demonstrate significant performance advantages such as 66% power reduction and at least 2.86× noise‐immunity improvement at the same delay compared to the differential domino circuits. © 2012 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.

Dynamic CMOS logic circuits are used in modern VLSI circuits because of its high system performance and its performance is high due to higher speed over static CMOS circuit. However dynamic logic circuit has less noise immunity and increased leakage power dissipation. Increase in leakage current combine with reduced noise margin results in performance degradation of dynamic circuits. In this paper DOIND logic approach is proposed for domino logic which reduces the leakage current with minimum delay penalty. Simulation is performed at 70 nm technology node for a domino logic and DOIND logic buffer using tanner EDA tool. Simulation results shows that proposed DOIND approach decreases the leakage current 93.3%, static power 93.3% and static energy 86.66% at supply voltage 1.15V. Proposed circuit also improves dynamic power 60.78%, dynamic energy delay product (EDP) 62.18% and dynamic power delay product (PDP) 62.07% at 1.15V supply voltage.

Recent trends in CMOS technology and scaling of devices clearly indicate that leakage power in digital circuits would be crucial and largely depend on the sub-threshold currents. Minimizing leakage, by power gating logic circuits using sleep transistors gives considerable power savings. However, this technique cannot be used in sequential circuits and memory cells, as it would result in loss of stored data. In this paper, we propose a novel circuit by applying a self-bias transistor (SBT) to minimize sub-threshold leakage currents in static and dynamic circuits. This circuit with SBTs, acts as a smart switch by virtually power gating either pull-up or pull-down logic, and causes a considerable reduction in leakage currents in both active and standby modes. A benchmark is simulated with 0.18 /spl mu/m CMOS technology in the Cadence Spectre circuit simulator. Results show significant reduction in leakage power, of up to 50% on average, for all possible states simulated in static and dynamic circuits by applying this proposed self-bias transistor.

Power and area will remain the main constraints in the designing of VLSI circuits. Dynamic CMOS logic circuits are broadly designed for high performance circuits due to their high speed. Conversely, the demerit of dynamic logic style is its high noise sensitivity and during cascading several problems like charge sharing and charge degradation arises. The main cause of this is the sub-threshold leakage current flowing through the pull down network and with continuous technology scaling, this problem is getting more and more severe. Compared to static CMOS circuits which have larger capacitance and offers more delay, Dynamic circuits are used to improve those parameters of design. In this paper we have proposed a new circuit in order to improve the power consumption by applying a multi-threshold technique. Simulations are done in Cadence for 90nm with IBM technology for OR gates with supply voltage of 1v.

A variable threshold voltage keeper circuit technique is proposed for simultaneous power reduction and speed enhancement of domino logic circuits. The threshold voltage of the keeper transistor is dynamically modified during circuit operation to reduce the contention current without sacrificing noise immunity. A four-bit multiple-output domino carry generator for a carry lookahead adder is designed with the proposed circuit technique. It is shown that the variable threshold voltage keeper circuit technique enhances the circuit evaluation speed by up to 60% while reducing power dissipation by 37% as compared to a standard domino logic circuit. It is also shown that the proposed domino logic circuit technique offers 20% higher noise immunity as compared to a standard domino circuit with the same evaluation delay characteristics.

New dynamic logic style for energy efficient tag comparators

Over the coming decade, advanced packaging will become increasingly critical to performance, cost, and density improvements in advanced electronics. There is both an industry push: cost and performance advances in transistor scaling are increasingly difficult. And there is an industry pull: customization for each market can be done far more quickly by assembling a series of parts in a package, rather than by design and integration into a single device. This isnt a new idea: Gordon Moore said “ It may prove to be more economical to build large systems out of smaller functions, which are separately packaged and interconnected. ” In the early years, this integration happened at the system level: GPU cards, sound cards, match coprocessors, and communication devices. In the 2000’s, this switched to integration of major components on die. And now, the same concept returns in integration on the local interconnect level. Manufacturing will necessarily advance in the packaging arena: pin density and package size will both increase to support the high bandwidth and device integration demands. Local bandwidth has expanded by 10x, which gives rise to 10x higher pincounts. Similarly, lower latency requirements require small, low delay interconnects. The downside of multiple device integration is a higher set of requirements on the reliability of both the individual devices and the fully assembled system. This is an opportunity to take advantage of new strategies and technologies in package inspection. The sampling challenges for both control and inspection for high reliability require systems that can run at 100% coverage and millions of units per year at (tens of) thousands of bumps per device. An overview of reliability sampling challenges as it relates to the end of line inspection, as well as sampling for both defect type and incidence is critical to understanding how and what to measure to maximize yield. There are fundamental tradeoffs between speed, resolution, and signal to noise ratio that inform a systematic engineering understanding of inspection. Optimizing that trade-off specifically for semiconductor inspection leads to dedicated tools with extremely high resolution, speed, and low dose. This does require rethinking some basic assumptions in the design of semiconductor inspection systems. To take advantage of this speed, fully automated systems are needed to identify and classify defects found at th bump level. In parallel with the speed requirements, sensitivity, and noise immunity can be improved with an understanding of the systematic sources of noise. These can be mitigated and even eliminated with novel algorithms for both image enhancement and defect location.

Over the coming decade, advanced packaging will become increasingly critical to performance, cost, and density improvements in advanced electronics. There is both an industry push: cost and performance advances in transistor scaling are increasingly difficult. And there is an industry pull: customization for each market can be done far more quickly by assembling a series of parts in a package, rather than by design and integration into a single device. This isnt a new idea: Gordon Moore said the same in the 60’s. But after decades of increased device level integration, it is an important change. Figure 1 shows an example (future) device: there are large bumps, hybrid bonds--for extreme bandwidth and low latency connection to cache memory, TSV based DRAM, and multiple CPU to CPU interconnects. Each of these is a failure point. Figure 1: The wide variety of interconnects on future advanced packages Figure 2: the triangle of misery as applied to standard and Advanced xray imaging (AXI) Manufacturing will necessarily advance in the packaging arena: pin density and package size will both increase to support the high bandwidth and device integration demands. The downside of multiple device integration is a higher set of requirements on the reliability of both the individual devices and the fully assembled system. This is an opportunity to take advantage of new strategies and technologies in package inspection. The sampling challenges for both control and inspection for high reliability require systems that can run at 100% coverage and millions of units per year. An overview of reliability sampling challenges as it relates to the end of line inspection, as well as sampling for both defect type and incidence is critical to understanding how and what to measure to maximize yield. There are fundamental tradeoffs between speed, resolution, and signal to noise ratio that inform a systematic engineering understanding of inspection. Optimizing that trade-off specifically for semiconductor inspection leads to dedicated tools with extremely high resolution, speed, and low dose. In parallel with the speed requirements, sensitivity, and noise immunity can be improved with an understanding of the systematic sources of noise. These can be mitigated and even eliminated with novel algorithms for both image enhancement and defect location.

Dual threshold voltage (Vt) technique is applied widely in dynamic OR circuits to achieve low leakage in register files (RF) design, but its effectiveness is significantly influenced by the selected sleep vector during the standby mode. As technology scales into deep nanometer era, the sleep vector selection in dual Vt dynamic OR (DV-OR) circuits becomes challenging due to the impact of PVT (process, supply voltage and temperature) variations. In this paper, we analyze the relationship among PVT variations, leakage characteristics, and sleep vectors in DV-OR circuits. We further perform a comprehensive study on sleep vector selection and explore its design space in DV-OR circuits. Finally, we present a generalization of our analysis for multiple Vt dynamic OR circuits and provide sleep vector selection guidelines to achieve low leakage and robust register files in modern processors.

This paper presents a detailed study on the impact of floating body in partially-depleted (PD) SOI MOSFET on various digital VLSI CMOS circuit families. The parasitic bipolar effect resulting from the floating body is shown to degrade the circuit noise margin and stability in general. In certain dynamic circuits and wide multiplexers, the parasitic bipolar effect is shown to cause logic state error if not properly accounted for.

A new level shift circuit featuring with capacitive load instead of resistive load is proposed and investigated in this paper. The proposed design can help the high voltage gate drive integrated circuit (HVIC) to achieve the high d Vs/dt noise immunity up to 85 V/ns and the allowable negative V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</sub> swing to -12 V at 15 V supply voltage. The temperature characteristic of the above reliability items of the HVIC with the proposed capacitive-loaded level shift (CLLS) circuit are investigated for the first time and are an improvement when compared to those of the conventional resistive-loaded level shift circuit, which is verified by numerous theoretic analyses and experiments. Moreover, although four high voltage lateral double-diffused metal-oxide-semiconductor transistors are used in the proposed CLLS circuit, no extra chip size is needed due to the fact that the transistors can be embedded in the high voltage isolation structure base on 0.5 μm Bipolar-CMOS-DMOS technology.

The paper is devoted to the application of mathematical modeling of dynamic circuits with a nonlinear transformer. The analytical solution of such a task is accompanied by complex mathematical calculations. In this case, the simulation of the electrical circuit allows to simplify the analysis procedure, reduce the calculation time, visualize schedules and considering alternative conditions for a task. The simulation is carried out with the help of the Simscape library in the MatLab system.

The increasing impact of noise in deep submicron designs combined with a need for high performance circuits warrants development of noise tolerant dynamic circuits. A circuit technique for addressing this problem is presented in this paper. Traditionally, an output controlled refresh has been used for providing noise immunity to the dynamic node. An input controlled refresh technique has been developed for noise-free performance with minimal impact on delay and power. Also this technique eliminates functional failure that occurs due to charge loss from the dynamic node. A metric, Unity Noise Gain (UNG) has been used to compare the proposed method with the existing approaches. Simulations show a significant improvement is noise immunity, for a NAND gate and an adder circuit.

Summary form only given. Scaling down of device sizes and supply voltage requires a commensurate scaling of transistor threshold voltage to maintain high performance. Such scaling leads to exponential increase in leakage current, decreased noise immunity for high speed circuits, and increased defects. In this tutorial we present design and test techniques to combat these problems in the deep sub-micron regime for bulk, SOI and future technologies. We consider the following issues in turn: 1. Device scaling and its impact on sub-threshold and gate leakage current, interconnects, and noise immunity. 2. Low voltage circuit design under high intrinsic leakage, leakage monitoring and control techniques, effective transistor stacking, multi-threshold CMOS, dynamic threshold CMOS, SOI implications. Design of low leakage data-paths and caches. 3. SOI design - comparison with bulk, logic and memory design, asynchronous design. 4. Copper, low k, and impact of low k on performance. 5. Future technologies - double gate fully depleted SOI, FIN FET, and 3D SOI. 6. Noise modeling and analysis for high-speed precharge-evaluate circuits such as domino. Noise tolerant circuit design styles - skewed CMOS, noise tolerant domino, layout styles for high noise immunity. 7. I/sub ddq/ testing of circuits with high intrinsic leakage /sub e/lta I/sub ddq/, two parameter tests. I/sub dd/ waveform analysis.