Optimizing X-Ray Inspection for Advanced Packaging Applications

Over the coming decade, advanced packaging will become increasingly critical to performance, cost, and density improvements in advanced electronics. There is both an industry push: cost and performance advances in transistor scaling are increasingly difficult. And there is an industry pull: customization for each market can be done far more quickly by assembling a series of parts in a package, rather than by design and integration into a single device. This isnt a new idea: Gordon Moore said “ It may prove to be more economical to build large systems out of smaller functions, which are separately packaged and interconnected. ” In the early years, this integration happened at the system level: GPU cards, sound cards, match coprocessors, and communication devices. In the 2000’s, this switched to integration of major components on die. And now, the same concept returns in integration on the local interconnect level. Manufacturing will necessarily advance in the packaging arena: pin density and package size will both increase to support the high bandwidth and device integration demands. Local bandwidth has expanded by 10x, which gives rise to 10x higher pincounts. Similarly, lower latency requirements require small, low delay interconnects. The downside of multiple device integration is a higher set of requirements on the reliability of both the individual devices and the fully assembled system. This is an opportunity to take advantage of new strategies and technologies in package inspection. The sampling challenges for both control and inspection for high reliability require systems that can run at 100% coverage and millions of units per year at (tens of) thousands of bumps per device. An overview of reliability sampling challenges as it relates to the end of line inspection, as well as sampling for both defect type and incidence is critical to understanding how and what to measure to maximize yield. There are fundamental tradeoffs between speed, resolution, and signal to noise ratio that inform a systematic engineering understanding of inspection. Optimizing that trade-off specifically for semiconductor inspection leads to dedicated tools with extremely high resolution, speed, and low dose. This does require rethinking some basic assumptions in the design of semiconductor inspection systems. To take advantage of this speed, fully automated systems are needed to identify and classify defects found at th bump level. In parallel with the speed requirements, sensitivity, and noise immunity can be improved with an understanding of the systematic sources of noise. These can be mitigated and even eliminated with novel algorithms for both image enhancement and defect location.

The demands for increased data transmission rates and bandwidth as well as reduced signal loss are increasing while package size is getting bigger. To accommodate increasing package size and manage high frequency loss and warpage management, Glass substrates in advanced packaging are gaining momentum for heterogeneous integration of advanced semiconductor packaging. Based on Yole report in 2020, a 2.5-3 fold increase from 2019 to 2025 for the glass substrates is predicted. Glass core and Glass interposer could become a leading processing technology in advanced Panel Level Packaging (PLP). Cost effectiveness and high-frequency characteristics of glass laid strong pathways for Advanced Packaging Roadmaps. However, insertion of glass poses several challenges such as CD uniformity of Through Glass Via (TGV) etch over different aspect ratio of via sizes. Also due to the CTE mismatch between glass and metal, adhesion and stress management appears to be a huge issue for integration of TGV metallization and RDL layers. This paper presents the detail of TGV etch process with respect to different glass types, laser modification methods, and aspect ratio. Etching characterization over bath life as well as with various Design of Experiments (DOE) was performed to address the HVM challenges. Fabrication of TGV and metallization requires a good buffer layer (BL) on glass vias followed by Eless Cu deposition. Based on the types and properties of buffer layer, buffer layer serves the purpose of adhesion promotion liner (APL) as well as stress buffer layer (SBL). Additionally, Electrode less (Eless) Cu would be beneficial to provide as seed layer for conformal or full TGV metallization. Hence, a closer look into the development of Through Glass Via (TGV) processing, Adhesion promotion layer (APL), and Eless Cu techniques are discussed in this paper. A Wet process system has been developed to enable the TGV processing, Adhesion promotion, and Eless Cu for different types of glass substrates. Cross sectional and chemical analyses were done to validate the studies and the data were used to develop the glass etching, APL/SBL, and Eless Cu. Simulation and experimental data indicates that this approach is feasible to address glass processing and stress management challenges.

Advanced packaging technology has become more and more important in the semiconductor industry because of the benefits of higher I/O density compared to conventional soldering technology. In advanced packaging technology, copper–copper (Cu-Cu) bonding has become the preferred choice due to its excellent electrical and thermal properties. However, one of the major challenges of Cu-Cu bonding is the high thermal budget of the bonding process caused by Cu oxidation, which can result in wafer warpage and other back-end-of-line process issues in some cases. Thus, for specific applications, reducing the thermal budget and preventing Cu oxidation are important considerations in low-temperature hybrid bonding processes. This paper first reviews the advancements in low-temperature Cu-based bonding technologies for advanced packaging. Various low-temperature Cu-Cu bonding techniques such as surface pretreatment, surface activation, structure modification, and orientation control have been proposed and investigated. To overcome coplanarity issues of Cu pillars and insufficient gaps for filling, low-temperature Cu-Cu bonding used, but it is still challenging in fine-pitch applications. Therefore, low-temperature Cu/SiO2, Cu/SiCN, and Cu/polymer hybrid bonding have been developed for advanced packaging applications. Furthermore, we present a novel hybrid bonding scheme for metal/polymer interfaces that achieves good flatness and an excellent bonding interface without the need for the chemical mechanical polishing (CMP) process.

Current DRAM advanced chip stack packages such as the high bandwidth memory (HBM) use throughsilicon-via (TSV) and thermal compression bonding (TCB) of solder capped micro bumps for the inter-layer connection. The bonding process has low throughput and cannot overcome the challenge of scaling below 40 μm pitch. These are compelling reasons to seek an alternative approach such as hybrid bonding. The pursuit of fine pitch die stacking with TSV interconnect using hybrid bonding is pervasive in the packaging industry today due to the promise of improved performance. Specifically, the Cu interconnect provides improved thermal and electrical performance and the all inorganic interface of the complete die stack offers enhanced thermal-mechanical performance and reliability in the final chip stack. Direct Bond Interconnect technology, also known as low temperature hybrid bonding, forms a spontaneous dielectric-to-dielectric bond at room temperature and then establishes metal-to-metal connection (usually Cu-to-Cu bond) by a low temperature batch annealing process (150 - 300°C). The direct bond process eliminates the need for solder and underfill and associated problems. While the hybrid bonding exists today in wafer-towafer (W2W) format in high volume manufacturing, chip to wafer (C2W) bonding developed for future product lines is making significant process in the past three years. A bonding process with high throughput has been demonstrated with electrical test yield above 90% with a daisy chain structure that covers 50mm^2 of bonding area. The bonded parts showed superior reliability performance in temperature cycling, high temperature storage and autoclave testing. This paper presents the latest development in C2W hybrid bonding and demonstrates the low temperature annealing capability and integration with TSV

Hybrid bonding technology has emerged as a critical 3D integration solution for advanced semiconductor packaging, enabling simultaneous bonding of metal interconnects and dielectric materials. However, conventional hybrid bonding processes face significant contamination challenges during O2 plasma treatment required for OH group formation on SiCN or the other dielectric material surfaces. The aggressive plasma conditions cause Cu sputtering and metal migration, leading to chamber and substrate contamination that accumulates over time and degrades process reliability. In this work, we present a novel approach to address these contamination issues by implementing a molybdenum disulfide (MoS2) barrier layer formed through plasma-enhanced chemical vapor deposition (PECVD) sulfurization of Mo films. The ultrathin MoS2 layer acts as an effective barrier preventing Cu sputtering during O2 plasma processing, thereby eliminating chamber contamination, and it also enables post-bonding electrical connectivity through controlled Cu filament formation via memristive switching mechanisms. When voltage is applied to the Cu-MoS2-Cu structure after hybrid bonding, Cu ions migrate through the MoS2 layer to form conductive filaments, establishing reliable electrical connections without compromising the bonding interface integrity. This innovative approach successfully resolves the fundamental contamination problem in hybrid bonding while maintaining excellent electrical performance, offering a pathway toward contamination-free and high-yield hybrid bonding processes for next-generation 3D-integrated devices.

Failure analysis (FA) of advanced semiconductor packages is becoming increasingly challenging due to shrinking feature sizes in advanced packaging and 3D stacking. Existing techniques often fail to balance high spatial resolution with the need to analyze large planar samples, such as advanced packages, chiplets, CoWoS, PCBs, 300 mm wafers and at a reasonable speed. This paper introduces a novel imaging tool that integrates high-resolution 3D X-ray or XRM (X-ray Microscopy) with advanced laminography, achieving a spatial resolution of 350 nm, with 3D acquisition time in minutes. By combining innovative laminography into a traditional CT (computed tomography) architecture, the system overcomes the geometric distortions and resolution limitations of conventional laminography. This versatile tool enables high-resolution package inspection to rapid board-level FA, with occasional wafer inspection, streamlining workflows in modern semiconductor <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{F A}$</tex> labs without requiring multiple X-ray systems. Case studies illustrate its efficiency and precision in real-world applications

To enable higher computing power in a single chip, there is demand for increasing die and substrate size for high performance applications in advanced nodes. Chip package interaction (CPI) performance is very critical for package reliability, specifically for advanced low-k 5nm, 3nm technology node chips including extreme low-k (ELK) and low-k (LK) dielectric materials. The material property coefficient of thermal expansion (CTE) mismatch between dielectric materials, copper, silicon can induce significant stresses, causing ELK-LK cracking or delamination and chip failure in electronic packages. For advanced semiconductor nodes like 5nm and 3nm, the Back End of Line (BEOL) structure mechanical strength is reduced due to the presence of porous material with low-dielectric constant which makes it more prone to thermal mechanical failures. On the other hand, use of stiff first level interconnect (copper pillars) together with large die, and package size causes an increased level of stress transfer from package to chip. For these reasons, die BEOL cracking or delamination due to Chip Package Interaction (CPI) is becoming more and more critical in advanced nodes and therefore necessary design optimizations should be done during initial package design phase to avoid any CPI related cracking or delamination failures in package. This study investigates in detail the impact of copper pillar design parameters such as copper pillar height, under bump metallization (UBM) diameter, copper pillar plating chemistry on die cracking or delamination within die BEOL structure. Novel fracture mechanics and stress-based with detail BEOL structure multi-level finite element analysis (FEA) simulation methodology based on the energy release rate (ERR) driving delamination using J-integral approach is developed to assess impact of various package parameters on cracking or delamination in die BEOL layer and used to assess die ELK cracking risk for advanced 5nm packages. Energy release rate (ERR) is the change in the elastic strain energy with respect to change in crack area. Critical ERR (ERRc) is material property also known as fracture toughness and it is used to estimate if the crack will propagate or not (crack will propagate if, ERR ≥ ERRc). This work is expected to provide design guidelines for package designers and help to optimize copper pillar structure for advanced 5nm packages.

A rapid, dependable method of on-line package inspection will allow wider implementation of energy- and material-efficient retortable pouches and trays, by reducing inspection costs. To evaluate high-frequency ultrasonic imaging as a sensing method, the 17·3 MHz ultrasonic pulse-echo Backscattered Amplitude Integral (BAI) method was used to visualize and evaluate major defects (channels and product inclusions, which compromise the seal integrity and must be reliably inspected) in the seal area of flexible food packages. The focus of this study was to evaluate the image contrast, denoted ΔBAI, for various packaging materials, defect types and sizes. Channel (6–100 µm in diameter) and inclusion defects (strands of mouse tail tendons, 20–150 µm) were created in the seal area of all-plastic and foil-containing packaging films. It has been shown that there is a direct relationship between the defect size and ΔBAI value, and that different defect types and packaging materials have a significant impact on the ΔBAI value. The utility of ΔBAI for detecting defects makes it a useful and reliable sensing method for package inspection. Copyright © 1999 John Wiley & Sons, Ltd.

We report a new wafer-level packaging technology for miniature MEMS in a hermetic micro-environment. The unique and new feature of this technology is that it only uses low cost wafer-level processes such as eutectic bonding, Bosch etching and mechanical lapping and thinning steps as compared to more expensive process steps that will be required in other alternative wafer-level technologies involving thru-silicon vias or membrane lids. We have demonstrated this technology by packaging silicon-based AlN microsensors in packages of size 1.3 × 1.3 mm2 and 200 micrometer thick. Our initial cost analysis has shown that when mass produced with high yields, this device will cost $0.10 to $0.90. The technology involves first preparing the lid and MEMS wafers separately with the sealring metal stack of Ti/Pt/Au on the MEMS wafers and Ti/Pt/Au/Ge/Au on the lid wafers. On the MEMS wafers, the Signal/Power/Ground interconnections to the wire-bond pads are isolated from the sealring metallization by an insulating AlN layer. Prior to bonding, the lid wafers were Bosch-etched in the wirebond pad area by 120 um and in the center hermetic device cavity area by 20 um. The MEMS and the lid wafers were then aligned and bonded in vacuum or in a nitrogen environment at or above the Au-Ge Eutectic temperature, 363°C. The bonded wafers were then thinned and polished first on the MEMS side and then on the lid side. The MEMS side was thinned to 100 ums with a nearly scratch-free and crack-free surface. The lid side was similarly thinned to 100 ums exposing the wire-bond pads. After thinning, a 100 um thick lid remained over the MEMS features providing a 20 um high hermetic micro-environment. Thinned MEMS/Lid wafer-level assemblies were then sawed into individual devices. These devices can be integrated into the next-level assembly either by wire-bonding or by surface mounting. The wafer-level packaging approach developed in this project demonstrated RF Feedthroughs with 50% hermetic yields.

The usage of noise-sensitive dynamic circuits has become commonplace due to speed and area requirements, making the noise issue even more prominent. This paper focuses on the trends of coupling and its effects on dynamic circuits. It presents closed form analytical solutions for noise, as well as noise tolerance metrics for dynamic circuits. These solutions are within 5% of dynamic simulations. It is shown that not all scaling trends are negative for noise, and that the scaling down of supply voltage and increasing frequency, help improve certain aspects of the noise immunity of dynamic circuits. Most of the works treated the noise immunity and the noise content separately. This paper introduces an analysis of noise scalability by looking at the noise immunity and the noise content simultaneously

Noise has become an important metric of deep submicron digital integrated circuit performance, and is becoming even more prominent due to the increasing usage of noise sensitive dynamic circuits for speed and area requirements. This paper presents closed form analytical solutions for noise as well as noise tolerance metrics for dynamic circuits to analyze the effects of coupling, which is considered as the dominant source of noise. These solutions are within 5% of dynamic simulations. It is shown that not all the scaling trends are negative for noise, and that the scaling down of supply voltage and increasing frequency help improve certain aspects of the noise immunity of dynamic circuit. Most of the work treated noise immunity and the noise content separately. This paper introduces a positive analysis of noise scalability by looking at the noise immunity and the noise content simultaneously.

With reducing of silicon techno, the pitches and pads at the chip to package interface become important factor. This drives interconnection toward to fan-out packaging, where the package size is larger than the chip size in order to provide a sufficient area to accommodate the 2nd level interconnects. Fan-out WLP has the potential to realize any number of interconnects at any shrink stage of the wafer node technology.

Advanced electronics technology is moving towards smaller footprints and higher computational power. In order to achieve this, advanced packaging techniques are currently being considered, including organic, glass, and semiconductor-based substrates that allow for 2.5D or 3D integration of chips and devices. Metal-core substrates are a new alternative with similar properties to those of semiconductor-based substrates but with the added benefits of higher flexibility and metal ductility. This work comprehensively compares the thermal properties of a novel metal-based substrate, molybdenum, and silicon and fused silica glass substrates in the context of system-on-foil (SoF) integration. A simple electronic technique is used to simulate the heat generated by a typical CPU and to measure the heat dissipation properties of the substrates. The results indicate that molybdenum and silicon are able to effectively dissipate a continuous power density of 2.3 W/mm2 as the surface temperature only increases by ~15 °C. In contrast, the surface temperature of fused silica glass substrates increases by &gt;140 °C for the same applied power. These simple techniques and measurements were validated with infrared camera measurements as well as through finite element analysis via COMSOL simulation. The results validate the use of molybdenum as an advanced packaging substrate and can be used to characterize new substrates and approaches for advanced packaging.

The tremendous growth in smartphones and tablets has been fueled by consumer demand for increased mobility, functionality, and ease of use. This, in turn, has been driving an increase in functional convergence and 3D integration of integrated circuit (IC) devices, resulting in the need for more advanced and sophisticated packaging techniques. In particular, the integration of the application processor (AP) and dedicated memory has become increasingly complex. Smartphones and tablets have become virtual streaming devices requiring low power, high bandwidth memory (HBM). For quality, high-speed video and multi-tasking applications, the memory interface to the AP must have superior signal integrity to minimize crosstalk and insertion/return losses. In addition, the thermal management of the processor must allow the maximum clock speed and duty cycle for high-performance applications. Finally, to conserve battery life for the mobility device, the power distribution to the processor must be as efficient as possible. This creates a significant challenge for the semiconductor packaging industry to meet these demanding requirements for smartphone and tablet products. This paper introduces a leading-edge high-density fan-out (HD-FO) semiconductor packaging technology that addresses the need for higher levels of integration and improved electrical and thermal performance for mobile applications. This new innovative technique, called Silicon Wafer Integrated Fan-out Technology (SWIFT™) packaging, leverages the fine feature size and thin-film circuit patterning capabilities of wafer-level packaging. In addition, thin-film dielectric photolithography and pattern plating provides a significant reduction in package z-height, which is critical for advanced mobile devices. By incorporating a redistribution layer (RDL)-first/chip-last process flow, there is also an opportunity for yield optimization and cycle-time reduction. This work compares the electrical and thermal modeling results between a conventional Package-on-Package (PoP) and HD-FO SWIFT devices. The results reveal a highly integrated PoP structure with exceptional electrical, mechanical, and thermal performance benefits – compared to conventional organic laminate-based technologies – to meet the growing need for high-performance mobile applications.

This paper presents the recent advances in the development of a laser assisted fast polymer bonding method for electronic packaging applications. In this method a high power diode laser is used to cure a polymer adhesive material to bond substrates together. A unique beam forming method using custom designed optical phase plate elements was developed to transform a fiber delivered laser beam into top-hat and frame shaped beam profiles for energy efficient polymer bonding for electronics manufacturing. In addition it has been found that the frame shaped beam profile can produce a desirable temperature distribution for MEMS packaging in which the surface temperature at the center of the substrate is lower by ~50°C than the packaging temperature (~300°C) when bonding a glass cap to a silicon substrate. An accurate temperature monitoring method using an embedded thin film microsensor array has been developed and has been used successfully for process monitoring. Defect-free fast bonding (~10 seconds) of transparent cap (glass) and non-transparent cap (silicon) to a silicon chip has been demonstrated. This work illustrates the potential of the diode laser based photonic technology for advanced MEMS packaging and electronics manufacturing.