Input controlled refresh for noise tolerant dynamic circuits

In this paper, a new circuit is proposed for enhancing the performance of the wide fan-in OR footless domino circuits in terms of noise immunity and speed. The proposed circuit is the modification of standard footless domino circuit by an adding keeper controlling network between the gate of the keeper transistor and the dynamic node. The keeper controlling network consists of a PMOS transistor, a diode and delay elements to control the keeper transistor. At the beginnings of evaluation phase for either low or high inputs, the keeper controlling network turns OFF the keeper transistor, which increases the circuit speed. In the same condition (when clock is high), if all the inputs of the pull down network are low then the noise immunity of the circuit gets increased. The proposed circuit and the other previously existing circuits are demonstrated through simulations using 90-nm CMOS technology for 4, 8, 16 and 32 inputs OR gate. The simulation results for 32 inputs OR gate show that the proposed circuit reduces the power consumption, delay, and power delay product by 31.42, 0.69, and 31.91%, and the noise immunity is increased by 0.23% as compared to the HS-domino circuit.

As compared to static logic, domino logic circuits are always preferable for high performance circuit designs because of their less number of transistor requirement and high operational speed. Due to the presence of charge sharing problem and less noise tolerance this logic is not broadly accepted for all logic designs. The desired output of the circuit can change with a little noise pulse in the input of domino logic. Domino logic circuit has two stages first is dynamic logic part which is followed by a static inverter. This static inverter consumes very less power and has high noise immunity. In this paper a novel circuit called current mirror footed domino logic has been proposed for CMOS domino logic. This proposed domino logic is noise tolerant and has low power consumption than the basic footed and footless domino logic styles. Unity noise gain (UNG) found is also good for this logic style as compared to the previous proposed logic styles.

In this work low leakage and high noise immunity domino circuit with negligible speed degradation is proposed. Wide Fan-In Gates are widely used as address decoders in memories. Wide Fan-In Gates increase the capacitance of the dynamic node which reduces the speed in domino circuits. Current contention exists between keeper transistor and evaluation network adding to speed reduction. To overcome this problem logic implementation network in the proposed Leakage Compensating Keeper (LCK) is separated from the dynamic node by current comparison stage in which the current of the pull up network is used to charge the capacitor at the dynamic node. Since capacitance is reduced the loss in speed due to additional transistors is compensated. Because of reduced parasitic capacitance Current Mirror based LCK is enough to design faster circuits. LCK improves the noise immunity by grounding the pull up networks leakage current. Simulation results shows that the proposed circuit has 22% power reduction compared to Standard Footless Domino for a 64bit input OR gate.

New dynamic logic style for energy efficient tag comparators

The development and application of CMOS VLSI semiconductor circuits employing sub-micron technology has faced significant challenges, specifically related to issues of latency and power usage. This paper presents the HSSODL technique, a novel approach for designing CMOS logic gates that minimize leakage current. The goal of this methodology has been to minimize energy consumption due to leakage while also improving digital circuit efficiency in terms of distortion. The suggested technique is utilized to create 16-bit OR gates, which are then simulated with Cadence's CMOS 45nm technology. The simulation results were evaluated by comparing Unity Noise Gain (UNG), power utilization, and latency. The findings from the simulation demonstrate that the suggested domino logic technique decreases the latency by a minimum of 35%. Overall, power usage and energy dissipation are lower than in contemporary domino logic techniques.

In modern CMOS digital design, the noise immunity has come to have an almost equal importance to the power consumption. In the last decade, many low power design schemes have been presented. However, no one can simply judge which one is the best from the noise immunity point of view. In this paper, we investigate the noise immunity of the static CMOS low power design schemes in terms of logic and delay errors caused by different kinds of noise existing in the static CMOS digital circuits. To fulfill the aims of the paper, first a model representing the different sources of noise in deep submicron design is presented. Then the model is applied to the most famous low power design schemes to find out the most robust one with regard to noise. Our results show the advantages of the dual threshold voltage scheme over other schemes from the noise immunity point of view. Moreover, it indicates that noise should be carefully taken into account when designing low power circuits; otherwise circuit performance would be unexpected. The study is carried out on three circuits; each is designed in five different schemes. The analysis is done using HSPICE, assuming 0.18 μm CMOS technology.

The usage of noise-sensitive dynamic circuits has become commonplace due to speed and area requirements, making the noise issue even more prominent. This paper focuses on the trends of coupling and its effects on dynamic circuits. It presents closed form analytical solutions for noise, as well as noise tolerance metrics for dynamic circuits. These solutions are within 5% of dynamic simulations. It is shown that not all scaling trends are negative for noise, and that the scaling down of supply voltage and increasing frequency, help improve certain aspects of the noise immunity of dynamic circuits. Most of the works treated the noise immunity and the noise content separately. This paper introduces an analysis of noise scalability by looking at the noise immunity and the noise content simultaneously

Noise has become an important metric of deep submicron digital integrated circuit performance, and is becoming even more prominent due to the increasing usage of noise sensitive dynamic circuits for speed and area requirements. This paper presents closed form analytical solutions for noise as well as noise tolerance metrics for dynamic circuits to analyze the effects of coupling, which is considered as the dominant source of noise. These solutions are within 5% of dynamic simulations. It is shown that not all the scaling trends are negative for noise, and that the scaling down of supply voltage and increasing frequency help improve certain aspects of the noise immunity of dynamic circuit. Most of the work treated noise immunity and the noise content separately. This paper introduces a positive analysis of noise scalability by looking at the noise immunity and the noise content simultaneously.

A variable threshold voltage keeper circuit technique is proposed for simultaneous power reduction and speed enhancement of domino logic circuits. The threshold voltage of the keeper transistor is dynamically modified during circuit operation to reduce the contention current without sacrificing noise immunity. A four-bit multiple-output domino carry generator for a carry lookahead adder is designed with the proposed circuit technique. It is shown that the variable threshold voltage keeper circuit technique enhances the circuit evaluation speed by up to 60% while reducing power dissipation by 37% as compared to a standard domino logic circuit. It is also shown that the proposed domino logic circuit technique offers 20% higher noise immunity as compared to a standard domino circuit with the same evaluation delay characteristics.

Dynamic logic is susceptible to noise, especially in the ultra-deep submicrometer dual threshold voltage technology. When the dual threshold voltage is applied to the domino logic, noise immunity must be carefully considered since the significant subthreshold current of the low threshold voltage transistor makes the dynamic node much more susceptible to noise. In the first part of this paper, we introduce a new keeper transistor sizing method to determine the optimal keeper transistor size in terms of speed, power, and noise immunity. With the use of data obtained by presimulation, it is unnecessary to simulate all the design corners corresponding to the feasible NMOS evaluation transistor size ranges to find the optimal keeper transistor size. HSPICE simulation results show that the proposed keeper transistor sizing method can be broadly applied to all the domino logic gates. In the second part of this paper, we propose a new dual threshold voltage domino logic synthesis with the keeper transistor sizing to minimize the power consumption while meeting delay and noise constraints. With the optimal keeper transistor size determined by the proposed keeper transistor sizing method, the dual threshold voltage assignment to domino logic can be simplified to the discrete threshold voltage selection. Experimental results for ISCAS85 benchmark circuits show significant savings on leakage power and active power.

Summary form only given. Scaling down of device sizes and supply voltage requires a commensurate scaling of transistor threshold voltage to maintain high performance. Such scaling leads to exponential increase in leakage current, decreased noise immunity for high speed circuits, and increased defects. In this tutorial we present design and test techniques to combat these problems in the deep sub-micron regime for bulk, SOI and future technologies. We consider the following issues in turn: 1. Device scaling and its impact on sub-threshold and gate leakage current, interconnects, and noise immunity. 2. Low voltage circuit design under high intrinsic leakage, leakage monitoring and control techniques, effective transistor stacking, multi-threshold CMOS, dynamic threshold CMOS, SOI implications. Design of low leakage data-paths and caches. 3. SOI design - comparison with bulk, logic and memory design, asynchronous design. 4. Copper, low k, and impact of low k on performance. 5. Future technologies - double gate fully depleted SOI, FIN FET, and 3D SOI. 6. Noise modeling and analysis for high-speed precharge-evaluate circuits such as domino. Noise tolerant circuit design styles - skewed CMOS, noise tolerant domino, layout styles for high noise immunity. 7. I/sub ddq/ testing of circuits with high intrinsic leakage /sub e/lta I/sub ddq/, two parameter tests. I/sub dd/ waveform analysis.

Dynamic CMOS logic circuits are used in modern VLSI circuits because of its high system performance and its performance is high due to higher speed over static CMOS circuit. However dynamic logic circuit has less noise immunity and increased leakage power dissipation. Increase in leakage current combine with reduced noise margin results in performance degradation of dynamic circuits. In this paper DOIND logic approach is proposed for domino logic which reduces the leakage current with minimum delay penalty. Simulation is performed at 70 nm technology node for a domino logic and DOIND logic buffer using tanner EDA tool. Simulation results shows that proposed DOIND approach decreases the leakage current 93.3%, static power 93.3% and static energy 86.66% at supply voltage 1.15V. Proposed circuit also improves dynamic power 60.78%, dynamic energy delay product (EDP) 62.18% and dynamic power delay product (PDP) 62.07% at 1.15V supply voltage.

A low swing domino logic technique is proposed to decrease power consumption without sacrificing noise immunity. With the proposed low swing domino logic circuit technique, active power consumption is reduced by up to 9.4% while improving the noise immunity by 2.6% as compared to standard domino logic circuits. It is also shown that by applying a low swing contention reduction technique, the power savings can be further increased by 6.7% while the delay can be improved by 8.6%. A simple and efficient dual threshold voltage (dual-Vt) circuit technique that incorporates low swing signals is also proposed. It is shown that the proposed dual-Vt technique reduces the standby leakage current by approximately 235 times while offering enhanced delay characteristics as compared to a standard low threshold voltage implementation.

A novel GaAs logic family, pseudodynamic latched logic (PDLL), is presented in this paper. It is composed of a dynamic circuit where the logic is performed and a static latch whose function is to permanently refresh the stored data on a dynamic node. Because of this hybrid structure, PDLL takes advantage of both static and dynamic families and thus, permits implementation of very complex structures with good speed-area power tradeoff. Moreover, the inclusion of the latch permits this class of logic family to be highly efficient for pipelined systems working even at high temperature without loss of data due to leakage currents. Barrel-shifters, programmable logic arrays (PLA's), and carry lookahead adders (CLA's) were verified by simulations demonstrating its feasibility for the development of high-performance very large scale integration (VLSI) systems.

We explore numerically the impact of additive Gaussian noise on the spatiotemporal dynamics of ring networks of nonlocally coupled chaotic maps. The local dynamics of network nodes is described by the logistic map, the Ricker map, and the Henon map. 2D distributions of the probability of observing chimera states are constructed in terms of the coupling strength and the noise intensity and for several choices of the local dynamics parameters. It is shown that the coupling strength range can be the widest at a certain optimum noise level at which chimera states are observed with a high probability for a large number of different realizations of randomly distributed initial conditions and noise sources. This phenomenon demonstrates a constructive role of noise in analogy with the effects of stochastic and coherence resonance and may be referred to as chimera resonance.