Low power technique in domino logic circuit

Background/Objectives: Domino logic designs are widely used owing to its high speed and less area. However, the on chip variation of the design becomes more severe on scaling down the technology nodes. Methods/Statistical analysis: This paper details the design of variation tolerant domino logic with novel keeper architecture which comprises of a stacked grounded keeper with a body-bias generator. Furthermore, this paper elaborates the process variation tolerance techniques and compares the proposed keeper style with the existing styles. The design and analysis are carried out on wide fan-in domino logic circuits using Cadence® Spectre and Monte Carlo simulations in ADE-XL environment Findings: The results demonstrate that the novel variation tolerant keeper has an advantage of less delay compared to the conventional keeper. Additionally, it offers lesser delay variability of 7.24% and 9.18% and power variability of 14.01% and 0.15% using 180nm and 45nm technology libraries. Improvements/Applications: The proposed architecture enables the domino logic circuits to be used in applications that require robust and fast processing.

A variable threshold voltage keeper circuit technique is proposed for simultaneous power reduction and speed enhancement of domino logic circuits. The threshold voltage of the keeper transistor is dynamically modified during circuit operation to reduce the contention current without sacrificing noise immunity. A four-bit multiple-output domino carry generator for a carry lookahead adder is designed with the proposed circuit technique. It is shown that the variable threshold voltage keeper circuit technique enhances the circuit evaluation speed by up to 60% while reducing power dissipation by 37% as compared to a standard domino logic circuit. It is also shown that the proposed domino logic circuit technique offers 20% higher noise immunity as compared to a standard domino circuit with the same evaluation delay characteristics.

Sleep switch dual threshold voltage domino logic with reduced subthreshold and gate oxide leakage current

As continue scaling down the transistor feature size subthreshold leakage current becomes major component of total power dissipation. This paper presents comparative analysis of different dynamic logic circuits for reducing subthreshold leakage current with improved performance in dynamic logic circuits. In this paper DOIND logic approach is proposed with and without body biasing of DOIND transistors for domino logic which reduces the leakage current with minimum delay penalty. Simulation is performed at 70 nm technology node for a different logic buffer using tanner EDA tool. Simulation results shows that reduction in leakage current by DOIND and reverse body biased (RBB) DOIND approaches are 89.72% and 89.35% respectively. Static power and energy for DOIND and RBB DOIND approaches are also improved by 45.46%, 37.07%, 45.28% and 8.66% respectively.

As compared to static logic, domino logic circuits are always preferable for high performance circuit designs because of their less number of transistor requirement and high operational speed. Due to the presence of charge sharing problem and less noise tolerance this logic is not broadly accepted for all logic designs. The desired output of the circuit can change with a little noise pulse in the input of domino logic. Domino logic circuit has two stages first is dynamic logic part which is followed by a static inverter. This static inverter consumes very less power and has high noise immunity. In this paper a novel circuit called current mirror footed domino logic has been proposed for CMOS domino logic. This proposed domino logic is noise tolerant and has low power consumption than the basic footed and footless domino logic styles. Unity noise gain (UNG) found is also good for this logic style as compared to the previous proposed logic styles.

With the scaling of the CMOS technology, domino logic circuits experience larger leakage currents, which affect their robustness and performance. The leakage can be compensated by using a properly sized PMOS keeper transistor, at the cost of circuit delay increase. Hence, it is expected that the performance improvement of domino logic will stop in future technology nodes, due to increased required keeper size to maintain robustness. In this paper, we will study different methods of keeper sizing for comparing the performance of CMOS-OR domino logic circuits designed using Predictive Technology models of 32nm, 22nm and 16nm CMOS technology nodes. The keeper size will be adjusted to obtain the same robustness (noise immunity) across the technology generations. With this method of keeper sizing across technology nodes, the simulation results shows that indeed the delay of a low fan-in domino circuit increases from 32nm to 22nm node and the domino circuits fail to operate at 16nm node. For a high fan-in domino gate, however, the delay reduces from 32nm to 22nm; and the circuit fails at 16nm.

A low swing domino logic technique is proposed to decrease power consumption without sacrificing noise immunity. With the proposed low swing domino logic circuit technique, active power consumption is reduced by up to 9.4% while improving the noise immunity by 2.6% as compared to standard domino logic circuits. It is also shown that by applying a low swing contention reduction technique, the power savings can be further increased by 6.7% while the delay can be improved by 8.6%. A simple and efficient dual threshold voltage (dual-Vt) circuit technique that incorporates low swing signals is also proposed. It is shown that the proposed dual-Vt technique reduces the standby leakage current by approximately 235 times while offering enhanced delay characteristics as compared to a standard low threshold voltage implementation.

For the design and manufacture of complex integrated circuits, control over the threshold voltage of the transistors is essential. In the present contribution, we present a non-invasive method to tune the threshold voltage of organic thin-film transistors after device assembly over a wide range without any significant degradation of the device characteristics. This is realized by incorporating a thin, chemically reactive siloxane layer bonded to the gate oxide. This results in threshold voltages of around 70 V in the as-prepared devices. By exposing a transistor modified in this way to ammonia at different concentrations, the threshold voltage can be tuned in steps of only a few volts. This treatment affects only the charge density at the semiconductor–dielectric interface, leaving the overall shape of the transistor characteristics and the charge-carrier mobility largely unaltered.

For high system performance in VLSI chips dynamic CMOS logic circuit techniques are used. As continue scaling down the dimension of transistors parameter variation becomes a serious issue in very deep sub-micron regime. The overall performance of any logic circuit reduces by increasing leakage current and variability of parameters in scaled device. To overcome the variability issue in sub-micron regime the design must be aware of variations. In this paper DOIND logic approach is proposed for domino logic to analyze the variability issue. This approach reduces leakage current as well as it reduces the variability issue with minimum delay penalty. Various process, voltage and temperature (PVT) variations are analyzed at 70 nm technology node for a domino logic and DOIND logic buffer using tanner EDA tool. Simulation result shows that DOIND approach has less affect of PVT variations as compare to domino logic circuit.

One of the major problem in cascading dynamic circuits is logic 1 to logic 0 transition which is solved by using a simple inverter at output named as domino logic. But in domino logic excess power dissipation is observed because of precharge propagation, which is solved by using pseudo dynamic buffer (PDB) model. Using PDB we can save almost 67% of power. While succeeding to stop precharge propagation in domino logic PDB allows logic 1 to logic 0 transitions, this may cause erroneous output while cascading. Here we proposed footed quasi resistance (FQR) model modified from PDB which is having advantages of PDB and can avoid logic 1 to logic 0 transitions at output. By using FQR we can get maximum of 57% power saving compared to domino logic, which is worthwhile to get faultless output in cascaded logic circuits. Simulation is carried out in 0.18µm technology node using Tanner EDA tool. Simulation results instance better performance of modified circuit over conventional and PDB at different frequencies, load capacitance and boolean functions.

Dynamic CMOS logic circuits are used in modern VLSI circuits because of its high system performance and its performance is high due to higher speed over static CMOS circuit. However dynamic logic circuit has less noise immunity and increased leakage power dissipation. Increase in leakage current combine with reduced noise margin results in performance degradation of dynamic circuits. In this paper DOIND logic approach is proposed for domino logic which reduces the leakage current with minimum delay penalty. Simulation is performed at 70 nm technology node for a domino logic and DOIND logic buffer using tanner EDA tool. Simulation results shows that proposed DOIND approach decreases the leakage current 93.3%, static power 93.3% and static energy 86.66% at supply voltage 1.15V. Proposed circuit also improves dynamic power 60.78%, dynamic energy delay product (EDP) 62.18% and dynamic power delay product (PDP) 62.07% at 1.15V supply voltage.

The dynamic circuits are supposed to offer superior speed and low power dissipation over static CMOS circuits. The domino logic circuits are used for high system performance but suffer from the precharge pulse degradation. This article provides different design topologies on the domino circuits to overcome the charge sharing and charge leakage with reference to the power dissipation and delay. The precharge keeper circuit has been proposed such that the keeper transistors also work as the precharge transistors to realize multiple output function. The performance improvement of the circuit’s analysis have been done for adders and logic gates using HSPICE tool. The proposed keeper techniques reveal lower power dissipation and lesser delay over the standard keeper circuit with less transistor count for different process variation.

Gated body-biased full adder

Domino CMOS Circuits are significantly used in high performance very large scale integrated (VLSI) system. Designing a low power with high speed performance VLSI circuit is one of the challenging aspects. Full adder is one of the basic blocks for many circuits for multiplication, division and exponentiation operation. This paper proposed a low power with high speed performance 1-bit full adder using domino approach and also shows a comparative analysis of proposed full adder with other full adder using static approach. The simulations are carried out by TANNER EDA tool using PTM 90nm technology node with 1.1V supply voltage. The results show that the proposed 22T domino full adder consume 54.74% less power as compared to 10T static full adder, 54.35% less power consumed as compared to domino 27T full adder and 3.2% less power consumed as compared to 28T static full adder. The results also depict that the speed of a proposed 22T domino full adder is much faster in comparison to 28T static full adder by 68.163%, 1.70% faster as compared to 27T domino full adder and 99% faster as compared to 10T static full adder.

We introduce a new dual threshold voltage technique for domino logic. Since domino logic is much more sensitive to noise, noise margins have to be taken into account when applying dual threshold voltages to domino logic. To guarantee the signal integrity in domino logic, we carefully consider the effect of transistor sizing and threshold voltage selection. For optimal design, tradeoffs need to be mad? among noise margin, power, and performance. Based on the characteristics of each logic gate, we propose noise and power constrained domino logic synthesis for high performance. ISCAS85 benchmark re sults show that performance can be improved up to 18.62%, with 2% active power increase, while maintaining noise margin.