Stack Contention-alleviated Precharge Keeper for Pseudo Domino Logic

A variable threshold voltage keeper circuit technique is proposed for simultaneous power reduction and speed enhancement of domino logic circuits. The threshold voltage of the keeper transistor is dynamically modified during circuit operation to reduce the contention current without sacrificing noise immunity. A four-bit multiple-output domino carry generator for a carry lookahead adder is designed with the proposed circuit technique. It is shown that the variable threshold voltage keeper circuit technique enhances the circuit evaluation speed by up to 60% while reducing power dissipation by 37% as compared to a standard domino logic circuit. It is also shown that the proposed domino logic circuit technique offers 20% higher noise immunity as compared to a standard domino circuit with the same evaluation delay characteristics.

Dynamic CMOS logic circuits are used in modern VLSI circuits because of its high system performance and its performance is high due to higher speed over static CMOS circuit. However dynamic logic circuit has less noise immunity and increased leakage power dissipation. Increase in leakage current combine with reduced noise margin results in performance degradation of dynamic circuits. In this paper DOIND logic approach is proposed for domino logic which reduces the leakage current with minimum delay penalty. Simulation is performed at 70 nm technology node for a domino logic and DOIND logic buffer using tanner EDA tool. Simulation results shows that proposed DOIND approach decreases the leakage current 93.3%, static power 93.3% and static energy 86.66% at supply voltage 1.15V. Proposed circuit also improves dynamic power 60.78%, dynamic energy delay product (EDP) 62.18% and dynamic power delay product (PDP) 62.07% at 1.15V supply voltage.

As compared to static logic, domino logic circuits are always preferable for high performance circuit designs because of their less number of transistor requirement and high operational speed. Due to the presence of charge sharing problem and less noise tolerance this logic is not broadly accepted for all logic designs. The desired output of the circuit can change with a little noise pulse in the input of domino logic. Domino logic circuit has two stages first is dynamic logic part which is followed by a static inverter. This static inverter consumes very less power and has high noise immunity. In this paper a novel circuit called current mirror footed domino logic has been proposed for CMOS domino logic. This proposed domino logic is noise tolerant and has low power consumption than the basic footed and footless domino logic styles. Unity noise gain (UNG) found is also good for this logic style as compared to the previous proposed logic styles.

As continue scaling down the transistor feature size subthreshold leakage current becomes major component of total power dissipation. This paper presents comparative analysis of different dynamic logic circuits for reducing subthreshold leakage current with improved performance in dynamic logic circuits. In this paper DOIND logic approach is proposed with and without body biasing of DOIND transistors for domino logic which reduces the leakage current with minimum delay penalty. Simulation is performed at 70 nm technology node for a different logic buffer using tanner EDA tool. Simulation results shows that reduction in leakage current by DOIND and reverse body biased (RBB) DOIND approaches are 89.72% and 89.35% respectively. Static power and energy for DOIND and RBB DOIND approaches are also improved by 45.46%, 37.07%, 45.28% and 8.66% respectively.

Sleep switch dual threshold voltage domino logic with reduced subthreshold and gate oxide leakage current

Background/Objectives: Domino logic designs are widely used owing to its high speed and less area. However, the on chip variation of the design becomes more severe on scaling down the technology nodes. Methods/Statistical analysis: This paper details the design of variation tolerant domino logic with novel keeper architecture which comprises of a stacked grounded keeper with a body-bias generator. Furthermore, this paper elaborates the process variation tolerance techniques and compares the proposed keeper style with the existing styles. The design and analysis are carried out on wide fan-in domino logic circuits using Cadence® Spectre and Monte Carlo simulations in ADE-XL environment Findings: The results demonstrate that the novel variation tolerant keeper has an advantage of less delay compared to the conventional keeper. Additionally, it offers lesser delay variability of 7.24% and 9.18% and power variability of 14.01% and 0.15% using 180nm and 45nm technology libraries. Improvements/Applications: The proposed architecture enables the domino logic circuits to be used in applications that require robust and fast processing.

With the scaling of the CMOS technology, domino logic circuits experience larger leakage currents, which affect their robustness and performance. The leakage can be compensated by using a properly sized PMOS keeper transistor, at the cost of circuit delay increase. Hence, it is expected that the performance improvement of domino logic will stop in future technology nodes, due to increased required keeper size to maintain robustness. In this paper, we will study different methods of keeper sizing for comparing the performance of CMOS-OR domino logic circuits designed using Predictive Technology models of 32nm, 22nm and 16nm CMOS technology nodes. The keeper size will be adjusted to obtain the same robustness (noise immunity) across the technology generations. With this method of keeper sizing across technology nodes, the simulation results shows that indeed the delay of a low fan-in domino circuit increases from 32nm to 22nm node and the domino circuits fail to operate at 16nm node. For a high fan-in domino gate, however, the delay reduces from 32nm to 22nm; and the circuit fails at 16nm.

A low swing domino logic technique is proposed to decrease power consumption without sacrificing noise immunity. With the proposed low swing domino logic circuit technique, active power consumption is reduced by up to 9.4% while improving the noise immunity by 2.6% as compared to standard domino logic circuits. It is also shown that by applying a low swing contention reduction technique, the power savings can be further increased by 6.7% while the delay can be improved by 8.6%. A simple and efficient dual threshold voltage (dual-Vt) circuit technique that incorporates low swing signals is also proposed. It is shown that the proposed dual-Vt technique reduces the standby leakage current by approximately 235 times while offering enhanced delay characteristics as compared to a standard low threshold voltage implementation.

High performance circuits demands domino logic design. A new technique for reducing the power consumption and increasing the speed without effecting noise margin is reviewed in this paper. In this technique threshold voltage of the keeper transistor is varied using body bias generator circuit. Three different body bias generator circuits are simulated, they are dynamic body bias generator, capacitive body bias generator and cross couple capacitive body bias generator circuit. Simulations are performed on tanner EDA tool at 180 nm and 65nm technology, for carry look ahead adder. The simulation results show that CBBG and CCCBBG have reduced power consumption and delay in comparison to other circuit techniques.

For high system performance in VLSI chips dynamic CMOS logic circuit techniques are used. As continue scaling down the dimension of transistors parameter variation becomes a serious issue in very deep sub-micron regime. The overall performance of any logic circuit reduces by increasing leakage current and variability of parameters in scaled device. To overcome the variability issue in sub-micron regime the design must be aware of variations. In this paper DOIND logic approach is proposed for domino logic to analyze the variability issue. This approach reduces leakage current as well as it reduces the variability issue with minimum delay penalty. Various process, voltage and temperature (PVT) variations are analyzed at 70 nm technology node for a domino logic and DOIND logic buffer using tanner EDA tool. Simulation result shows that DOIND approach has less affect of PVT variations as compare to domino logic circuit.

Dynamic logic is much susceptible to noise specially in ul tra deep submicron technology The keeper transistor has to be carefully sized to maintain noise margin without much speed penalty In this paper we analyze the keeper tran sistor sizing with respect to the size of NMOS transistors in the evaluation tree Based on the analytical results we propose a keeper transistor sizing method HSPICE simula tion results show that the proposed keeper transistor sizing method can be broadly applied to all domino logic gates

Dual‐rail dynamic logic circuits can provide inverting and noninverting outputs, especially for asynchronous designs, to implement complicated gates at the cost of approximately doubling the area and power consumption. In this paper, a new dual‐rail dynamic circuit is proposed which has lower die area consumption and higher noise immunity without dramatic speed degradation for even wide fan‐in gates for asynchronous circuits. The main idea in the proposed circuit is that voltage due to the current of the pulldown network (PDN) is compared with the reference voltage to provide two complementary outputs. The reference voltage almost corresponds to the leakage current of the PDN with all transistors being off. The proposed circuit is compared with conventional dual‐rail circuits such as differential domino logic and differential cross‐coupled domino logic. Simulation results for 32‐bit‐wide OR gates designed using high‐performance 16‐nm predictive technology model demonstrate significant performance advantages such as 66% power reduction and at least 2.86× noise‐immunity improvement at the same delay compared to the differential domino circuits. © 2012 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.

The following investigation on flip-flop circuits was originally undertaken to determine if a reliable flip-flop circuit could be designed to operate from a low supply voltage using tubes that are presently available and in production. The reason for designing the circuit to operate from a low supply voltage is to reduce the required power consumption of such information storage devices to a minimum and to provide a low d-c level output. The low d-c level output voltages of the two stable states of the circuit and the low flip-flop power dissipation enables an entire computer to operate from one regulated power supply rather than the numerous regulated supplies required by most computers. The low power dissipation is also essential since the reliability of germanium diodes and other heat sensitive components is greatly increased as their operating temperature is decreased.

The errorless data transmission in optimal communication depends on flaw identification and renewal techniques. In one bit error identification and error modification codes the hamming code is mostly used, because of its efficiency. To increase performance, system capability we need the low power design. To reduce the rate of information loss and power dissipation the reversible logic is well suited. When a reversible logic gates used in the design of hamming code, in place of irreversible logic gates gives low power dissipation, which identify and modify the error if any. In this document we construct the hamming code using the FinFET technique, because of its capability of operating at lower supply voltages and it is suppress the short channel effects in sub-micron region, through this documentation we represent the propagation delay values. The transient responses are taken by using cadence virtuoso. The power consumption of overall design is 0.48□W.

Device scaling is a pivotal aspect in the field of electronics, aimed at enhancing the performance of integrated circuits (ICs) by reducing the dimensions of transistors. The device scaling presents the short channel effects (SCEs) in the nanoscale regime. To address the SCEs, nanometer IC designers have turned to the carbon nanotube field-effect transistor (CNTFET) technology, which offers unique properties and mitigates the challenges associated with transistor scaling. In this research work, a leakage reduction technique known as the input-dependent (INDEP) method is suggested to tackle the leakage current issue at the nanoscale regime using CNTFET technology. The INDEP method involves the incorporation of two additional transistors within the logic circuit. To evaluate the efficacy of the INDEP method, a CNTFET-based 7-stage inverter chain is meticulously designed at 32 nm CNTFET technology node. Subsequent comparative analysis against alternative designs is conducted, assessing performance metrics such as power dissipation, delay, and power delay product (PDP). The suggested INDEP method reduces power dissipation by 83.75% and improves PDP by 78.44%. Furthermore, the study delves into the impact of process, voltage, and temperature (PVT) variations. Additionally, the investigation explores the influence of parameters such as the number of carbon nanotubes, temperature, supply voltage, and chiral indices on the performance of the 7-stage inverter chain. The simulation results demonstrate that the CNTFET-based INDEP technique yields promising outcomes, characterized by low power dissipation, precise output, and minimal uncertainty across all evaluated metrics.