Low Power SEC-DED Hamming Code Using Reversible Logic

Reversible logic gate has gained importance in recent times due to its low power dissipation and less information loss. QCA on the other hand has low power consumption and has applications in reversible logic. In this paper, a 4×2 priority encoder is proposed which is based on reversible logic implemented in QCA. Firstly, this paper discusses about QCA layout design of Fredkin gate and Universal Reversible Logic Gate (URLG). Secondly, this paper uses reversible logic gate (both Fredkin and URLG) to design a 4×2 priority encoder in QCA.

Quantum-dot Cellular Automata (QCA) is a newly developed paradigm for digital design. It explains how computation can be performed using nano sized quantum dots. One of the trending application of QCA is the design of reversible logic circuits and gates. Reversible logic is a dissipation less digital logic. According to this logic digital circuitry with almost zero power dissipation can be designed. The most important application of reversible logic is quantum computing. Quantum Computation cannot be performed without the use of reversible circuits. A number of reversible gates have been designed and used in quantum computing. The best way to derive the maximum out of reversible computation is to design those gates and circuits using systems which are inherently reversible. This is true for the quantum mechanical systems. For this quantum level designing Quantum-dot Cellular Automata stands as the appropriate choice. It's a nano level based archetype. Performing multiple functions using single circuits has always been the aim of the digital industry researchers. In reversible logic the approach is developing towards designing multifunction gates that can perform a number of functions using a same circuit with some adjustments. This development has however not yet been explored much in QCA. In this paper the majority logic equations for the outputs of a multifunction reversible logic gate are derived and the novel Quantum-dot Cellular Automata design is proposed. Some of the functions of multifunction reversible logic gate are discussed and simulated results using QCA Designer 2.0.3 are shown in the figure.

Heat is an important issue in VLSI circuits. But the reversible logic gives zero amount of heat dissipation. So, its an important role in nanotechnology, less energy complementary metal oxide semiconductor [CMOS] designs etc. It has been realized that quantum computing is one of the latest technologies using reversible logic gates. It is contemplating that accumulation extension of transistor density, energy desolation will command their limits in ordinary technologies. In ordinary area or range during the logic influence bits of orientation is erased resulting gratification of power in powerful amount. In the terms of reversible logic results are not lost.[1] This minimize the delays but at the amount of little hardware. So we can use reversible logic technology for decreasing the energy dispersion, heatwave dissipation, increasing rapidness etc. So it is used to maximize the speed and reducing energy consumption. In this, we can describe following reversible logic gates like fredkin, peres, Feynmen and toffoli gate etc.

Reversible logic has various applications in fields of computer graphics, optical information processing, quantum computing, DNA computing, ultra low power CMOS design and communication. As our day to day life is demanding more and more portable electronic devices, challenging focus on technology is demanding great system performance without any compromise in power consumption. It is obvious to find tradeoff between processing power and heat generation. As decreased processing speed leads to reduced power consumption but obviously compromise in performance is not acceptable for sophisticated applications. Thus power consumption is a prime target now days. Needless to say, researchers will now look at reversible logic in this vein. Primitive component of reversible logic synthesis are reversible logic gates. Thus it is very important for a new researcher to look into extensive literature survey of reversible logic gates. Many papers have been reported with review of reversible logic gates. This paper aims on updates in reversible logic gates which are stepping stones in design and synthesis of any complex reversible logic based synthesis.

Reversible logic has various applications in fields of computer graphics, optical information processing, quantum computing, DNA computing, ultra low power CMOS design and communication. As our day to day life is demanding more and more portable electronic devices, challenging focus on technology is demanding great system performance without any compromise in power consumption. It is obvious to find tradeoff between processing power and heat generation. As decreased processing speed leads to reduced power consumption but obviously compromise in performance is not acceptable for sophisticated applications. Thus power consumption is a prime target now days. Needless to say, researchers will now look at reversible logic in this vein. Primitive component of reversible logic synthesis are reversible logic gates .Thus it is very important for a new researcher to look into extensive literature survey of reversible logic gates. Many papers have been reported with review of reversible logic gates. This paper aims on updates in reversible logic gates and propose a novel reversible DS gate which will be stepping stone in design and synthesis of any complex reversible logic based synthesis.

Reversibility is the prominent technology in the recent era. In reversible logic the number output lines are equal to the number of input lines. In reversible logic the inputs are to be retrieved from the outputs. Reversible logic gates are user defined gates. Reversible logic owns its applications in various fields which include low power VLSI. In this paper multiplexer is implemented using QCA, SAM and QCA & SAM gate. Also demultiplexer is implemented using two new reversible logic gates RAMESH and RAMESH-1 gates. These designs are simulated and synthesized using Xilinx ISE 12.1 and Mentor Graphics tool. The result shows that the proposed designs are more efficient in terms of gate count, quantum cost and power consumption.

Irreversible logic operations inevitably discard information, setting fundamental limitations on the flexibility and the efficiency of modern computation. To circumvent the limit imposed by the von Neumann-Landauer (VNL) principle, an important objective is the development of reversible logic gates, as proposed by Fredkin, Toffoli, Wilczek, Feynman, and others. Here, we present a novel nanomechanical logic architecture for implementing a Fredkin gate, a universal logic gate from which any reversible computation can be built. In addition to verifying the truth table, we demonstrate operation of the device as an AND, OR, NOT, and FANOUT gate. Excluding losses due to resonator dissipation and transduction, which will require significant improvement in order to minimize the overall energy cost, our device requires an energy of order 10(4) kT per logic operation, similar in magnitude to state-of-the-art transistor-based technologies. Ultimately, reversible nanomechanical logic gates could play a crucial role in developing highly efficient reversible computers, with implications for efficient error correction and quantum computing.

Reversible logic is emerging as a promising alternative for applications in low-power design and quantum computation in recent years due to its ability to reduce power dissipation, which is an important research area in low power VLSI and ULSI designs. Many important contributions have been made in the literatures towards the reversible implementations of arithmetic and logical structures; however, there have not been many efforts directed towards efficient approaches for designing reversible Arithmetic Logic Unit (ALU). In this study, three efficient approaches are presented and their implementations in the design of reversible ALUs are demonstrated. Three new designs of reversible one-digit arithmetic logic unit for quantum arithmetic has been presented in this article. This paper provides explicit construction of reversible ALU effecting basic arithmetic operations with respect to the minimization of cost metrics. The architectures of the designs have been proposed in which each block is realized using elementary quantum logic gates. Then, reversible implementations of the proposed designs are analyzed and evaluated. The results demonstrate that the proposed designs are cost-effective compared with the existing counterparts. All the scales are in the NANO-metric area.

The following investigation on flip-flop circuits was originally undertaken to determine if a reliable flip-flop circuit could be designed to operate from a low supply voltage using tubes that are presently available and in production. The reason for designing the circuit to operate from a low supply voltage is to reduce the required power consumption of such information storage devices to a minimum and to provide a low d-c level output. The low d-c level output voltages of the two stable states of the circuit and the low flip-flop power dissipation enables an entire computer to operate from one regulated power supply rather than the numerous regulated supplies required by most computers. The low power dissipation is also essential since the reliability of germanium diodes and other heat sensitive components is greatly increased as their operating temperature is decreased.

Reversible logic has represented itself as a prominent technology which plays an important role in Quantum Computing. Theoretically Quantum Computers operates at high speed and consumes less power. Furthermore, Reversible logic can break the conventional speed of power trade-off. To prove this we are implementing Ripple Carry Adder and Carry Look Ahead Adder using reversible logic gates. The paper presents efficient adder circuits using Peres gate, New fault Tolerant gate and Double Feyman gate. The complexity, simulated outputs and the speed parameters for the adder circuit have been indicated using the Quartus II 9.1 edition and Modelsim tool. Moreover, the quantum algorithms can potentially solve NP-complete problems. Furthermore, doing high performance functions beyond the limit of deterministic computer systems is possible by only reversible logic. Quantum operations are unitary in nature which is reversible and hence the arithmetic operations like adders can be implemented using the reversible logic. Likewise, optimized block size, minimum ancillary bits, and one to one mappings of inputs and outputs are obtained in the reversible adder circuit, giving fan out as 1. Hence, the Ripple Carry Adder and Carry look Ahead Adder is providing complexity reduction and high speed, proving to be an efficient and important part in the development of arithmetic blocks of Quantum Computers.

A communication system is implemented as quantum-dot cellular automata. The advance method of Nano technology is Quantum-dot cellular automata (QCA). QCA is a promising alternative to the current CMOS technology. It can be implemented at the Nano scale, reaching ultra-low power consumption. Communication systems are important in current computer systems and it is expected to be even more important in near future. In a bottom-up approach, the Parallel-to-Serial and Serial-to-Parallel converters were described, which are essential to the serial communication. The components for robust communication, such as QCA circuits for Hamming code and Parity Checker are used. The coplanar QCA crossover architecture is used in the design of QCA that leads to the reduction of QCA cell count and area consumption. Reversible Logic design is also used. Reversible logic is found to be Low power design which becomes emerging technology in Low power Nanotechnology era. In this work they devoted to design a Reversible Logic Gate which is a universal gate and can be design with alternative of co-planer cross over wire. They introduce a passive type 3×3 tile that will also helpful for design the co-planner crossover wire.

In today’s technology, Parallel Prefix Adders is widely used in VLSI to get higher delay performance. The demand for adders that use reversible logic gates is growing every day as technology advances. However, since reversible logic gates have no information loss, reversible circuits consume less heat than conventional circuits. Reversible logic gates along with extra characteristics that input parity and output parity are equal is termed as PPRLG (parity preserving reversible logic gates). This characteristic allows any device to function normally even if any intermediary nodes fail. The Brent-Kung adder offers a faster response time as compared to many adders. As a consequence, designing an extremely fast, fault-tolerable, and low-power adder immediately results in increased device speed for quicker computing purposes, so Brent Kung adder with the help of PPRLG is presented in our work. The suggested Adder implementation is done using Verilog programming language in the Xilinx software with version 14.7. For the purpose of demonstration of its quality, presented Parity Preserving Reversible Adder, including many sub-parts, we used a number of parameters like Quantum-Cost, CI, GC, and Unused Output, including the schematic (Register Transfer Level) of the Brent-Kung Adder and its sub-parts. So yet, no Brent-Kung adder circuit employing Reversible Logic Gates with Fault-Tolerant capabilities has been suggested, to the best of our knowledge.

High-performance computing beyond sub-10 nm advanced node technology allows us to explore and use complex 2.5D/3D SOC design architecture. Node scaling, heterogeneous integration, and complex design enable us to think beyond Moore’s law but, at the same time, limit the scope with concerns of excessive power dissipation. The field of quantum computation and reversible logic functions has been researched in recent years in the context of low power VLSI circuit designs and nanotechnology. Reversible computation exhibits significantly reduced power dissipation in digital circuits. In this paper, we propose a novel design of Artificial Neural Network (ANN) using reversible logic gates. A thorough search of the relevant literature yielded only a few related articles. To the best of our knowledge, our proposed approach is the first attempt to implement a complete feedforward neural network circuit using only reversible logic gates. The comparative analysis demonstrates that our proposed approach has achieved an approximately 16% reduction in overall power dissipation compared to existing approaches. The proposed approach also has better scalability than the classical design approach.

Any sequential learning task relies on the idea of connecting previous time-stamp information to the immediate present time-stamp task to predict the future. The underlying challenge is to understand the hidden patterns in the sequence by means of analyzing short- and long-term dependencies and temporal differences. Recurrent Neural Networks (RNNs) and their variants, such as Long Short-Term Memory (LSTM) are widely used in problem domains like speech recognition, Natural Language Processing (NLP), fault prediction, and language translation modeling over the past few years. Higher accuracy demands complex LSTM network models which lead to high computational cost, area overhead, and excessive power consumption. Reversible logic circuit synthesis, in the context of ideally Zero heat dissipation, has emerged as a new research paradigm for low power circuit designs. In this paper, we have proposed a novel design of LSTM architecture using reversible logic gates. To the best of our knowledge, the proposed approach is the first attempt to implement a complete feedforward LSTM circuit using only reversible logic gates. The hardware implementation of the proposed method is presented using VHDL and Altera Arria10 GX FPGA. The comparative analysis demonstrates that the proposed approach has achieved an approximately 17% reduction in overall power dissipation compared to traditional networks. The proposed approach also has better scalability than the classical design approach.

FPGA Implementation Of Dynamic Power, Area Optimized Reversible ALU For Various DSP Applications